Seiko Epson S1C17153 User manual

Rev. 1.0
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17153
Technical Manual

©
SEIKO EPSON CORPORATION 2013, All rights reserved.
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical prod-
ucts. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation
or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. When exporting the products or technology described in this material, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to
export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or
manufacture of weapon of mass destruction or for other military purposes.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

Devices
S1 C 17xxx F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA, WCSP
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 17000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx: Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Yx : Writer software
Corresponding model number
17xxx: for S1C17xxx
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number
CONFIGURATION OF PRODUCT NUMBER
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.0)
Configuration of product number

CONTENTS
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.0)
– Contents –
1 Overview........................................................................................................................1-1
1.1 Features ...........................................................................................................................1-1
1.2 Block Diagram..................................................................................................................1-2
1.3 Pads .................................................................................................................................1-3
1.3.1 Pad Configuration Diagram................................................................................1-3
1.3.2 Pin Descriptions.................................................................................................1-5
2 CPU................................................................................................................................2-1
2.1 Features of the S1C17 Core ............................................................................................2-1
2.2 CPU Registers .................................................................................................................2-2
2.3 Instruction Set ..................................................................................................................2-2
2.4 Reading PSR ...................................................................................................................2-5
2.5 Processor Information ......................................................................................................2-6
3 Memory Map, Bus Control ...........................................................................................3-1
3.1 Bus Cycle .........................................................................................................................3-1
3.1.1 Restrictions on Access Size...............................................................................3-2
3.1.2 Restrictions on Instruction Execution Cycles.....................................................3-2
3.2 Internal ROM Area ...........................................................................................................3-2
3.2.1 Embedded ROM ................................................................................................3-2
3.2.2 ROM Read Wait Cycle Setting ..........................................................................3-2
ROMC Read Wait Control Register (ROMC_WAIT) .................................................................. 3-2
3.3 Internal RAM Area............................................................................................................3-3
3.3.1 Embedded RAM ................................................................................................3-3
3.4 Display RAM area ............................................................................................................3-3
3.5 Internal Peripheral Area ...................................................................................................3-3
3.5.1 Internal Peripheral Area 1 (0x4000–).................................................................3-3
3.5.2 Internal Peripheral Area 2 (0x5000–).................................................................3-3
3.6 S1C17 Core I/O Area .......................................................................................................3-4
4 Power Supply ................................................................................................................4-1
4.1 Power Supply Voltage (VDD) .............................................................................................4-1
4.2 Internal Power Supply Circuit...........................................................................................4-1
4.2.1 VD1 Regulator.....................................................................................................4-1
4.2.2 LCD Power Supply Circuit..................................................................................4-1
4.2.3 Heavy Load Protection Mode.............................................................................4-2
4.3 Control Register Details ...................................................................................................4-3
LCD Booster Clock Control Register (LCD_BCLK)................................................................... 4-3
LCD Voltage Regulator Control Register (LCD_VREG) ............................................................ 4-4
VD1 Control Register (VD1_CTL)............................................................................................... 4-5
5 Initial Reset ...................................................................................................................5-1
5.1 Initial Reset Sources ........................................................................................................5-1
5.1.1 #RESET Pin.......................................................................................................5-1
5.1.2 P0 Port Key-Entry Reset ...................................................................................5-1
5.1.3 Resetting by the Watchdog Timer ......................................................................5-1
5.2 Initial Reset Sequence .....................................................................................................5-2
5.3 Initial Settings After an Initial Reset ................................................................................5-2
6 Interrupt Controller (ITC) .............................................................................................6-1
6.1 ITC Module Overview.......................................................................................................6-1

CONTENTS
ii Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
6.2 Vector Table......................................................................................................................6-2
Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH).............................. 6-3
6.3 Control of Maskable Interrupts .........................................................................................6-3
6.3.1 Interrupt Control Bits in Peripheral Modules ......................................................6-3
6.3.2 ITC Interrupt Request Processing .....................................................................6-3
6.3.3 Interrupt Processing by the S1C17 Core ...........................................................6-4
6.4 NMI...................................................................................................................................6-4
6.5 Software Interrupts...........................................................................................................6-4
6.6 HALT and SLEEP Mode Cancellation ..............................................................................6-5
6.7 Control Register Details ...................................................................................................6-5
Interrupt Level Setup Register x(ITC_LVx) ............................................................................... 6-5
7 Clock Generator (CLG).................................................................................................7-1
7.1 CLG Module Overview .....................................................................................................7-1
7.2 CLG Input/Output Pins .....................................................................................................7-2
7.3 Oscillators ........................................................................................................................7-2
7.3.1 OSC3B Oscillator...............................................................................................7-2
7.3.2 OSC1A Oscillator...............................................................................................7-3
7.4 System Clock Switching...................................................................................................7-5
7.5 CPU Core Clock (CCLK) Control .....................................................................................7-6
7.6 Peripheral Module Clock (PCLK) Control.........................................................................7-6
7.7 Clock External Output (FOUTA, FOUTB).........................................................................7-7
7.8 Control Register Details ...................................................................................................7-8
Clock Source Select Register (CLG_SRC) ............................................................................... 7-8
Oscillation Control Register (CLG_CTL) ................................................................................... 7-9
FOUTA Control Register (CLG_FOUTA) .................................................................................. 7-10
FOUTB Control Register (CLG_FOUTB) ................................................................................. 7-11
Oscillation Stabilization Wait Control Register (CLG_WAIT) .................................................... 7-11
PCLK Control Register (CLG_PCLK)....................................................................................... 7-12
CCLK Control Register (CLG_CCLK)....................................................................................... 7-13
8 Real-Time Clock (RTC).................................................................................................8-1
8.1 RTC Module Overview .....................................................................................................8-1
8.2 RTC Counters ..................................................................................................................8-1
8.3 RTC Control .....................................................................................................................8-3
8.3.1 Operating Clock Control.....................................................................................8-3
8.3.2 12-hour/24-hour mode selection .......................................................................8-3
8.3.3 RTC Start/Stop ..................................................................................................8-3
8.3.4 Counter Settings ................................................................................................8-3
8.3.5 Counter Read ....................................................................................................8-4
8.4 RTC Interrupts..................................................................................................................8-5
8.5 Control Register Details ...................................................................................................8-5
RTC Control Register (RTC_CTL)............................................................................................. 8-5
RTC Interrupt Enable Register (RTC_IEN)................................................................................ 8-6
RTC Interrupt Flag Register (RTC_IFLG).................................................................................. 8-7
RTC Minute/Second Counter Register (RTC_MS).................................................................... 8-8
RTC Hour Counter Register (RTC_H) ....................................................................................... 8-9
9 I/O Ports (P)...................................................................................................................9-1
9.1 P Module Overview ..........................................................................................................9-1
9.2 Input/Output Pin Function Selection (Port MUX)..............................................................9-2
9.3 Data Input/Output.............................................................................................................9-2
9.4 Pull-up Control .................................................................................................................9-3
9.5 Port Input Interrupt ...........................................................................................................9-3

CONTENTS
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation iii
(Rev. 1.0)
9.6 P0 Port Chattering Filter Function....................................................................................9-4
9.7 P0 Port Key-Entry Reset .................................................................................................9-5
9.8 Control Register Details ...................................................................................................9-5
PxPort Input Data Registers (Px_IN)........................................................................................ 9-5
PxPort Output Data Registers (Px_OUT) ................................................................................. 9-6
PxPort Output Enable Registers (Px_OEN) ............................................................................. 9-6
PxPort Pull-up Control Registers (Px_PU) ............................................................................... 9-6
P0 Port Interrupt Mask Register (P0_IMSK).............................................................................. 9-7
P0 Port Interrupt Edge Select Register (P0_EDGE) ................................................................. 9-7
P0 Port Interrupt Flag Register (P0_IFLG)................................................................................ 9-7
P0 Port Chattering Filter Control Register (P0_CHAT).............................................................. 9-8
P0 Port Key-Entry Reset Configuration Register (P0_KRST) ................................................... 9-9
PxPort Input Enable Registers (Px_IEN).................................................................................. 9-9
P0[3:0] Port Function Select Register (P00_03PMUX) ............................................................ 9-10
P0[7:4] Port Function Select Register (P04_07PMUX) ............................................................ 9-11
P1[3:0] Port Function Select Register (P10_13PMUX) ............................................................ 9-12
10 8-bit Timer (T8)...........................................................................................................10-1
10.1 T8 Module Overview .....................................................................................................10-1
10.2 Count Clock...................................................................................................................10-2
10.3 Count Mode...................................................................................................................10-2
10.4 Reload Data Register and Underflow Cycle..................................................................10-2
10.5 Timer Reset...................................................................................................................10-3
10.6 Timer RUN/STOP Control .............................................................................................10-3
10.7 T8 Output Signals..........................................................................................................10-4
10.8 T8 Interrupts..................................................................................................................10-4
10.9 Control Register Details ................................................................................................10-5
T8 Ch.xCount Clock Select Register (T8_CLKx)..................................................................... 10-5
T8 Ch.xReload Data Register (T8_TRx) ................................................................................. 10-5
T8 Ch.xCounter Data Register (T8_TCx)................................................................................ 10-6
T8 Ch.xControl Register (T8_CTLx)........................................................................................ 10-6
T8 Ch.xInterrupt Control Register (T8_INTx) .......................................................................... 10-7
11 16-bit PWM Timer (T16A2).........................................................................................11-1
11.1 T16A2 Module Overview ...............................................................................................11-1
11.2 T16A2 Input/Output Pins...............................................................................................11-2
11.3 Count Clock...................................................................................................................11-2
11.4 T16A2 Operating Modes ...............................................................................................11-3
11.4.1 Comparator Mode and Capture Mode ............................................................11-4
11.4.2 Repeat Mode and One-Shot Mode.................................................................11-5
11.4.3 Normal Clock Mode and Half Clock Mode......................................................11-5
11.5 Counter Control ............................................................................................................11-6
11.5.1 Counter Reset.................................................................................................11-6
11.5.2 Counter RUN/STOP Control ...........................................................................11-6
11.5.3 Reading Counter Values .................................................................................11-6
11.5.4 Counter Operation and Interrupt Timing Charts..............................................11-7
11.6 Timer Output Control.....................................................................................................11-7
11.7 T16A2 Interrupts............................................................................................................11-9
11.8 Control Register Details ...............................................................................................11-11
T16A Clock Control Register Ch.x(T16A_CLKx).................................................................... 11-11
T16A Counter Ch.xControl Register (T16A_CTLx) ................................................................ 11-12
T16A Counter Ch.xData Register (T16A_TCx) ...................................................................... 11-14
T16A Comparator/Capture Ch.xControl Register (T16A_CCCTLx) ....................................... 11-14
T16A Comparator/Capture Ch.xA Data Register (T16A_CCAx)............................................ 11-16
T16A Comparator/Capture Ch.xB Data Register (T16A_CCBx)............................................ 11-16

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iv Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
T16A Comparator/Capture Ch.xInterrupt Enable Register (T16A_IENx) ............................... 11-17
T16A Comparator/Capture Ch.xInterrupt Flag Register (T16A_IFLGx) ................................. 11-18
12 Clock Timer (CT) ........................................................................................................12-1
12.1 CT Module Overview.....................................................................................................12-1
12.2 Operation Clock.............................................................................................................12-1
12.3 Timer Reset...................................................................................................................12-1
12.4 Timer RUN/STOP Control .............................................................................................12-2
12.5 CT Interrupts .................................................................................................................12-2
12.6 Control Register Details ................................................................................................12-3
Clock Timer Control Register (CT_CTL)................................................................................... 12-3
Clock Timer Counter Register (CT_CNT)................................................................................. 12-4
Clock Timer Interrupt Mask Register (CT_IMSK) ..................................................................... 12-4
Clock Timer Interrupt Flag Register (CT_IFLG)........................................................................ 12-4
13 Watchdog Timer (WDT)..............................................................................................13-1
13.1 WDT Module Overview .................................................................................................13-1
13.2 Operation Clock.............................................................................................................13-1
13.3 WDT Control..................................................................................................................13-1
13.3.1 NMI/Reset Mode Selection .............................................................................13-1
13.3.2 WDT Run/Stop Control ...................................................................................13-2
13.3.3 WDT Reset .....................................................................................................13-2
13.3.4 Operations in HALT and SLEEP Modes .........................................................13-2
13.4 Control Register Details ................................................................................................13-2
Watchdog Timer Control Register (WDT_CTL) ........................................................................ 13-2
Watchdog Timer Status Register (WDT_ST)............................................................................ 13-3
14 UART...........................................................................................................................14-1
14.1 UART Module Overview................................................................................................14-1
14.2 UART Input/Output Pins................................................................................................14-2
14.3 Baud Rate Generator ....................................................................................................14-2
14.4 Transfer Data Settings...................................................................................................14-4
14.5 Data Transfer Control ....................................................................................................14-5
14.6 Receive Errors...............................................................................................................14-7
14.7 UART Interrupts ............................................................................................................14-8
14.8 IrDA Interface ................................................................................................................14-9
14.9 Control Register Details ...............................................................................................14-10
UART Ch.xStatus Register (UART_STx)................................................................................ 14-10
UART Ch.xTransmit Data Register (UART_TXDx) ................................................................. 14-12
UART Ch.xReceive Data Register (UART_RXDx) ................................................................. 14-12
UART Ch.xMode Register (UART_MODx) ............................................................................. 14-12
UART Ch.xControl Register (UART_CTLx) ............................................................................ 14-13
UART Ch.xExpansion Register (UART_EXPx) ...................................................................... 14-14
UART Ch.xBaud Rate Register (UART_BRx) ........................................................................ 14-14
UART Ch.xFine Mode Register (UART_FMDx)...................................................................... 14-15
UART Ch.xClock Control Register (UART_CLKx).................................................................. 14-15
15 SPI...............................................................................................................................15-1
15.1 SPI Module Overview....................................................................................................15-1
15.2 SPI Input/Output Pins....................................................................................................15-1
15.3 SPI Clock ......................................................................................................................15-2
15.4 Data Transfer Condition Settings...................................................................................15-2
15.5 Data Transfer Control ....................................................................................................15-3
15.6 SPI Interrupts ................................................................................................................15-5

CONTENTS
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation v
(Rev. 1.0)
15.7 Control Register Details ................................................................................................15-6
SPI Ch.xStatus Register (SPI_STx) ........................................................................................ 15-6
SPI Ch.xTransmit Data Register (SPI_TXDx).......................................................................... 15-7
SPI Ch.xReceive Data Register (SPI_RXDx).......................................................................... 15-7
SPI Ch.xControl Register (SPI_CTLx)..................................................................................... 15-7
16 LCD Driver (LCD).......................................................................................................16-1
16.1 LCD Module Overview ..................................................................................................16-1
16.2 LCD Power Supply ........................................................................................................16-1
16.3 LCD Clock .....................................................................................................................16-2
16.3.1 LCD Operating Clock (LCLK)..........................................................................16-2
16.3.2 Frame Signal...................................................................................................16-3
16.4 Drive Duty Control.........................................................................................................16-3
16.4.1 Drive Duty Switching.......................................................................................16-3
16.4.2 Drive Waveform...............................................................................................16-4
16.5 Display Memory ............................................................................................................16-7
16.6 Display Control..............................................................................................................16-8
16.6.1 Display On/Off.................................................................................................16-8
16.6.2 Inverted Display ..............................................................................................16-8
16.7 LCD Interrupt.................................................................................................................16-9
16.8 Control Register Details ................................................................................................16-9
LCD Timing Clock Select Register (LCD_TCLK)...................................................................... 16-9
LCD Display Control Register (LCD_DCTL)............................................................................ 16-10
LCD Clock Control Register (LCD_CCTL) .............................................................................. 16-11
LCD Voltage Regulator Control Register (LCD_VREG) .......................................................... 16-12
LCD Interrupt Mask Register (LCD_IMSK) ............................................................................. 16-12
LCD Interrupt Flag Register (LCD_IFLG)................................................................................ 16-12
17 Sound Generator (SND) ............................................................................................17-1
17.1 SND Module Overview..................................................................................................17-1
17.2 SND Output Pins...........................................................................................................17-1
17.3 SND Operating Clock....................................................................................................17-1
17.4 Buzzer Frequency and Volume Settings........................................................................17-2
17.4.1 Buzzer Frequency...........................................................................................17-2
17.4.2 Volume level....................................................................................................17-2
17.5 Buzzer Mode and Output Control..................................................................................17-3
17.5.1 Buzzer Mode Selection...................................................................................17-3
17.5.2 Output Control in Normal Mode .....................................................................17-3
17.5.3 Output Control in One-shot Mode ..................................................................17-3
17.5.4 Output Control in Envelope Mode...................................................................17-4
17.6 Control Register Details ...............................................................................................17-5
SND Clock Control Register (SND_CLK)................................................................................. 17-5
SND Control Register (SND_CTL) ........................................................................................... 17-5
Buzzer Frequency Control Register (SND_BZFQ) ................................................................... 17-7
Buzzer Duty Ratio Control Register (SND_BZDT) ................................................................... 17-7
18 Supply Voltage Detection Circuit (SVD)...................................................................18-1
18.1 SVD Module Overview ..................................................................................................18-1
18.2 Comparison Voltage Setting..........................................................................................18-1
18.3 SVD Control ..................................................................................................................18-2
18.4 Control Register Details ................................................................................................18-2
SVD Enable Register (SVD_EN).............................................................................................. 18-2
SVD Comparison Voltage Register (SVD_CMP)...................................................................... 18-3
SVD Detection Result Register (SVD_RSLT)........................................................................... 18-4

CONTENTS
vi Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
19 Multiplier/Divider (COPRO).......................................................................................19-1
19.1 Overview .......................................................................................................................19-1
19.2 Operation Mode and Output Mode................................................................................19-1
19.3 Multiplication .................................................................................................................19-2
19.4 Division..........................................................................................................................19-3
19.5 MAC ..............................................................................................................................19-4
19.6 Reading Operation Results ...........................................................................................19-6
20 Electrical Characteristics..........................................................................................20-1
20.1 Absolute Maximum Ratings ..........................................................................................20-1
20.2 Recommended Operating Conditions ...........................................................................20-1
20.3 Current Consumption ....................................................................................................20-1
20.4 Oscillation Characteristics.............................................................................................20-3
20.5 External Clock Input Characteristics .............................................................................20-3
20.6 Input/Output Pin Characteristics ...................................................................................20-3
20.7 SPI Characteristics........................................................................................................20-5
20.8 LCD Driver Characteristics............................................................................................20-5
20.9 SVD Circuit Characteristics...........................................................................................20-8
21 Basic External Connection Diagram........................................................................21-1
22 Evaluation Package ...................................................................................................22-1
Appendix A List of I/O Registers................................................................................ AP-A-1
0x4100–0x4107, 0x506c UART (with IrDA) Ch.0 .................................... AP-A-3
0x4240–0x4248 8-bit Timer Ch.0............................................... AP-A-4
0x4306–0x4314 Interrupt Controller .......................................... AP-A-4
0x4320–0x4326 SPI Ch.0.......................................................... AP-A-4
0x5000–0x5003 Clock Timer ..................................................... AP-A-5
0x5040–0x5041 Watchdog Timer .............................................. AP-A-5
0x5060–0x5081 Clock Generator .............................................. AP-A-5
0x5070–0x5071, 0x50a0–0x50a6 LCD Driver ...................................................... AP-A-6
0x5100–0x5102 SVD Circuit...................................................... AP-A-7
0x5120 Power Generator ............................................. AP-A-8
0x506e, 0x5180–0x5182 Sound Generator............................................. AP-A-8
0x5200–0x52a2 P Port & Port MUX .......................................... AP-A-8
0x5324–0x532c MISC Registers .............................................. AP-A-10
0x5068, 0x5400–0x540c 16-bit PWM Timer Ch.0.................................. AP-A-11
0x54b0 ROM Controller .............................................. AP-A-12
0x56c0–0x56c8 Real-time Clock.............................................. AP-A-12
0xffff84 S1C17 Core I/O.............................................. AP-A-13
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Clock Control Power Saving......................................................................................... AP-B-1
B.2 Reducing Power Consumption via Power Supply Control ........................................... AP-B-3
Appendix C Mounting Precautions............................................................................ AP-C-1
Appendix D Measures Against Noise........................................................................ AP-D-1
Appendix E Initialization Routine............................................................................... AP-E-1
Appendix F Mask ROM Code Development .............................................................. AP-F-1
Revision History

1 OVERVIEW
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.0)
Overview1
The S1C17153 is a 16-bit MCU featuring ultra-low-power operations and compact dimensions in die form. The
S1C17153 is ideal for battery-driven electronic equipment, such as OTP cards, eTokens, and remote control units
with a simple display.
Features1.1
The main features of the S1C17153 are listed below.
1.1 FeaturesTable 1.
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Multiplier/Divider (COPRO) •16-bit ×16-bit multiplier
•16-bit ×16-bit + 32-bit multiply and accumulation unit
•16-bit ÷16-bit divider
Embedded ROM
Capacity 16K bytes (for both instructions and data)
Embedded RAM
Capacity 2K bytes
Clock generator
System clock source 2 sources (OSC3B/OSC1A)
OSC3B oscillator circuit 2M/1M/500k Hz (typ.) internal oscillator circuit
OSC1A oscillator circuit 32.768 kHz (typ.) crystal oscillator circuit
Other •Core clock frequency control
•Peripheral module clock supply control
LCD driver
Number of driver outputs Segment output: 32 pins
Common output: 4 pins
Other •Includes a power supply voltage booster/reducer.
•Includes a display data memory.
I/O ports
Number of
general-purpose I/O ports Max. 12 bits (Pins are shared with the peripheral I/O.)
Other •Schmitt input
•Pull-up control function
•Port input interrupt: 8 bits
Serial interfaces
SPI 1 channel
UART 1 channel (IrDA1.0 supported)
Timers/Counters
8-bit timer (T8) 1 channel (Generates the SPI clock.)
16-bit PWM timer (T16A2) 1 channel (PWM output, event counter, and count capture functions)
Watchdog timer (WDT) 1 channel (Generates NMI/reset.)
Clock functions
Real-time clock (RTC) 1 channel (Hour, minute, and second counters)
Clock timer (CT) 1 channel (128 Hz to 1 Hz counters)
Sound generator
Buzzer frequency 8 frequencies selectable
Volume control 8 steps adjustable
Other •One-shot buzzer
•Auto envelope function
Analog circuits
Supply voltage
detection circuit (SVD) 1 channel (Detection voltage: 13 levels)
Interrupts
Reset interrupt #RESET pin/watchdog timer
NMI Watchdog timer
Programmable interrupts 8 systems (8 levels)

1 OVERVIEW
1-2 Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
Power supply voltage
Operating voltage (VDD) 2.0 V to 3.6 V
Operating temperature
Operating temperature range -40°C to 85°C
Current consumption (Typ value, VDD = 2.0 V to 3.6 V)
SLEEP state 130 nA (OSC1A = Off, RTC = Off, OSC3B = Off)
HALT state 0.42 µA (OSC1A = 32 kHz, RTC = Off, OSC3B = Off)
0.42 µA (OSC1A = 32 kHz, RTC = On, OSC3B = Off)
Run state 4 µA (OSC1A = 32 kHz, RTC = Off, OSC3B = Off)
240 µA (OSC1A = 32 kHz, RTC = Off, OSC3B = 2 MHz)
Shipping form
Aluminum pad chip
Block Diagram1.2
CPU Core S1C17
Internal RAM
(2K bytes)
8-bit timer (1 ch.)
Clock generator
(with oscillators)
Clock timer
Watchdog timer
16-bit PWM timer
(1 ch.)
MISC register
Power generator
Internal ROM
(16K bytes)
32 bits
16 bits
Interrupt system
8/16 bits
VD1, VC1–3,
CA, CB
OSC1–2
FOUTA, FOUTB
EXCL0,
CAPA0/TOUTA0,
CAPB0/TOUTB0
P00–07, P10–13
#RESET
SIN0, SOUT0,
SCLK0
SDI0, SDO0,
SPICLK0,
#SPISS0
Reset circuit
8/16 bits
I/O 2 (0x5000–)
Interrupt controller
UART (1 ch.)
SPI (1 ch.)
I/O 1 (0x4000–)
I/O port/
port MUX
Real-time clock
TEST Test circuit
Sound generator BZ, #BZ
LCD driver
Supply voltage
detection circuit
SEG0–31, COM0–3
LFRO
2.1 S1C17153 Block DiagramFigure 1.

1 OVERVIEW
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.0)
Pads1.3
Pad Configuration Diagram1.3.1
P03/EXCL0/LFRO
P04/TOUTA0/CAPA0
P05/TOUTB0/CAPB0/#SPISS0
P06/BZ/SDI0
P07/#BZ/SDO0
P10/FOUTB/SPICLK0
P11/BZ
P12/#BZ
P13
SEG31 SEG30 SEG29 SEG28
COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
VC3
VC2
VC1
CB
CA
VSS
VDD
VD1
OSC1
OSC2
TEST
#RESET
P00/SIN0
P01/SOUT0
P02/SCLK0/FOUTA
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
Y
X
(0, 0)
1.952 mm
1.781 mm
1 2 3 4 5 6 7 8 9 10 11 12 13
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
45 44 43 42 41 40 39 38 37 36 35 34
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Die No.
3.1.1 S1C17153 Pad Configuration DiagramFigure 1.
Chip size X = 1.781 mm, Y = 1.952 mm
Pad opening X = 68 µm, Y = 68 µm
Chip thickness 400 µm

1 OVERVIEW
1-4 Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
3.1.1 S1C17153 Pad CoordinatesTable 1.
No. Name X (µm) Y (µm) No. Name X (µm) Y (µm)
1P03/EXCL0/LFRO -453.5 -896.5 34 SEG7 549.0 896.5
2P04/TOUTA0/CAPA0 -373.5 -896.5 35 SEG6 469.0 896.5
3P05/TOUTB0/CAPB0/#SPISS0 -293.5 -896.5 36 SEG5 389.0 896.5
4P06/BZ/SDI0 -213.5 -896.5 37 SEG4 309.0 896.5
5P07/#BZ/SDO0 -133.5 -896.5 38 SEG3 229.0 896.5
6P10/FOUTB/SPICLK0 -53.5 -896.5 39 SEG2 149.0 896.5
7 P11/BZ 26.5 -896.5 40 SEG1 69.0 896.5
8 P12/#BZ 106.5 -896.5 41 SEG0 -11.0 896.5
9 P13 186.5 -896.5 42 COM3 -96.0 896.5
10 SEG31 309.0 -896.5 43 COM2 -176.0 896.5
11 SEG30 389.0 -896.5 44 COM1 -256.0 896.5
12 SEG29 469.0 -896.5 45 COM0 -336.0 896.5
13 SEG28 549.0 -896.5 46 VC3 -811.0 840.5
14 SEG27 811.0 -858.3 47 VC2 -811.0 760.5
15 SEG26 811.0 -778.3 48 VC1 -811.0 680.5
16 SEG25 811.0 -600.0 49 CB -811.0 600.5
17 SEG24 811.0 -520.0 50 CA -811.0 520.5
18 SEG23 811.0 -440.0 51 VSS -811.0 350.0
19 SEG22 811.0 -360.0 52 VDD -811.0 270.0
20 SEG21 811.0 -280.0 53 VD1 -811.0 190.0
21 SEG20 811.0 -200.0 54 OSC1 -811.0 50.0
22 SEG19 811.0 -120.0 55 OSC2 -811.0 -50.0
23 SEG18 811.0 -40.0 56 TEST -811.0 -190.0
24 SEG17 811.0 40.0 57 #RESET -811.0 -270.0
25 SEG16 811.0 120.0 58 P00/SIN0 -811.0 -350.0
26 SEG15 811.0 200.0 59 P01/SOUT0 -811.0 -430.0
27 SEG14 811.0 280.0 60 P02/SCLK0/FOUTA -811.0 -510.0
28 SEG13 811.0 360.0
29 SEG12 811.0 440.0
30 SEG11 811.0 520.0
31 SEG10 811.0 600.0
32 SEG9 811.0 778.3
33 SEG8 811.0 858.3

1 OVERVIEW
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.0)
Pin Descriptions1.3.2
Note: The pin names described in boldface type are default settings.
3.2.1 Pin DescriptionsTable 1.
Pad No. Name I/O Default
status Function
10–41 SEG31–SEG0 O O (Hi-Z) LCD segment output pins
42–45 COM3–COM0 O O (Hi-Z) LCD common output pins
46 VC3 – – LCD system power supply circuit output pin
47 VC2 – – LCD system power supply circuit output pin
48 VC1 – – LCD system power supply circuit output pin
49 CB – –
Voltage boost capacitor connecting pin for LCD system power supply circuit
50 CA – –
Voltage boost capacitor connecting pin for LCD system power supply circuit
51 VSS – – GND pin
52 VDD – – Power supply pin (2.0 to 3.6 V)
53 VD1 – – Internal logic system voltage regulator output pin
54 OSC1 I I OSC1A oscillation input pin
55 OSC2 O O OSC1A oscillation output pin
56 TEST I
I (Pull-down) Test input pin (Connect to VSS for normal operation.)
57 #RESET I I (Pull-up) Initial reset input pin
58 P00 I/O I (Pull-up) I/O port pin (with port input interrupt function)
SIN0 I UART Ch.0 data input pin
59 P01 I/O I (Pull-up) I/O port pin (with port input interrupt function)
SOUT0 O UART Ch.0 data output pin
60 P02 I/O I (Pull-up) I/O port pin (with port input interrupt function)
SCLK0 I UART Ch.0 external clock input pin
FOUTA O Clock output pin
1P03 I/O I (Pull-up) I/O port pin (with port input interrupt function)
EXCL0 I T16A2 Ch.0 external clock input pin
LFRO O LCD frame signal output pin
2P04 I/O I (Pull-up) I/O port pin (with port input interrupt function)
TOUTA0 O T16A2 Ch.0 TOUT A signal output pin
CAPA0 I T16A2 Ch.0 capture A trigger signal input pin
3P05 I/O I (Pull-up) I/O port pin (with port input interrupt function)
TOUTB0 O T16A2 Ch.0 TOUT B signal output pin
CAPB0 I T16A2 Ch.0 capture B trigger signal input pin
#SPISS0 I SPI Ch.0 slave select signal input pin
4P06 I/O I (Pull-up) I/O port pin (with port input interrupt function)
BZ O Buzzer output pin
SDI0 I SPI Ch.0 data input pin
5P07 I/O I (Pull-up) I/O port pin (with port input interrupt function)
#BZ O Buzzer inverted output pin
SDO0 O SPI Ch.0 data output pin
6P10 I/O I (Pull-up) I/O port pin
FOUTB O Clock output pin
SPICLK0 I/O SPI Ch.0 clock input/output pin
7–O O (H) –
P11 I/O I/O port pin
BZ O Buzzer output pin
8–I I (Pull-up) –
P12 I/O I/O port pin
#BZ O Buzzer inverted output pin
9–O O (L) –
P13 I/O I/O port pin

2 CPU
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation 2-1
(Rev. 1.0)
CPU2
The S1C17153 contains the S1C17 Core as its core processor.
The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor.
It features low power consumption, high-speed operation, large address space, main instructions executable in one
clock cycle, and a small sized design. The S1C17 Core is suitable for embedded applications such as controllers
and sequencers for which an eight-bit CPU is commonly used.
For details of the S1C17 Core, refer to the “S1C17 Family S1C17 Core Manual.”
Features of the S1C17 Core2.1
Processor type
•Seiko Epson original 16-bit RISC processor
•0.35–0.15 µm low power CMOS process technology
Instruction set
•Code length: 16-bit fixed length
•Number of instructions: 111 basic instructions (184 including variations)
•Execution cycle: Main instructions executed in one cycle
•Extended immediate instructions: Immediate extended up to 24 bits
•Compact and fast instruction set optimized for development in C language
Register set
•Eight 24-bit general-purpose registers
•Two 24-bit special registers
•One 8-bit special register
Memory space and bus
•Up to 16M bytes of memory space (24-bit address)
•Harvard architecture using separated instruction bus (16 bits) and data bus (32 bits)
Interrupts
•Reset, NMI, and 32 external interrupts supported
•Address misaligned interrupt
•Debug interrupt
•Direct branching from vector table to interrupt handler routine
•Programmable software interrupts with a vector number specified (all vector numbers specifiable)
Power saving
•HALT (halt instruction)
•SLEEP (slp instruction)
Coprocessor interface
•16-bit ×16-bit multiplier
•16-bit ÷16-bit divider
•16-bit ×16-bit + 32-bit multiply and accumulation unit

2 CPU
2-2 Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
CPU Registers2.2
The S1C17 Core contains eight general-purpose registers and three special registers.
R4
R5
R6
R7
R3
R2
R1
R0
bit 23 bit 0
General-purpose registers
PC
bit 23
7
6
5
4
3
2
1
0
bit 0
PSR
SP
Special registers
IL[2:0]
765
IE
4
C
3
V
2
Z
1
N
0
2.1 RegistersFigure 2.
Instruction Set2.3
The S1C17 Core instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, al-
lows most important instructions to be executed in one cycle. For details, refer to the “S1C17 Family S1C17 Core
Manual.”
3.1 List of S1C17 Core InstructionsTable 2.
Classification Mnemonic Function
Data transfer ld.b %rd,%rs General-purpose register (byte) →general-purpose register (sign-extended)
%rd,[%rb]Memory (byte) →general-purpose register (sign-extended)
Memory address post-increment, post-decrement, and pre-decrement
functions can be used.
%rd,[%rb]+
%rd,[%rb]-
%rd,-[%rb]
%rd,[%sp+imm7]Stack (byte) →general-purpose register (sign-extended)
%rd,[imm7]Memory (byte) →general-purpose register (sign-extended)
[%rb],%rs General-purpose register (byte) →memory
Memory address post-increment, post-decrement, and pre-decrement
functions can be used.
[%rb]+,%rs
[%rb]-,%rs
-[%rb],%rs
[%sp+imm7],%rs General-purpose register (byte) →stack
[imm7],%rs General-purpose register (byte) →memory
ld.ub %rd,%rs General-purpose register (byte) →general-purpose register (zero-extended)
%rd,[%rb]Memory (byte) →general-purpose register (zero-extended)
Memory address post-increment, post-decrement, and pre-decrement
functions can be used.
%rd,[%rb]+
%rd,[%rb]-
%rd,-[%rb]
%rd,[%sp+imm7]Stack (byte) →general-purpose register (zero-extended)
%rd,[imm7]Memory (byte) →general-purpose register (zero-extended)
ld %rd,%rs General-purpose register (16 bits) →general-purpose register
%rd,sign7 Immediate →general-purpose register (sign-extended)
%rd,[%rb]Memory (16 bits) →general-purpose register
Memory address post-increment, post-decrement, and pre-decrement
functions can be used.
%rd,[%rb]+
%rd,[%rb]-
%rd,-[%rb]
%rd,[%sp+imm7]Stack (16 bits) →general-purpose register
%rd,[imm7]Memory (16 bits) →general-purpose register
[%rb],%rs General-purpose register (16 bits) →memory
Memory address post-increment, post-decrement, and pre-decrement
functions can be used.
[%rb]+,%rs
[%rb]-,%rs
-[%rb],%rs
[%sp+imm7],%rs General-purpose register (16 bits) →stack
[imm7],%rs General-purpose register (16 bits) →memory
ld.a %rd,%rs General-purpose register (24 bits) →general-purpose register
%rd,imm7 Immediate →general-purpose register (zero-extended)

2 CPU
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation 2-3
(Rev. 1.0)
Classification Mnemonic Function
Data transfer ld.a %rd,[%rb]Memory (32 bits) →general-purpose register (*1)
Memory address post-increment, post-decrement, and pre-decrement
functions can be used.
%rd,[%rb]+
%rd,[%rb]-
%rd,-[%rb]
%rd,[%sp+imm7]Stack (32 bits) →general-purpose register (*1)
%rd,[imm7]Memory (32 bits) →general-purpose register (*1)
[%rb],%rs General-purpose register (32 bits, zero-extended) →memory (*1)
Memory address post-increment, post-decrement, and pre-decrement
functions can be used.
[%rb]+,%rs
[%rb]-,%rs
-[%rb],%rs
[%sp+imm7],%rs General-purpose register (32 bits, zero-extended) →stack (*1)
[imm7],%rs General-purpose register (32 bits, zero-extended) →memory (*1)
%rd,%sp SP →general-purpose register
%rd,%pc PC →general-purpose register
%rd,[%sp] Stack (32 bits) →general-purpose register (*1)
Stack pointer post-increment, post-decrement, and pre-decrement functions
can be used.
%rd,[%sp]+
%rd,[%sp]-
%rd,-[%sp]
[%sp],%rs General-purpose register (32 bits, zero-extended) →stack (*1)
Stack pointer post-increment, post-decrement, and pre-decrement functions
can be used.
[%sp]+,%rs
[%sp]-,%rs
-[%sp],%rs
%sp,%rs General-purpose register (24 bits) →SP
%sp,imm7 Immediate →SP
Integer arithmetic
operation
add %rd,%rs 16-bit addition between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
add/c
add/nc
add %rd,imm7 16-bit addition of general-purpose register and immediate
add.a %rd,%rs 24-bit addition between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
add.a/c
add.a/nc
add.a %sp,%rs 24-bit addition of SP and general-purpose register
%rd,imm7 24-bit addition of general-purpose register and immediate
%sp,imm7 24-bit addition of SP and immediate
adc %rd,%rs 16-bit addition with carry between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
adc/c
adc/nc
adc %rd,imm7 16-bit addition of general-purpose register and immediate with carry
sub %rd,%rs 16-bit subtraction between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
sub/c
sub/nc
sub %rd,imm7 16-bit subtraction of general-purpose register and immediate
sub.a %rd,%rs 24-bit subtraction between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
sub.a/c
sub.a/nc
sub.a %sp,%rs 24-bit subtraction of SP and general-purpose register
%rd,imm7 24-bit subtraction of general-purpose register and immediate
%sp,imm7 24-bit subtraction of SP and immediate
sbc %rd,%rs 16-bit subtraction with carry between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
sbc/c
sbc/nc
sbc %rd,imm7 16-bit subtraction of general-purpose register and immediate with carry
cmp %rd,%rs 16-bit comparison between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
cmp/c
cmp/nc
cmp %rd,sign7 16-bit comparison of general-purpose register and immediate
cmp.a %rd,%rs 24-bit comparison between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
cmp.a/c
cmp.a/nc
cmp.a %rd,imm7 24-bit comparison of general-purpose register and immediate
cmc %rd,%rs 16-bit comparison with carry between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
cmc/c
cmc/nc
cmc %rd,sign7 16-bit comparison of general-purpose register and immediate with carry

2 CPU
2-4 Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
Classification Mnemonic Function
Logical operation and %rd,%rs Logical AND between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
and/c
and/nc
and %rd,sign7 Logical AND of general-purpose register and immediate
or %rd,%rs Logical OR between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
or/c
or/nc
or %rd,sign7 Logical OR of general-purpose register and immediate
xor %rd,%rs Exclusive OR between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
xor/c
xor/nc
xor %rd,sign7 Exclusive OR of general-purpose register and immediate
not %rd,%rs Logical inversion between general-purpose registers (1's complement)
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
not/c
not/nc
not %rd,sign7 Logical inversion of general-purpose register and immediate (1's complement)
Shift and swap sr %rd,%rs Logical shift to the right with the number of bits specified by the register
%rd,imm7 Logical shift to the right with the number of bits specified by immediate
sa %rd,%rs Arithmetic shift to the right with the number of bits specified by the register
%rd,imm7 Arithmetic shift to the right with the number of bits specified by immediate
sl %rd,%rs Logical shift to the left with the number of bits specified by the register
%rd,imm7 Logical shift to the left with the number of bits specified by immediate
swap %rd,%rs Bytewise swap on byte boundary in 16 bits
Immediate extension
ext imm13 Extend operand in the following instruction
Conversion cv.ab %rd,%rs Converts signed 8-bit data into 24 bits
cv.as %rd,%rs Converts signed 16-bit data into 24 bits
cv.al %rd,%rs Converts 32-bit data into 24 bits
cv.la %rd,%rs Converts 24-bit data into 32 bits
cv.ls %rd,%rs Converts 16-bit data into 32 bits
Branch jpr
jpr.d
sign10 PC relative jump
Delayed branching possible
%rb
jpa
jpa.d
imm7 Absolute jump
Delayed branching possible
%rb
jrgt
jrgt.d
sign7 PC relative conditional jump Branch condition: !Z & !(N ^ V)
Delayed branching possible
jrge
jrge.d
sign7 PC relative conditional jump Branch condition: !(N ^ V)
Delayed branching possible
jrlt
jrlt.d
sign7 PC relative conditional jump Branch condition: N ^ V
Delayed branching possible
jrle
jrle.d
sign7 PC relative conditional jump Branch condition: Z | N ^ V
Delayed branching possible
jrugt
jrugt.d
sign7 PC relative conditional jump Branch condition: !Z & !C
Delayed branching possible
jruge
jruge.d
sign7 PC relative conditional jump Branch condition: !C
Delayed branching possible
jrult
jrult.d
sign7 PC relative conditional jump Branch condition: C
Delayed branching possible
jrule
jrule.d
sign7 PC relative conditional jump Branch condition: Z | C
Delayed branching possible
jreq
jreq.d
sign7 PC relative conditional jump Branch condition: Z
Delayed branching possible
jrne
jrne.d
sign7 PC relative conditional jump Branch condition: !Z
Delayed branching possible
call
call.d
sign10 PC relative subroutine call
Delayed call possible
%rb
calla
calla.d
imm7 Absolute subroutine call
Delayed call possible
%rb
ret
ret.d
Return from subroutine
Delayed return possible
int imm5 Software interrupt
intl imm5,imm3 Software interrupt with interrupt level setting
reti
reti.d
Return from interrupt handling
Delayed call possible
brk Debug interrupt

2 CPU
S1C17153 TECHNICAL MANUAL Seiko Epson Corporation 2-5
(Rev. 1.0)
Classification Mnemonic Function
Branch retd Return from debug processing
System control nop No operation
halt HALT mode
slp SLEEP mode
ei Enable interrupts
di Disable interrupts
Coprocessor control
ld.cw %rd,%rs Transfer data to coprocessor
%rd,imm7
ld.ca %rd,%rs Transfer data to coprocessor and get results and flag statuses
%rd,imm7
ld.cf %rd,%rs Transfer data to coprocessor and get flag statuses
%rd,imm7
*1 The ld.a instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the
32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memory,
the eight high-order bits of the read data are ignored.
The symbols in the above table each have the meanings specified below.
3.2 Symbol MeaningsTable 2.
Symbol Description
%rs General-purpose register, source
%rd General-purpose register, destination
[%rb]Memory addressed by general-purpose register
[%rb]+ Memory addressed by general-purpose register with address post-incremented
[%rb]- Memory addressed by general-purpose register with address post-decremented
-[%rb]Memory addressed by general-purpose register with address pre-decremented
%sp Stack pointer
[%sp],[%sp+imm7]Stack
[%sp]+ Stack with address post-incremented
[%sp]- Stack with address post-decremented
-[%sp] Stack with address pre-decremented
imm3,imm5,imm7,imm13 Unsigned immediate (numerals indicating bit length)
sign7,sign10 Signed immediate (numerals indicating bit length)
Reading PSR2.4
The S1C17153 includes the MISC_PSR register for reading the contents of the PSR (Processor Status Register) in
the S1C17 Core. Reading the contents of this register makes it possible to check the contents of the PSR using the
application software. Note that data cannot be written to the PSR.
PSR Register (MISC_PSR)
Register name Address Bit Name Function Setting Init. R/W Remarks
PSR Register
(MISC_PSR)
0x532c
(16 bits)
D15–8 –reserved – – – 0 when being read.
D7–5 PSRIL[2:0] PSR interrupt level (IL) bits 0x0 to 0x7 0x0 R
D4 PSRIE PSR interrupt enable (IE) bit 1 1 (enable) 0 0 (disable) 0 R
D3 PSRC PSR carry (C) flag 1 1 (set) 0 0 (cleared) 0 R
D2 PSRV PSR overflow (V) flag 1 1 (set) 0 0 (cleared) 0 R
D1 PSRZ PSR zero (Z) flag 1 1 (set) 0 0 (cleared) 0 R
D0 PSRN PSR negative (N) flag 1 1 (set) 0 0 (cleared) 0 R
D[15:8] Reserved
D[7:5] PSRIL[2:0]: PSR Interrupt Level (IL) Bits
The value of the PSR IL (interrupt level) bits can be read out. (Default: 0x0)
D4 PSRIE: PSR Interrupt Enable (IE) Bit
The value of the PSR IE (interrupt enable) bit can be read out.
1 (R): 1 (interrupt enabled)
0 (R): 0 (interrupt disabled) (default)

2 CPU
2-6 Seiko Epson Corporation S1C17153 TECHNICAL MANUAL
(Rev. 1.0)
D3 PSRC: PSR Carry (C) Flag Bit
The value of the PSR C (carry) flag can be read out.
1 (R): 1
0 (R): 0 (default)
D2 PSRV: PSR Overflow (V) Flag Bit
The value of the PSR V (overflow) flag can be read out.
1 (R): 1
0 (R): 0 (default)
D1 PSRZ: PSR Zero (Z) Flag Bit
The value of the PSR Z (zero) flag can be read out.
1 (R): 1
0 (R): 0 (default)
D0 PSRN: PSR Negative (N) Flag Bit
The value of the PSR N (negative) flag can be read out.
1 (R): 1
0 (R): 0 (default)
Processor Information2.5
The S1C17153 has the IDIR register shown below that allows the application software to identify CPU core type.
Processor ID Register (IDIR)
Register name Address Bit Name Function Setting Init. R/W Remarks
Processor ID
Register
(IDIR)
0xffff84
(8 bits)
D7–0 IDIR[7:0] Processor ID
0x10: S1C17 Core
0x10 0x10 R
This is a read-only register that contains the ID code to represent a processor model. The S1C17 Core’s ID code is
0x10.