Sharp Pc-1211 User manual

SHARP CORPORATION

CONTENTS

1

.

Specifications

.

. .

.

. . . . .

. .

.

. .

. . . . . .

. .

.

. . . . . .

.

. . . . . .

.

2

2. Block diagram

. . . . .

.

. . . . . . . . . . . .

.

. . . . . .

.

. .

.

. . .

. .

. . .

. .

4

3

.

LSI signal description

12

4

.

About servicing

17

5

.

Cassette operation

. . . .

.

. .

.

. . . . .

.

. .

. . .

. . . .

.

. . . . . . . . . . . . . . . . . .

18

6. Check program

·

· · ·

25

7

.

Circuit diagram

. . . . .

.

. .

. . . .

.

. . .

. .

. . .

. .

.

. .

.

. .

.

. . . . .

.

. .

.

. .

26

8

.

PC

-

1211 parts list & guide

· ·

32

9.

CE

-

121 parts list

&

guide

.

. . .

. .

.

. . . . . .

.

. .

. . .

.

· ·

·

.

·

· · ·

· ·

· · ·

34

MODEL

PC-1211, CE-121

----SHARP----

SERVICE

MANUAL

2

Add

(+)

,

Subtract(

-

)

,

Multiply

(+),Divide(/)

,

Power raising

(

A

)

Trigonometric

funct

i

ons

:

SIN(sine)

,

COS(cosine)

,

TAN(tangent)

Inversetrigonometric functions: ASN(sine

"

), ACS

(cosine

-

1

),

ATN

(

tangent

-

1

)

Logarithmic functions: LOG(common logarithm), LN(natural

log

a

rit

hm

[

ln

]

)

·

Exponential functions: EXP(exponential)

Angulartransformations: DMS(decimalnotation to sexagesimal

n

o

ta

ti

o

n

)

,

DEG(sexagesimalnotation to decimaln

ota

t

i

o

n

)

Square root extraction:

r

Signum

function

.

SGN

Absolute

val

u

e

:

ABS

(IX

I)

Interization: INT

Execution of arithmetic operation

is

commanded by the ENTER key

.

1-3

.

Arithmeticfunctions

•

Buffers

:

•

Capacities

:

12

digits of mantissa and

2

digitsof exponent.

According to mathematical formula (with priority consideration

andjudge function)

Programmemory; 1424

steps

,

max (PC1211)

Data memory; Fixed memory

26 memories

Flexible memory (commonly usable with the

programmemory)

178 memories

,

max (PC1211)

Reserveprogram; 18 kinds, 48 steps

,

max

Input buffer; 80 steps

Data buffer;

8

stages

Functional buffer;

16

stages(but

15

stagesfor

parenthesis

)

Subroutine buffer; 4 stages

"FOR NEXT" stagement

buffer

:

4 stages

•

Computational capacity:

•

Computational method:

1-2. Basic

functions

•

Displaytube: LF8017JE

•

Displaymethod:

5

x

7

dot matrix liquid crystal

•

Displaycapacity: 24 coulumns (alphanumerics and symbols)

1-1

.

Display

I

N

S

OJ

ITJ []]

El G

DEL

w w

rn

w

@g

G] [[] []]

W

[

MODE

\

C

A

/

BR

EA

K

1(

A

<

>

~~

PO

WER

IT] [TI 0

OJ OJ

[

S

HF

T

j

!

" #

s

%

¥

?

•

;

~ ~ 0 0

IT]

[!] ~ [I] ~ 0

0 [}] 0 0 0 0 0

IT]

[TI~

IT] 0 [I] 0 0 0 ~ ~

~

E

R

i

R

E

SE

R

VABLE

KEY

S

1. SPECIFICATIONS

3

Data

protection

:

Program memory, data

memory

,

reserve program memory

P

eri

p

heral unit: Audio cassette unit

(recording

/

reading of the program memory,

d

ata

memo

r

y and reserve program memory)

Physical

d

imensions: 175(W)

x 7

0

(D) x 44(H) mm

1

-

7. Others

Four MR44 (mercury batteries)

3

0

0 hours

0.01

iw

About 6 minutes

B

att

e

ry:

B

attery life:

Po

we

r

co

n

sumption:

Automatic

p

ower shut off:

1

-6. Power source

1

-

5

.

Programming language

BAS

IC

(

Beginne

r's

Al

l

pu

rpose

S

ymbolic Instruction Code)

....

(right),

~

(left)

I

N

S

D

EL

+(

d

own),

t

(

up

)

Cursor shift:

Insert

i

on

.

Deletion

:

Line control:

1-4. Editorial

functions

4

-

0..

0

0.

~

cc

I

t

cc

_

Cfl

-e-

...

I

u

...::...

I

~ ~

...

cc

"'

~ ~

;!:

"-

(/)

l

>::

(/) (/) (/)

~

u;

~

L<(

-x:J-i

·-

"'

00

l

H-

lH

"'

t--

::J

.....

B

d

"

i

d

""

0..

....

-

d

s

!

a

u

~

-

ir:

~

.0

-

"'

~

...

::a

en

G:

eo co

~

0

B;

"-

::il

x

-

"'

8

0.

-

<- cc

-c

~ rn rn

'' Z<

;:;,

"'

(/)

:i:

11;[

i CJ

>

>>

>

> >

I

"-

"'

.0

:i:

:;;

-'-

~

r- 00 0

A.. f

:;;:

'.,

-c:

:;:

~

--

,___

"'

~

I

,_

,___

~

I+-

,__

-

0..

~

a

i.........:..::

-

V

H

"'

q

,\\/N ~·l•lt--

x

...

~

8V-!V 0

0

"'

-

cc

"'

0

u x

-

I

"'

-

0

...

0

...

II

(/)

-

.l

I

u 0

- (/)

~

(/)

~

::il

tO

ia

-

!OJG

rn

/I-- c,

<

~

' l

¥---

·-

6

.0

rn

-

°'

er:

s-,

G:

'7

rn rn

.o

~

rn

"'rn

-

rn

c.

~

~ ~U":l

~

qs

00

v;

;;;

~

Cl

rn

""

CJ

'--

"'

-

c

I+---

>O-

<llO..

"-

(/)

u

t--

~

i+--

:>Cl

ID

c

!.---

><

-

.....

~

-

>

L'lCJ

""

..__

::J

....

'-

L'l

Z

O

0..

u

Ul

~

I+--

;::::=:¢

-s-

sc

>::

·

-

I

:'.:

>::

-

en

>::

I

z

»

"'

cc

0

>::

in

;..

¢=

~

>::

o

:E

<(

a:

CJ

<(

c

~

0

...J

m

en

(/)

CJ

z

0

"'

0

~~

u

"'

.l

<

.l

z

<

CJ

z

CJ

.l

<

z

CJ

(/)

5

•

The CPU

I

functions to read key-in data or read the instruction to be executed from the

RAM

,

and decides what

is

to be done for the control of arithmetical operation (i.e. control of

arithmetic sequence, memorizing of arithmetical

data

,

and its readout), or interprete the syntax

of the BASICinstruction for deciding what

is

to be executed, or determines and prepares the

information to be displayed, but the CPU

I

does not perform any execution by

itself

.

It

only

arrangesthe data and information in proper sequence and acts to provideinstruction code to the

CPU II via the buffer. On the other

hand

,

the CPU II constantly receivesexecution instructions

from the CPU

I

via the transfer buffer and executes operation against each of instructions or

sometimes performs to exchange data depending on the

situation

.

Although it sharesmajor part

of execution in term of execution, it performs some kinds of auxiliary CPUwhen looked in the

viewthat it does not perform any decision by

itself

.

Clockstop

Clockstop control

I

Power shut off control

I

Power off

Displayprocessingroutine

Input buffer

Computational result

Error

Arithmetic routine

Character generator

Cassetteroutine

Print routine

Buzzer

Recognition of printer

Key input routine

Acknowledgementof the remaining

program

One instruction to one program step

incorporation

Interpreter:

Programexecute statement

Cassettecontrol statement

Command statement

Printer control

Execution of manual operation

CPU

II

CPUI

TheseCPUsare provided with internal ROM,and each of CPUsshares the followingassignments:

2-1

.

CP

U

I,

CP

U

II

System

configuration

(see

the

system

block

diagram)

System of this unit consists of the followingcomponents:

1)

CPU

I

(SC43157)

x

1

2) CPUII (SC43178)

x

1

3) 4K-bit RAM (TC5514P

x

3)

4) Displaychip (SC43125

x

3, with built-in RAM)

5) 2ANDgate (TC401

l

UBP

x

1)

6) 2AND

20R

(TC4019BP

x

1)

7) Inverter (TC4069BP

x

1)

8) Quard AnalogSwitchMultiplexer(TC4066BP)

9) LCD (24-digit FEMdot LCD)

10) Key

11) Crystal (CSB2560)

8

>

6

In the case of manual operation of the pocket computer, the instruction code (key code)

is

written

into the RAMin the display chip (input buffer) after information

is

put through the keyboard and

converted into the instruction code by the CPU

I,

then this instruction code (display, at this case)

is

transfered to the CPUII

via

the transfer buffer.

As

the CPUII receivesthis instruction, the CPU

II

then decodes this instruction

(display

,

at this case) and executes display processing. Upon the

completion of this processing,

it

is

then notified to the CPUI, then the CPU

I

confirms the comple-

tion of the task by the CPUII before terminating their jobs.

CPU

Il

Ex: Actions of CPU

I

and CPU II at the time of key data entry.

7

Although RAM area is mainly shared by the

program

,

data

and reserve program

memories

,

it

is

also used for the sub-

routine stack, FOR NEXT statement stack and fixed

memories

(W

,

X

,

Y

,

Z)

.

1536

1472

1504

001

048

(PC1211)

Reserve

pr

o

gram

------- - -

-

--

Program

or

flexible

memory

~---

-

-- -------

Fixed memories (W

-

Z)

Subroutine

I

FOR

stack

A certain number

of

C-MOS RAM

(1

-

3

chips, 4K bits each) and another RAM incorporated inside

the display chip are used in this pocket computer, having varieties of configurations

as

described

below:

•

Map

of

4K-bit RAM

153

6 Bytes

2-2.

RAM

en

nd

;e)

II

he

le-

8

•

Input buffer

Remaining 80 bytes (10 memories equivalent) of the display chip

1

is

used for the input

buffer

,

whi

c

h

is

used in the following

fun

c

tions:

1.

Any information entered through the keyboard

is

stored once in this

buffer

,

thus allowingup

to 80 steps.

2. The display contents

is

stored by the CPU

I

and the CPUII makes selection out of this

da

t

a.

3

.

When an

arithmet

i

cal instruction

i

s

entered

,

its

p

rocedure

is

stored in this buffer by the CPU

I

and the CPU

II

performs operation accord

i

ng to this procedure.

4

.

Whenprogram or reserveprogram

is

t

o

be recorded or read out during the execution of the

cassette control

instruction

,

action takes place through this input buffer.

•

Transfer buffer

8

bytes

(1

memory

equi

v

alent) of the

displa

y

c

hi

p

1

i

s

used

as

a

transfer buffer

w

h

ic

h

is

used in

the

transa

c

t

i

on of instruction between the

C

PU

I

and the CPUII.

16

b

i

ts

----1}4bit

1

memory

•

Fixed memory

The total memory of 176 bytes from the display chip

2

and

3

is

used

as a

fixed

memories

,

A

-

V

(22 memories).

•

8-digitdisplaybuffer

40 bytes of 8-digit display buffer

is

used

as a

display data buffer during displayingand also used

as

a

buffer memory for arithmetical result duringthe arithmetical operation.

128

80 step input buffer Fixed memories

(L-V

,

11

memories)

Fixed memories

(A-K

,

11

memories)

Transfer buffer

040

04

8

8-digitdisplaybuffer 8-digitdisplaybuffer

8-digitdisplaybuffer

000

DISPLAY CHIP

3

DISPLAY CHIP

2

DISPLAY CHIP

1

•

Map of the RAM incorporated in the display chip

There are three lK-bit RAMs (128 bytes each) incorporated in each of display chips (SC43125),

having the following

configurations

:

9

F

i

g

2

-

3

-1

The

numeri

ca

figure

"

4

", to be displayed by the CPU

II

,

is

c

onverted into the

r

ele

v

ant character

code and carried through on the address data bus

.

First of

all

,

the segment Sl

is

selected with the

address

A8-Al "

00000000" to

s

tore the data DI04-DI01

"1000

"

in

t

he display buffer

(see

Fi

g

.

2-3-1

). To store second half 4 bits of the

data

,

only

AS

in the address in

t

urned

"

1

" to make the

address "00010000" to store data

"

0001". In the same

manner

,

the address "00000001"

is

selected

for storing the first half

4

-

bit data

"O

100" for he segmentS2 and the

se

c

ond half 4

-

bit data

"

000

I

"

is

stored with the address "00010001 ".

S40

S32

S3

3

S34

Sl6

Sl7

Sl

8

1

S2

A5=0

A5=1

DI04 DI02 DI04 DI02

'--------..,..-~

Addr

es

s

0

1

0

0 0

)

F

0

1

0 0

1

)

F

0

1

0

1

0

~

F

Al

I

A8

A7

A6 A4

Hl

DDD•D

H2

oo••

o

H3

o•o•

o

H4

•oo•o

H

5

•••••

H6

ooo•o

H7

ooo•o

Sl

S2

S

3

S4 S5

Ex

:

Displaying numerical figure

"4"

There are

8

x

40=320 bits

(

40 bytes)

of area in the display buffer in the

display chip.

D

is

p

lay

b

u

ffer

XOOl 0100

H8 H7 H6 H5 H4 H3 H2

Hl

X

OOl 1000

Co

unter/

decoder

HA

T

he con

t

ents of

di

sp

lay

ind

i

cated by

t

he CPU

I is

receiv

e

d

by the

C

P

U

II

via the input buffer and

m

akes converte

d

into

respecti

ve

character cod

e

s,

then they are carried over to the displaybuffer in

t

he

di

sp

lay

chi

p through

t

he addressdata

bus

.

•

D

es

i

gnatio

n of the display

d

ata

Th

e

followin

g

struct

u

re is

observedin the displaybuffer in the display

chip

.

2-3. Display

the

ata.

'U

I

up

f

er

,

.in

v

d

10

HA: Clock frequency for the counter. This signal

is

counted and decoded to perform

s

y

nchroni

-

zation with the comman

signal

,

Hl-H7

,

generated from the CPU

II

.

DSIP: With high level of this

signal

,

processing of display operation

is

indicated (RAM data

designatedby

Hl-H8

is

sent out on SI

-S40).

The data stored in the display buffer

is

carried

th

rough

SI-S40

(Fig

.

2-3

-

2) to be fed

t

o

the LCD.

(To

indicat

e

"4

" on the

dis

p

lay

,

H4 and HS

ar

e

engag

ed for

SI

,

H3 and

H

S

for

S

2,

etc

.

,

all the same

throughout

S6-S40

.

)

F

ig

2

-

3

-

2

S

2

Sl

H7

H6

LJl....____flJ

L

I

H

5

LJ

H

4

H3

H

2

Hl

-----------

--------

-

--

GND

--

---

VA

--------.

-----------Vs

--

-

Vn1

S

P

HA

DI SP

0.

5

ms

~

-

----

-3

.9

V

VDISP

VB

---

-

--

-2

.

lV

- - -

--

-

3.

9V

L_

VM

-

-----IV

...._

__ - - -

--

- -

2.8

V

6.8ms--

--

VA

-- ---

ov

...._

__ - - -

--

-

I.

8

V

11

E

ye

po

siti

on

30

°

o

Adj

u

stments of reference voltageVDISP

The VDISP had been precisely adjusted to become

-

3

.

74V at an

ambi

e

nt temperature of

20

°

C

and

-

4

.

29V at

0

°

C

.

In casethere

is

a

n

eed of

rea

d

justing the voltage after servicingthe LCDor exchanging

some of power source

components

,

be sure to look on the LCDfrom

30° of anglefrom the

v

e

rtical line while adjusting the pot.

:

D

.

mi-

Low sidevoltage of common signals

(Hl-H7)

for

LCD

.

Highside voltagefor segmentsignals

(S

l

-

S40)

Intermediate voltageof the common and

segm

e

nt signals

Lowsidevoltageof segment signals.

VA

,

VM and VB become pulses in an amplitude of several volts owing to influence

caused from the LSI.

VA:

VM:

VB

:

NOTE

:

ata

o The

liq

ui

d

cry

s

tal

refer

e

nce voltage

VDI

S

P

is

generated in the above

circ

ui

try in order to

avoi

d

occurrence of such unpleasant phenomena

as

blurred character or contrast

var

i

ation that might

degrade display

performance

,

which

is

caused by

a

slight voltage variation in the liquid crystal

refer

e

nce voltage VDISP, since the

5

x

7

dot matrix liquid crystal

is

use

d

in the

di

sp

lay of this

pock

e

t

com

pu

ter.

A)

VD

D

i

s

generated in the CPU

II

on the basis of VGG.

B) The gate

vo

l

tag

e

of MOSFET

i

s

controlled by the 250KS1pot to regurate the voltagefor VDISP.

Furthermore

,

the voltage of VDISP

is

changedby the thermistor to meet with temperature

varia

-

tio

n

,

so as to maintain proper display

performance

.

C) Line between the reference voltage VDISP and GND

is

d

ividedby resistor to make

o

u

t VA,VM

an

d

VB

.

V

DISP

:

2

0

°

o

C

PU

il

Yoo

Relation between

ternperture

and

VD

I

S

P

M

OS FET

ioo»

2-4. Power source

12

Pin No. Signalname In/Out Description

1

F4a Out Chip Enable signal(RAM3select signal)

2

F3a Out Chip Enable signal(RAM2select signal)

3

F2a Out Chip Enable signal(RAM

1

select signal)

4

Fla

Out Chip Enable signal(Displaychip

1

select signal,for input

buffer and transfer buffer usage)

During

display

:

Low

/

- -

-

- -

During read-in: turns momentarily high

6

VGG

In

Source

voltage("

-

"

voltageof battery)

7

VGG

In

8

Xin

In

Basicclock (pulse signalin 256KHz)

9

TE

S

Tl

Connected with GND

10 TEST2

11

RESET In All reset switch input

Normally high but turns low when the all reset switch

is

depressed.

12

R/Wa Out RAMData Read/Writesignal

Duringdisplay

:

High

________

Depressionof the key causesit momentary

low!

13

DIO

l

In/O

u

t Data Bus(for addressdesignation of the input buffer and

14 DI02

In/O

u

t transfer buffer in RAMand displaychip

1

).

15

DI03 In/Out During display: High

\_

16 DI03

In/O

u

t During

read-in

:

Low

17

B8a

O

u

t AddressBus(for addressdesignation

of

the input buffer and

18

B7a Out transfer buffer in RAMand display chip

1

)

.

19

B6a Out

20

BS

a Out During

display

:

___

Memen

t

ary generation

21 B

4a Out

22 B3a Out Duringread-in

:

lllllllllll

l

lllllllll

l

ll

l

23 B2a Out

24

Bla

Out

30 GND

In

Sourcevoltage

(OV)

40 S16a Out Busy signalto the CPUII (High during the execution in the

CPU

I)

During display: Low

Duringread-in

:

turns momentarily high

3. LSI SIGNAL DESCRIPTIONS

3-1. SC43157 (CPU

I)

13

No

.

Signalname

In

/Out Description

1

F4 Out Buzzersignal

Whenthe buzzer

is

off

:

Low

----i

0

.

2

5

msl--

Whenthe buzzer

is

on

:

LS1___J

2

F3 Out Chip Enable signal(Display chip

3

select signal)

3

F2 Out Chip Enable signal(Display chip 2 select signal)

4

Fl

Out Chip Enable signal(Display chip

1

selectsignal)

During display

:

Low

-----

_

__

Duringread-in: Turns mementarily high

5

VDD Out For liquid crystal drivevoltagepreparation (VDD :; VGG)

6 VGG

In

Source

voltage("-"

voltageof the battery)

7

VGG

In

-

8

Xin

In

Basicclock (Pulsesignalin 256KHz)

11

RESET

In

Allreset switch input

3

-

2.

SC43178 (CPU

II)

No

.

Signalname In/Out Description

-

41 Sn Out Key Strobe

signal

,

RAMAddresssignal

42

Si

Out Key Strobe signal,RAMAddresssignal

43 Sl3 Out Key Strobe signal

44

Sl2

Out

45

Sll

Out During display: High

46 SlO Out Depressionof the key causesit momentary low

47 S9 Out

48 S8 Out

49 S7 Out

50 S6 Out

51

SS

Out

52 S4 Out

53

S3

Out

54 S2 Out

55 Kil

In

Key input signal

56 Ki2 In

57 Ki3

In

Duringdisplay: Low

58 Ki4

In

Depression of the key causesit momentary high

59 S16b In Busysignalof the CPU II (high duringthe execution

of

the

(Ki5) CPUII)

I

During

display

:

Low

Depression

of

the key causesit momentary

high'.

n

14

No

.

Signal name

In

/Out Description

1

2

R/V

I Out RAM Data Read/Write signal

During display: High

During read-in: Turns momentarily

low-- - - -

- -

-

13

DI04 In/Out Data Bus (for data transaction between RAM and display chip)

14 DI03 In

/

Out During display: High

lS DI02 In/Out During read-in: Turns

low--l[lllll

16

DIOl In/Out

17

B8b Out Address Bus (for address designation of the display chip)

18 B7b Out During display

:

Bl

b=high

,

B2B=low

,

B3b=low,

B4b=low

,

19

B6b Out BSb=high,

B6b=

h

igh,

B7b=low

,

B8b=low

20 BSb Out During

read-in

:

Turns momentarily high

21

B4b Out

.

_

____

/

22 B3b Out

23

B2b Out

24 Blb Out

2

S

HA Out Displaysignal(Common signalcounting

pulse

)

.ruu

Be

i

ng generated during

displa

y

ing

--10.Smst--

26 DISP Out Displaycommand signal

During display: High

During

execution

:

Low

27

VM

In LCDdisplay voltage(Intermediate voltage of the segment

signal)

28 VA In LCDdisplay voltage(High sidevoltage

of

the segment

s

ignal)

29 GND

In

Supply voltage(OV)

30 H4 Out LCDcommon signals(backplate)

31

H7 Out

32 H3 Out

33 H6 Out

34 H2 Out

3S

HS

Out

36

Hl

Out

37

VDISP

In

LCDdisplay voltage(Low side

vo

ltage

of

the

c

ommon

signal

)

38

VB

In

LCDdisplayvoltage

(

Lo

w side

v

oltage of

t

he segment

signal

)

39

Sl6

Out Busysignalto the CPU

I

(

High during the

e

x

ecution in the

CPUII)

Duringdisplay

:

Low

/

Depressionof key causes

i

t momentarily

h

i

gh

.

40 SIS Out Record signalto the cassette tape and print

data

.

4

1

Sl4

Out Remote signalto the

M

T.

15

No

.

Signalname In/Out Description

42

Sl3

Out Busysignalto the printer.

43

Sl2

Out Expansion signal

-~

During

display

:

Low

Depressionof the CA (ON) key causesan instant pulse

generation

.

49

S6

Out For DEF symbol display(engaged

:

low, not engaged:high)

54 Sl Out For symbol display

(SHIFT

,

DGE

,

RAD,

GRAD

,

RESERVE,

PRO, RUN)

Samewaveformasthe segmentsignal.

55 Kil In CPU

I

Busysignal(High during the execution in CPU

I)

(Sl6a)

56

K.i2

In

Expansion signal

To be connected to Sl2 (CPUII) for

PC

-

1

2

11

.

57

K.i3

In Printer Busy signal

Low when the priner

i

s

not

operated

.

58

K.i4

In Printer connection identifying signal.

Low when the printer

is

not

connected

.

5

9

l

~

5

In

C

a

s

e

tte

r

e

p

ro

d

uc

t

s

ig

n

al.

60

K.i6

In ONkey input signal

1)

)

16

TC4019BP TC4066BP

(Quad

AND

-

OR se

l

ect gate)

(

Quad bi

l

ateral switch

)

1

4 13

1

5

CIN

IN/ouT

OUf

/

IN

1

3

1

2

1

5

2

CIN

12 4

IN/ouT our

/

IN

3

4

6

11

5

CIN

8

IN/ouT

OUT

/

IN

9

6

10

12

7

CJN

11

IN/our

OUT

/

IN

10

9

7

GND

5

4

2

6

3

2

5

4

3

7

GND

6

8

Vnn

1

4

1

3

1

2

11

1

0

9

Vno

1

4

13 12

11 10 9

TC4069

P

(

HEX

i

n

verter

T

C

4

011

U

BP

(

Qua

d

2

- input

p

osi

t

ive

NAN

D

gate

)

3

-

3

IC

17

Fi

g

4 -

2

Scr

ew

(c)

Sc

r

ew

(

e

l

Under

850

µ

A

Under 12µA

•

Measur

i

ng

c

u

r

ren

t

c

onsump

ti

on

Power source voltage.

4.

72

V

Current

consumpt

i

on

:

After depressthe ON key:

After depressthe

O

F

key

:

Fig 4-

1

Lac

h

•

Disass

e

mbl

y proc

edure

1

) Remove the

2

screws

(a

) and

2

s

c

rews (b

)

.

2) Separate the

upp

e

r

cabine

t

from the

l

ower cabinet

fr

om

the screw

side

,

a

s

the

y are

latched

togethe

r at three

points

,

A,

B

,

and

C

.

•

Repa

i

r

ing

pr

oc

e

du

re

1)

As

the

ba

c

k

o

f the

arithmeti

c

printed board

co

mes into

sight after the removal of the

lower cabinet, the arithmetic

printed board

ca

n be checked from the back

side

.

2) Replacement

o

f

the CPUII is

possible

.

3)

If

the key

printe

d

bo

ard

i

s

to be

checked

,

the arithmetic printed

bo

a

rd has to be

b

ent

i

n right

angle

afte

r

rem

ov

i

ng the screws(d) and (

e

). Inspection of the

C

P

U

I

is

possible

if

the

b

u

zzer

i

s

removed

a

f

ter

r

e

movi

n

g

the screw

(c)

.

4) The

k

ey

p

rinte

d

b

oar

d can be dismounted from the upper cabinet when the

9

screws

(f)

and

2 screws

(g

)

a

re

removed

.

But

,

c

are must be

e

xe

r

cise

d

i

n

dismo

u

nting the

p

rin

ted

board

,

as

key tops may

co

m

e

fa

llingdown one after

another

.

•

Replacement

of

th

e

LSI

1)

It

will be mu

c

h

c

onvenient if the

L

S

I

use soldering pencil

(UK

O

G

-007

8C

S

ZZ

)

i

s

u

se

d for

replacingthe LSI.

2)

Be

sure to

re

mov

e

t

he

ke

y printed board from the upper cabinet

first

,

i

f

the

L

S

I

on the key

printed board

is

to be removed.

If

the LSI was removed with the key printed

boar

d being

fitted on the

uppe

r

c

ab

in

et

,

there is a

possibilit

y of deforming the key rubber by

th

e

heat of

the

solderin

g

pen

c

il.

3

)

Be

sure

t

o cut the legs

o

f

IC

,

if IC was removed.

~--S

c

r

ew(b)

4.

ABOUT SERVICING

5

18

1

bit

4KHz

DATA"i

"

2

KHz

DATA"O"

1

=

Check sun code (after every

8

s

t

eps or one data

memory

.

)

2

=

8

steps of program or reserveprogram

3

=

End code of recording.

4

=

This gap, composed of all

"l

"

,

is

inserted at each step the recordingexceeds 80

steps

,

during

which teime the next 80 steps of data to be input

is

prepared in the input

buffer

.

5

=

All

"l"

is

recorded for

a

period of about

6

seconds in order to avoid non-recordable area

located at the top of the tape and

is

alsoused for the cueing of the recordinghead.

6

=

Withthis program or reserveprogram name

is

indicated.

7

=

File name

8

=

Data memory

is

indicated with this

code

.

9

=

Area for one data memory.

Recording method

Data "O" and

"l"

are identified by changingthe frequency of the recording signal

(F4")

.

Data memory recording format

Recording

format of

program or reserveprogram

Contents

of

program

or

reserveprogram

80 steps

4

1+1

5-1. Recording

Recor

di

ng

metho

d

5. CASSETTE OPERATION

19

KI

5

Ampl

i

f

i

er circu

i

t

Schmitt circu

i

t

CPU

11

Output signal from the EAR PHONE jack of the tape recorder

is

amplified

a

nd shaped in the

Schmitt

circuit

,

to be input to the CPUII through the

KiS

terminal of the CPU

II

.

5-2.

Reproduction

When recording signal

"1

"

is

t

o

be

rec

orded

,

Sl

5

is

turn

e

d l

ow level and the

sign

al

F4

(cl

o

ck

pulse

of

'..;'.

4KHz)

is

output during

t

hat

per

i

od

.

Whenrecordingsignal

"

O

"

i

s

to be

r

ecorded

,

SI

5

is

turned high level and the F4 output

is

inhibited during

t

hat

period

,

at

whi

c

h

durati

o

n

t

he

reverse

s

i

gnal of HA (clock pulse

of

:::

2KHz)

is

ca

rried on the recording

s

i

gnal.

Then

,

this signal

is

supplied to the MIC terminal

o

f the tape

re

c

orde

r

vi

a

the modulation

c

ircuit

of the

CE1

2

1.

Signalwaveform

a

t

he

tim

e

o

f

re

c

ord

i

ng

R

e

c

ording signal

(

F

4

11

)

F4

HA

s

15

., ~

F<

"

---+ To CE121 cassette

rnodulat

i

on

c

i

rc

ui

t

Sl5 ~

Recordingsignal

(F4

"

)

generation

cir

c

uit

a

rea

ring

TI

20

Deactivation of

the

·

relay

(cassette

to

stop running)

Lr

\

QA-u

\

Activation of

the

relay

(cassette to

start

runn

i

ng)

~Startup

of the cassette operation

~

Termination of the cassette operation

Sl4----i--~~~~~~~~~__.r--

The TC 4528P

is

a

mono-stable multivibrator which can perform trigger operation and reset

operation and two circuits are contained in the samechip.

"

A" outputs

a

pulsewhich

is

dependable on the time constant of CR at the fallingedge of the input

signal

,

and "B" outputs

a

pulse which

is

dependable on the time constant of CRat the risingedgeof

the input signal.The relay operates

ON

and OFF accordingto the current flow to the

coil

,

and it

is

activated when "A"

is

activeand deactivated when "B"

is

active.

NR-5711

-----..,

5

ru_

I

L------~

0.0

4.:7

PF

4

70Kn

100

2 Kn

4

Ain Q

6

2

SA733

MT A

REMOTO

5

Bin

QA

7

74'

W

(Sl4

)

TC452

8

BP

33

n

3

0

.

047

µF

VGG

100

8

1

4

Kn

8

in QB

10

2

SA7

33

83

B

GND

11

Bin

QB

9

1

4w

TC45

2

8BP

3

30

13

The CEl

21

will control the REMOTEterminal in automatic manner against the record, playback

and check commands.

5-3. Remote control

Sharp PC-1211 User manual

Popular Calculator manuals by other brands