Sharp CE-158 User manual
----SHARP----
SERVICE
MANUAL
CE-158
WWW.
PC
·
l500
.INFO
SHARP
CORPORATION
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ut Sharp P
C-
1500 at http://www.PC-1500.info
SERVICE MANUAL
MODEL
CE-158
RS-232C
Interface
(PC-1500
Option)
CON
T
ENTS
I.
Intro
du
ction . . . . _ .
..
. . . . _.
..
•
...
. . . .
..
. . . . . . . . - . . . - . . . .
2. Specification
....
_
..
...
.
..
..
.
...
.
...
.•.
- . . . . . . .
....
. . . . - . . J
3. System configuration . . . . . . . . . . . . . . . . . . • . • . . . . . . . • . . . . . . . . . . 2
4.
lllock
di
agram
..
. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
S. Circ
ui
t
di
scription . -
..
• . .
..
. .
...
. .
..
.
...
.
...
.
..
. . . . . . . . . . -
4-
8
6. l.si disc
ri
ption .
..
- . . .
....
. . . . . . .
..
. . . . .
....
. . .
..
. . •
...
. . 9- 17
7. IC pin connec
ti
on . - . . . . . . • . . . . . . . • . .
.•
..
...
...
. . .
.......
1
8-
20
8. Circuit diagram . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . 2J
9.
Co
lor chart
....
.
....
..
.
......
. . . . .
•..
. . .
...
. . . · · · • · · · ·
22-
23
lO. Parts Guide/Parts li
st
. . . . . . . . . . . . . • • . . • . . . . . .
...
.•
· · · · · · · ·
24
- 28
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nto
the
service manual
"PC
-
1500
&
Opt
i
on"
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1.
INTRODUCTI
ON
There
arc
cwo
cypc
s
of
interfaces built-in. One is a general-purpose interface for the communication
between
PC-
15011)
and a
devic
e equ
ipp
ed w
i1h
RS
-232C 1ype
i111erface
, such as personal computor,
pe
ripheral
de
vice
, etc. The 0
1h
er is a centronic$ type
paralle
l inter
face
for
full-scale data proc
ess
ing
pri
nt
ers.
2. RS-2
32C
INTERFACE SPECIFICATIONS
·
rransrnission
ll)Cthod
Applicable standards
Baud
ra
te
Data bit
Parity bit
Stop
bi1
Connectors used
Power supp
ly
source
Po\vcr
consu
n
1ptio
n
AC
adaptor/charger
Ba11ery
capacity
Output s
ig11al
level
Inter
fa
cing signals
Switch
Dilncns
i
ons
W
eigh
t
Acces
sor
ies
Asynchron
o
us
EIA
RS
-232C compliance
50
, 100, 110, 200,
300
, 600,
12
00,24
00
baud, programmabl
e•
5,
6,
7,Sbit
s,
p
rogra
mmabl
e
Eve
n,
odd
, no
n-
pa
rity)
progranunabJ
e
1, 1.5
for
1he character size
of
5. } programmable
2.0
for
the character
sizes
of
6
to
8.
60-pin
male
connector
fo
r connection
with
1he
PC
-1500 or
CE
-150.
25-pin connector,
DB
-
2S(W),
for
connection
wi1h
an
ex
ternal
devic
e.
Adaplorjack.
4.8 V
~
(DC): Ni
-Cd
recha
rg
eab
le
b:lllcry
AC:
120 V,
60
Hz
wilh EA-
21
A
4.8 V m (DC), 0.80 W
EA
-
21
A(120 V. 60 Hz)
For approx. 3 hours of operation
(c
harging:
15 hour
s)
High
le
vel:
+5
V to +
IO
V(3
to
7 Kohms load)
Low
l
evel:
- 5 V
to
-
10
V
(3
l<l 7 Kohms l
o:i
d)
Inputs:
RD,
DSR, Cl), C
TS
Outpu
ts
:
TD
, RTS,
DTR
01hcrs: SC
(F
G)
XI (
POWER
sw
itch)
86 (W) X
115
(D) X
SO
(H)
mm
3
-3
/8
"
(W)
X 4·17/32" (D) X
1-3
1/32" (H)
435 g(0.96
lb
s.)
Keyboard
1cmp
l
a1cs
, join! plales
(1wo
kinds) and
in
struction manual.
• :
In
terminal program mode, the
speci
ftca1ions
of
baud
rate
(600, 1200
:rn
d 2400) is restricted.
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3.
SYSTEM CONFIGURATION
CON,NECTION
OF
PC-1500
WITH
CE-158
CE·
15
8
Po
we
r switch
Joint plate
(A
)
CONNECTION
OF
PC-1500
WITH
CE-150
AND
CE-158
2
PC·1
5
00
""'
CE·158
Connee
tor
for
~
pa
rall
el
interface--
-+1-..:;;;
~~
AC
ad
apto
r
con
nection
jack
Connector
for
RS·232C
""
Jo
in
t plate (8 )
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50
A
ll
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at
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K.S
·
2J2C
llf
OS
·
:?
S(A)
PAR.=t.
lL
EL
llF
D
A.2$tB
J
4.
BLOCK DIAGRAM
•V'(+
OC
I
OC
V
e:>
CO
Nv
e
rueA
;;,.
GN
I>
$i.:1
:;
18
8
SNl'S
l
l}!)
A
•
Ve-
r-
-----
--
----
-
---
i't
l
'N
.
lt
JT
.------1.~
tf
=::i:::::=:-
-
·
:::
:::::::::::
--i--
---
~
···
C.
MOS
UAA
T
n=
=
=I
-
~
COP1
A54
ACI<
'"
'
,,.,
,"
It
•:
..
)~)
t:• (-c)l;!I
H
r--
--+•
-
-+
--~+
----------l}
A
lE
cu
s
r
--
+l
-
-'---
-1--1-
----~---
--
AOH
ES
SUS
RCM
S
C>Gll
XXX
CO 0
l!o:l
t;
K
H
~
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not sale this PDF!!!
Ej'.
-----
PU1, OM
Eo
!-
-"-----
-""·
•vcc
s
;NQ
tiO
PIN
C::O
l
lNl!C
l OR
3
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ll
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ut Sharp P
C-
1500 at http
:/
/www.PC-1500.info
5. CIRCUIT DISCRIPTION
• Power >upply
The CE·158 is driven
by
the PC·ISOO power (Vee) and Ni
-C
d
battery,
or through an AC
adapte
r.
The
input
is
fe
d through the DC-DC
co
nverter
to
reach VDO (+
5.0
V),
VC
+ (+9.0 V
),
and
VC-
(-
9.0
V).
Not
el
. Oat"' rlnc 1
i1
1
cr
(
ESD
-H-
1
4B
}
,__,-<>
V
C-
(- 9.
0V)
1W
100C
l
EA21Ay
1
00
1
X2
+
r--
~-
-.
l
ow
ba
tt
ery
det
ec
tion
Circu
it.
,__,-<>
VC
+ (+ 9.
0V
)
DC
-
DC
0.1
)I
f
P.GNO
-+-
-~'----;,_;....
~
'-
--·
S.
GND
1
6V
220µF
Con
Y
OtOI'
1---0
VD
oC
+ 5.0V }
Circuit
,__,..-<)
GNO
• Low battery detection circuit
4
Battery
condition is
monito
r
ed
by
th
e cir
cuit
s
ket
c
hed
below. Signals detected are check
ed
by
the
CPU for each receivi
ng
and transmilting st
ep
through LH58J I
's
PA5
1/0
port.
Be
sides,
SW6
reaches the GND level with
po
wer on,
ther
e
by
turning
on
2SA937R
to
keep
the
low
batte
ry
detection circuir in functi
on
.
+
SOV
11rF
2
SA93
7R
(SW6
}
3.
:lKO
560
KO 150
H438L
L01
Vee
100
KO
RV22KO 2SC2021RS
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at
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• 1 .
....
.
'
'
c
· ·
~
•• '"
·
~
...
No
te:
While
th
e power s
wit
ch
is
on
,
SW4
and
SWS
arc kept open
to
each otl1cr. V
ee
is
impressed
to the
base
of
2S
C2
02I, and 2
SC202
I and 258822 arc turned
on
.
•
1)
No
te
I : Data
lin
e filt
cr(E
SO.H·l4B)
•2)
Conve
rt
er H1750
•3) 3-terminal rcgul•tor
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at
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POWI
ER
SOURCE
(PC-1500,
CE-150,
CE-158)
PC"
500
CE·1
50
,
,~
.
...
,,
o-e=}--o
1SS9E
~A
INT(:R
(A.t50
AEGULATOA
OAIV€R
1001
)(
"1
•
Al;
MOTE
"'
=
su
M
CI
P
(:UIT
,:.
3
...
• •
••
vcc
V«
lO
W
941i
t.t-c:d -
C-':Q#fl
""~
..c
s
=
-
REY
oFF
-+--
ori-t--oi=r:
.. ~
·
'
'
'
V
e.a
' '
-
-·~·--·~·
-
'
'
'
'
Vu
'
L
'
V
¢.
'J
¢ L
Voo C
E-1
58
6
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at
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0 D D 0
p p p I)
B D B B
4 3 2 1
_T_l_R_C_L_O_C_K_
_.
PEOU
T 110
14
5696
Vee.
'l
oo
V
ss
• C
LOCK
circu
it
(S
W
2)
V
ss
15
0K
cl--
~~~~
-<
.,:-7=~~
'-..>-
~
CF
CTLA
C
TLe
1
54KHt
According to co
mm
ands f
ro
m the CPU, the frequency dividing
ra
tio
is
c
han
ged to make a cl
ock
pulse
co
rres
po
nd
ing to respecti
ve
baud rates. In initi
al
settin
g,
af
ter turni
ng
the power switch on,
the baud
ra
te
of
300
is
automatically provided. Thus a specified baud rate can
be
obtained with
ch•nge command from
the
CPU. The commands 3rC delivered
to
LH581 l ports
PCO
thru PC4,
PA6
or
P
A7
.
(T
/R clock= baud r3tc X 16)
•
CDP
1
854
ACE
CH
IPSELECT
The con
di
tions
to
se
l
ect
this chip are
that
CSI
and
CS3
arc
at
HIGH p
osi1
i
on
and that CS2 is at
LOW
po
si
ti
on
.
The
circuit isassh
own
be
low.
A015(1)
jd
)
A0
14
(1)
---
--l
-
·>--
- -
CS2
-
----
A012(1)
CS
3
.--
•
)
CS
1
A09
(1
110
8
AD
I RO/
WR
A0
15(t
A0
14
(1
~
)
·
:
~
I
)
)
\ .
11
0 13 (0
11
0 1
2(
1
A011 (0
11010(0
1109 (1
ME l
(1
_J
r-
40H1
38P
Y1
h
o,.
er;;
G1
c
B
A
Of-
0
of-
YI
• G1 •
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notsale this PDF !!!
0200
...
.............
WRITE
)
0201 ................ READ
7
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•
TPB
ClRCUIT
Y,
---
---.
0---
--~
TPB
M£ ,
Y, 0
PRO
~«;
CK
CL
V<x:
•
INT
CIRCUIT
A15
(1 /
A13\G)
-l-~
==
::::_
__
__,J
G>b
A1
2{
1)
r-
--
-iG
1
A11
(11
)--
--
+---
-C
A1
0(1
) 8
A9
(1)
- - - -
+-
-
---l
AS
ME
l
(1 )
-
--
~
X>-
- T
PB
The
lefr.hand circuir
is
10
produce
one
pu
l
se
at
ME,
(Y1) . At Y1 and
<Pos
.
however
,
two
pulses
are
generated
up
to
TPB.
The
re.
fore
, a stage
of
OFF
i.s
added
to
produce signal Q.
Thus
TPB consi
sls
of
Y1, Q,
and
¢OS·
INTERRUl'T
PORT
ADDRESS
(
DEOO)
ME,
I
DFFF
INTERR
U
PT
will
be
effective
Oll
ly c
ondilion
of
MEI, A9,
AlO
,
All,
A12
, AB
Al4
, A15,
(In
tcrrupl
will
proceed
adress
of
between
D£00
to
DFFF)
•
LH58
11 CHIPSELECT
8
AD1
S
(1
/
--
-<
AD14
(1) - -
-I
~O
H
1
38P
10---<)!G
>a
-
-4
-!:::===
:::::_-_J--<jG
>,•
A0·
13(0)
A012
(1)
A0
·
11
(0)
--
-----
-
f-
-IC
AD t
O(O)
8
A09
(0)
A
'--
---'
ME
1 (1) -
----
- -
--'
Vss
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(
Add
ress
0000
or
DOOF
to
be used)
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-1
500 at http
:/
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6.
LSI Discription
CDP1854A, COP1854AC Types
1.
Initialization
and Controls
In this mode. the CDPJ854A is configured to recei
ve
commands and send stal\Js
via
t
he
micro-
processor dat.a bus. The register connected
to
the transmitter bus
or
the receiver bus
is
determined
by the RD/WR and RSEL inputs as follows:
TAB
LE
1-Register
Se•,ct
i
on
:;um•nary
RSEL
RD{WR
Function
Low LO
\V
Load Transmitter Holding Register from Transmitter Bus
LO\\' High Read
Receiv
er Hod
Ung
Register from Receiver Bus
High
Low
LoadControl Register from
Tranm
1
iltcr
Hus
High Low Read
Status
Register from Receiver Bus
In this mode the CDPJ854A is compatible with a bidirectional
bu
s system.
The
receiver and trans·
rnitter buses are connected
to
the bus. The CLEAR
in
put
is
pulsed, resetting
the
Control, Status,
and Receiver Holding Registers
and
setting S.ERIAL DATA OUT(SDO) high. The Control Register
is
loaded
fron
n
th
e
Trans111itter
Bus
in
order
to dete
r1nine
the
oper3ting configuration
for
tlu?
UART
.
Data
is
transferred from the Transmitter Bus inputs
to
the
Control Register
du
ring TPB when the
UART
is
sel
ected
(CSI · CS2 · CS3
·1
) and the Control Register
is
designat
ed
(RSEL
= H. RD/
WR
= L
).
Titc CDPI854A also has a Status Register wltich can
be
read
onto
the Receiver Bus
(R
BUS
O-
R BUS
7)
in order to determine the status
of
the UART. Some
of
these status bits are also available
at separate te
rm
inals as indi
ca
ted
in Fig. 7.
2. Transmi
tt
er
Operation
Before beginning to traMmit. the TBANSMIT REQUEST
(TR)
bit in the Control Register(see b
it
assignment, Fig.
3)
is
set. Loading the Control Register w
it
h
TR
= I (bit 7 =
ihig)
1) inhibits changing
the
othe
r control bits. Therefore two loads arc required: one to format the UART, the second
to
set
TR
.
1~1ien
TR
has been set, a
TR
ANSMITTER HOLDING REGISTER EMPTY (THRE) inte
r-
rupt will occur. signalling the micropr<icessor that the Transmitter
Ho
lding Register
is
empty
and
may be loaded. S
ett
ing
TR
also causes asscrhon of a low
-l
evel
on
the REQUEST TO SENT
(R
TS)
output
to
the
peripheral.
It
is not necessary to set
TR
for proper operation for the UART.
If
de-
sired, it can
be
used to enable
THRE
intcrr
~1pts
and to generate the RTS s]gnaL The Transmitter
Holding Regist
er
is
loaded from the bus
by
TPB during exe
cutio
n
of
an
output
in
st
ru
ct
i
on
. The
CDPI
854A is selected
by
CS!
•
CS2
•
CS3
-
I,
and
the
Holding Regis
ter
is
se
lected
by
RSEL =
L
and
RD/WR =
L.
When the CLEAR
TO
SEND (CTS) input, which
can
be connected
to
a
peripheral device
output
, goes low, the Transmitter Shift Register
will
be
load
ed from the Transmi
t·
ter
Ho
lding Register and data transmissi
on
will
begin.
If
CTS
is
always low, the Transm
itte
r Shift
Register wi
ll
be
lo
ad
ed
on
t.he
first high-to.l
ow
edge
of
the clock which occurs at least 1/2 clock
period after 'the trailing edge
of
TPll
and
transmi
s.•
i
on
of
a start b
it
will occur 1/2 clock period
later (see
Fig_
I). Parity (
if
programmed)
and
stop bit(s) will be transmitted fo
ll
owing
the
last data
bit.
If
the
word
len
gUt
selected
is
Jess than 8 bits, the most signifi
ca
nt unused bits in the transmitter
shift register w
ill
not
be
transmitted.
One tran
smitte
r clock per
io
d after the Trnnsmitter Shilt Regist
er
is
loaded from the Transmitter
Holding Regi
ster
, the THRE signal
will
go
l
ow
and an interr
upt
will
occur
(INT
goes low). The next
character to
be
transmitted can t.hen
be
loaded
into
the Transmilter Holding Register for trans-
mission
with
its
start
bi!
immediale
ly
following
the
lasl
stop
bit
oft
he
previous
character.
This
cycle
can
be
repea
ted
until the l
as!
character
is
transmitted,
at
which time a final
THRE
· TSRE
intern
1
pt
will occur.
T11is
in
terrupt signals the microprocessor that
TR
can
be
turned
off. This is done by
9
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reloading the original control
byte
in the
Cont
rol Register with
I.he
TR
bit=
0,
thus terminating
the
REQUEST
TO
SEND (RTS)signal.
SER
I
AL
DATA OUT (SDO) can
be
heldlow
by
setting the BRcAK bit
in
the
Control Rcgister($ee
Fig
.
6)
.
SDO
is
held
low
until
the BREAK
bi
t
is
reset
DYNAMIC ELECTRICAL CHARACTERISTI
CS
at
TA . -
40
tC>
+85°C,
Voo
±5%,
t,
,
tf-20ns,
VIH . 0.7
Yoo
·
VIL=
0.3
Voo
·
CL
•
100
pF. See Figs.
1and2
.
LIMITS
CHARACTERISTIC
Voo
COPl8S4A CDP·l854AC UNITS
(V)
Typ
."
• • •
Max.
Typ
. Max.
Trransmitter Timing-MOOE I
Minimum Clock
Period
ICC
5
2so
310
2SO
310
10
125
ISS
ns
--
Minimum
P11lse
Width: lCL s I00 125 100 125 ns
Clock Low Level
10
75
100
--
Clock
High
Level l(;H s I00 125
JOO
1
25
10 75
100
ns
--
TP
B
ITT
5 100 150 100
ISO
10
so
75
ns
- -
Mi
nimum
Setup
Time:
IT
C s 175
22
5 175 22S
TPB toClock 10
90
I
SO
ns
- -
Pr
opagation Delay Time:
tco
s
300
450
300
450
ns
Clock
to
D
ata
Start Bit
JO
I
SO
225
--
'rPB
to
THRJO
t·1TH 5
20
0
30
0
200
300
10
100 1
50
ns
--
Clock to THRE
tent
5
200
30
0
200
300
ns
10 100 150 - -
CPU lnicrface -
W~TE
Timing-
MO
DE I
Minimum Pulse Wid01: ITT 5 100 ISO 100
ISO
TPB
so
75
ns
10 --
Minimum Setup Time:
tRSW
5
50
74
50
7S
RSEL to Write 10
25
40
ns
--
Data
to
Write tow 5 -100 -
75
100
-75
ns
10
-SO
-35 --
Minimum Hold Time:
IWRS
s
so
75
so
75
ns
RSEL afterWrite 10
25
40
- -
Data afterWrite
two
5
15
12S 15 125
10
40
60 ns
--
• Typicalvalues are for T
11
= 2S°C
and
nominal voltages.
• Maximum limits
of
minimum characteristics
are
the
values above which
all
devices function.
10
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notsale this PDF !!!
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ll
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at
http
:/
/www.PC-1500.info
TRA
NSMIT
TER
HOt.
OING..
TRAN$M
1r r
£H
$tUFT
.,.:
REGI
ST
ER
LOA
OEO
REGISTER LDA
DED
T C
LO
(;
K
WNI
TEI
tT
PB
! I l T , , •
.........,.:
tr
ru
:
.....;
:-
1c1t-1
~
-·
.
T...,
E
____
_,
soo
-:
~
tc o
I' ' D
AT
A.
SIT
•
THE
BOLDING REGISTER IS LOADED
ON
THE
TRAillNG
EDGE
OFT
PB
••
THE
TRA
NS
Ml1TER
SHIFT
REGISTER
IS
LOADED
ON
Till\
FIRST
HIGH
-
TO.LOW
lRt\!'I
SITION
OF T
f!
E CLOCK
WHI
CH OCCURS AT LEAST I
/2
CL
OCK
PERIOD + lTC
AFTER
THE
TRAIUNG
EOGE
OFTPB
, ANO TRANSMISSION
OF
A
START
BITOCCURS 1/2CLOCK PERIOD
+tep
LATER.
WRITE IS T
llE
OVEl!LAP
OF
TPB,
CSI
, AND CS3
=I
AND CS3.
Rll
/
WR
•
0.
Fig. I - Transmiller liming dia
gram
-
MODE
I.
•
1501'1
' •
;-.-err·~
T
P
~---
-----------
-:;:,.,~
:---•
Rsw
75
ni
:
;...1wa
s
...
t1\
--
--------
-~~----t
•
>-+--
--~·--~·~--
11
SEL
• i
~
X
~--
_
-;!
'.
: 1 125n1
11
:-•Dv1~
:--
wo
::t,
,_
__
_
TS
US:
0-
f
SUS
7
--------
----"-----II,__
__
__
_._
__
./\..
__
_
11
•
WRIT!>
IS THE OVERLAP
OF
TPB.
C:
SJ,
CS3
=I
AND CS2. RO/WR • O.
Fig. 2 -
MOD
E I cpu inte.rface (WRITE) t
im
ing diagram.
Do
notsale this PDF!!!
11
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at
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CONTROL
REG
ISTER BIT ASSIGNMENT TABLE
Bit
Signal
7
TR
6
BREAK
5
IE
4 3
WLS
2
WI.SI
2
SBS
I
EPE 0
Pl
Bil
Signal: Func1ion
12
0 PAR
l1Y
INHIBIT (Pl):
When
sea
high parity gcneralion :llld vcrificalion are lnhibiled and the PE Status bit
is
held low.
If
parity
is
inhibited the s
top
bits(s) will immediately follow
1he
last
da1a
bil
on
1ransmission.
and EPE is ignored.
EVE
N PARITY ENABLE (EPE):
When set high. even parity
is
generated by
the
transmillcr
and
checked by
the
receiver. Wilen
low, odd parity is selected.
2 STOP BIT SELECT (SllS):
Sec tab
le
below.
3 WORD
LENGTH
SELECT I (WLS
I):
See table below.
4 WORD LENGTH
SEUiCT
2 {WLS2
):
See
1abl
e below.
Bit
4 Bil 3 Bit 2
WLS2 WLSI SBS
0 0 0
0 0 1
0 I 0
0 I 1
0 0
0 1
0
Function
5data bits, I stop b
it
Sdata bias, J.S stop bits
6
da
1a
bias, I
stop
bit
6 data bits, 2 stop bits
7 data bits, I
stop
bit
7 data bias, 2
stop
bits
8 dala bits, 1 stop
bit
8
da1a
bits, 2 stop bits
Fig. 3 - Cont
rol
Rcgistar bit assignment.
5
INTERR
UPT
ENABL
E
(IE
):
When set high THRE. DA. THRE · TSRE,
CTS
. :llld PSI interrupts are enabled (see ln1errupt
Conditions. Table II).
6 TRANSMIT BREAK (
BR
EAK):
Holds SDO low when set. Once the break bit in the control regis1er has been set high. SDO will
s
1ay
low until the break bil is r
ese
t low and
one
of
the following occu
rs
: CLEAR goes low; CTS
&oes
high;
or
a word is transmilled. (The 1ransmit1ed word
wil.I
nol be v
al
id since there c
an
be no
starl bit
if
SDO
is
already
low
. SDO
r;.1n
be sci high without intermediate transitions
by
trans·
millinga word consisting
of
a
ll
zeros).
7 TRANSMIT REQUEST
(T
R):
Wh
en
set
high
, RTS
is
set low a
nd
data transfer through the 1ransmit1cr is initiated
by
the
ini
t
ial
THRE interrupt. (When loading
the
Control Register from 1he bus, th
is
(T
R)
bit
inhibi1s
cha
ng-
ing
of
othercontrol Oip.nops.)
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1500 at http://www.PC-1500.info
3. Receiver Operation
The
receive
operation begins when a start bit is detected
at
the SERIAL
DA
TA
IN
(SDI) input.
After detection
of
the first
high
·to-low t
ra
nsition on the
SDI
line, a valid start bit is verified by
check
ing
for a
low
-l
ave!
input
7-1/2
receiver clock
peri<>ds
later.
When
a
vaUd
start bit
has
been
verified, the following data bits, parity bit
(if
programmed) and stop bit(s) are shifted into the
Receiver Shift Register by clock pulse 7-1/2 in each bit time. The parity
bit
(if programmed) is
checked and receipt
of
a valid stop bit
is
verified. On count 7
-1
/2
of
the first stop bit, the
received
data
is
l
oa
ded
into
the
Rec
eiver Holding
Regis1er
. If the word length
is
l
ess
than 8 bits, zeros (low
output
le
ve
l) a
rc
loaded into the unused most significant bits. If
DATA
AVAILABLE
(DA) has not
been reset by tbe time the Receiver Holding Register
is
loaded, the
OVERRUN
ERROR (OE) status
bit
is
set. One half clock period later, the PARITY ERROR
(PE.)
and
FRAMING
ERROR (FE)
status bits become valid
for
the character
in
the Rec
ei
ver
Holding Register. At this time, the Data
Available status bit is also set and the Data
Avai]able
status bit
is
also set and the
DATA
AVAILABLE
(DA) and INTERRUPT (INT) outputs
go
low, signalli
ng
the microprocessor that a
received charac.ter is ready. The
mic
roprocessor
res
p
ond.<
by executing an input instruction. The
UART's 3-state bus drivers
are
enabled when the UART
is
selected (
CS!
·
CS2
·
CS3
= I) and
RD/WR
= high. Status
can
be
re
ad
when
RS
EL=high. Data is read
when
RSE
L =
Low
. When read-
ing
data,
TPB
lat
ches data
in
the microprocessor and resets
DAT
A
AV
Al
LAB
LE
(DA) in the
UAR
T.
The preceding sequence
is
repeated
fo
r each serial character
which
is
received from the peripheral.
STATUS REGISTER
BIT
ASSIGNMENT
TABLE
Bit
7 6 5 4 3 2 I 0
Signal THRE TSRE
PSI
ES
FE
PE
OE
DA
Also
Availa
ble
22•
14
15
15
19•
at Te
rminal
•P
olar
ity
r
eversed
at
o
ut
put te
rminal
,
Fig.
4 - Status Re
gi
ster bit assignment
BIT
SIGNAL:
FUNCTION
0 DATAAVAlLABLE(DA):
When
set high, this bit indicat
es
that an entire character
has
been
received
and
tr
ansferred
to
the
Rec
ei
ver
Holding
Registe
r.
11\is
signal
is
also available at
Tem1
.
19
but with its polarity
reversed
.
OVERRUN
ERROR (OE):
When
se
t hi
gh,
this bit indicates that the Data Available bit
was
not reset before the next
character
w"'
transferred
to
the Receiver Holding Register. This
signal
OR
'ed with
PE
is output
at
Term
. 15.
2
PARITY
ERROR(PE):
When
set h
igh
, this
bit
in
d
icat
es
that the received parity bit docs not compare to that
pro-
grammed by the
EVEN
PARITY
ENABLE
(
EPE)
contro
l.
This bit is updated each
time
a
character is trans
fe
rr
ed
to
the Receiver Holding Register. This
signal
OR'ed
with
OE
is
output
at
Tenn.
15.
3
FRAMING
ERROR (FE):
When
se
t hi·
gh
, this bit indicates that the rece
iv
ed character
has
no
valid
stop
bit, i.e
.,
the
bit
following the parity bit
(if
programmed) is
not
a
high-l
eve
l voltage.
Th
is bit
is
updated each time
a character is transferred
to
the
Rec
eiv
er Holding Register. This si
gnal
is
also
avail
able at Term.
14.
4
EX
T
ER
NALSTATUS(ES):
This
bit
is set
high
by a l
ow.
level
input at Tenn. 38(ES).
13
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at
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5 PERIPHERAL STATUS
IN
TERRUPT (PSI):
This
bit
is
set high by a
high·t<>-lo
w voltage transition
of
Term
.
37
(PSI
).
The INTERRUPT
out
.
put
(Term. 13) is also asserted ( INT = low)
whe
n this bit
is
set.
6 TRANSMITTER SHI
FT
REGI
ST
ER E
MPTY
(TSRE):
Wh
en set high, this bit indicates that the Transmitter Shift Register has completed ser
ia
l trans·
mission of a
fu
ll
character including st
op
bit(s).
It
remains sci until the start or trans
mi
ssion of
rh
e next cha
ra
cter.
7 TRANSMITT
ER
HOLDING R
EG
ISTER EMPTY (THRE):
Wh
en set high, this bit indicates that the Transmitt
er
Holding Register has transferred its
contents to
the
Transmitter
Sh
ift Register and may be reloaded
wi
th a new character. Setting this
bit also sets t
he
THRE
output
(Term. 22) low
and
causes an INTERRUPT (I
NT=
low),
if
TR is
high.
4. Peripheral Interface
14
In addition
to
serial data in and out, fo
ur
signals arc provided for communicationwith a peripheral.
n ie REQUEST TO SET
NT
(RTS) o
utput
sign
al al
er
ts
th
e periphe
ra
l to
ge
l ready 10 recei
ve
da
ta
.
The
CLEAR TO SE
ND
(CTS)
inpu
t sign
al
is
the response, signalling that the peripheral is ready. The
EXTERNAL STATUS (ES) input latches a peripheral Slatus level, and
the
PERIPHERALSTATUS
IN
TER
RUPT
(P
SI) input
senSC$
a status edge (high·lo·low)
and
also generates an interrupt. For
example, the modern DATA
CA
RR
IE
R DETECT line could be connected
to
the
l'sfinpu
l
on
t
he
U
ART
in ord
er
to
si
gn
al
t
he
microprocessor
th
at t
ra
nsmission failed because of loss
of
the
carri
er
on the commu
ni
cations lin
e.
The PSI and ES bits arc stored in the Status Regist
er
(See Fi
g.
4).
~
:-
1oc•
so1
-----i
: S
fAAT
Bil
PAHnY
I
srOP
e
rr
t
A(AO••
~~--
-t-
-----~------------
-T-'--
-
--t
I
TT~
TPS
___
__,
OE
•
'------
--------
-
---
_.)
;
!--
• C
OL
:
ICP~
:----:
···
~-
---------------------
-.;,....;_
1'C
Pt
,.....-.
Ft;I
- -
-------
---
-----
-
--
-=-
-'--
Fig. 5 - MODE I receiver timing diagram.
' I
I'
A
ST
A
RT
BIT
OC
CU
RS AT A
TIME
LESS
THA
N
Toe
DEFO
RE
A f
ll
GH·
'f().LOW TRANSI
TIO
N
OF
'Jl
lE
CLO
CK. THE
ST
ART
BIT
MAY
NO
T RE RECOG
NIZE
D UN
TI
L THE NE
XT
J
llG
ll
·T
O·l..OW
TRANSITION
OF
THE
CLOC
K, THE
ST
AR
T
arr
MAY
IHO
COM
PLE
TELY
ASYNC
HR
ONOUS WI
T.H
TllEC
L
OC
K.
" READ JS
TH
E
OVER
LAP
OF
CSI,
CS
3.
RD/WR • 1A
ND
CS2
•
O.
II'
A PE
ND
I
NG
DA
HAS
N
OT
B
EEN
CL
EARE D BY A REA D O F
THE
R
ECE
IVER
HOLDING
R
EGIS
TER BY
THE
TIME A NEW
WO
RD IS
LOADED
t
NTO
Tll
E
RECEIVE
R
llOLDINC
REG
I
STE
R,
Til
£
0F.
SIGNAL WILL
COME
TRUE.
t
0£
AND
P£
SHARE
TER
M
INAL
JS
AN
D
ARE
ALSO
AVAILABLE
AS
1'1'0
SEPARATE
BITS JN
TIIE
STATUS
REG
I
STER
.
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ll
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at
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DYNAMIC ELECTRICAL CHARACTERISTI
CS
at
TA=
-40
to
+85°
C,
Voo
:it
5%, tr.
If=
20
ns,
V
1H
= 0.7
Vo
o. VIL =
0.3
Vo
o .
DL
= 100 pF. See F
igs.
5 and
6.
LIMITS
Yoo
CHARACTERISTIC CDPJ854A CDP1
85
4A
C UNITS
(V)
Min.
Typ.•
Max.
•
Min
.
Ty
p.
• •
Max
.
Recei
ver
Timing -MODE 1
Minimum Clock
Pe
ri
od
5 -
250
310
-
25
0 310
tee
10 125 155 ns
- - - -
Minim
um
Pulse Width:
te
l 5 -
10
0 1
25
-
100
1
25
Clock L
ow
Level
JO
7S J
OO
ns
- - - -
Clock
High
Level 5 -
100
125 -
100
12S
ten
JO
75
10
0 ns
----
TPB t
rr
5 -1
00
15
0 -
100
1
50
10
so
75
ns
- - - -
Minimum Set
up
l ime: 5 -JOO ISO -
100
150
DataStart Bit
to
Clock 1
Dc
JO
50
75 ns
-- - -
Propagation
Dela):'.
Time: 5 -
220
325 -
220
3
25
TPB to
DA
'l'A AVA
l[
Al
All and more about Sharp PC-1500
at
http:f/www.PC-1500.info
~•rr
-;
TP9
~
~~~~~~~~~~~
~~
~tnsr
_;
;._
tTAS
-:
ASEL
~~~~~~~~~
v-~
~~~
-1
•~~~...,._
~--..,
;,...-~~
~~
II
* READ IS
THE
OVERLAP
OF
CS
!.
CS3. RD/WR • I ANDCS2 • 0
Fig. 6 - MODE I
cpu
inte1facc (READ) timingdiagram
TABLE 2·1nte
rrupt
Set
and Reset Cond
iti
ons
SET
*
(I
NT=
LOW)
RESET
(INT
=
HIGll
)
CAUSE CONDITION TIME
DA
Re
ad
of
datn TPB leading edge
(Receipt of dat
a}
THR
E* Read
or
Stntus
or
TPB leading edge
(Ability
to
reload) write
of
chara
cter
THRE
•
TSRE
Read
of
status
or
TPB leadingedge
(Transmitter
done)
write
of
character
PSI
Read
of
status TPB trailing edge
(Negat
ive
edge)
CTS Read
of
st
:i
tus TPB leading edge
(Positive edge wh
en
THRE ·
TSRE
)
•
Int
err
up
ts will occur only
af
t
er
lhe
1£
b
it
in the Control R
cg
islcr
(se
c Fi
g.
3) has been set.
• TH
RE
will
cause an inter
rupt
on
ly
:a
fter the
TR
bit in
th
e Co
nt
ro
l Register (see Fig. 3) has been
se
t.
FUNCTIONAL DEFI
NIT
IONS FOR CDP1854A
TERMINALS
~
1
0DE
I
SIGNAL: FUNCTION
vDD:
P
os
itive supply voltage
MOD
E
SE
L
ECT
(MODc):
A higll·level voltage
at
this
input
selects
MODE I
operation.
VSS:
Ground
CHIP SELECT 2 (CS2):
A
lo
w·lcvcl voltage at
th
is
input ll>gether with
CS I and
CS
3 selects
th
e COPI8S4A
UA
RT
.
RECEIVER
BUS
(R BUS 7 · R
BUS
0):
16
Receiver parallel data
outputs
(may
be
ex
·
ternally connected to corresponding tran
smit
·
tcr bus terminals).
INTERRUPT
(IN
T):
A low·lcvel voltage
al
this
output
indicates
the
p1escncc
of
one
of
more
of
the interrupt con·
ditions listed in Table2.
FR
A
MI
NG
ER
ROR
(FE)
:
A high-level voltage
at
this
outpu
t indicat
t!S
t
hat
th
e 1eceive
cl
character h
as
no
va
lid st
op
bit, i.e.. the bit fo
ll
ow
ing
th
e paii
ty
bit (if
pr
ogramme
d)
is
no
t a high·levcl volt:tgc. This
ou
tp
ut is
updated
e
ach
li
me
a chnraclcr is
transferred
10
the
Receiver Holding Register.
PARITY
ERROR
or
OVERRUN
ERROR
(PE{OE):
A hig)l·lcvcl voltage
at
this
output
indicat
es
that either
the
PE
or
OE b
it
in the Sll1Us
Register
ha
s been set (see Status Register Bit
Assi
gnme
nt
, Fig.
4)
.
R
EG
ISTER SELECT (RSEL):
Th
is
Input is used to choose either
the
Control
/S
tatlls Register (high input)
or
the
transrnltter{receiver data registers (low
input)
according10 the
lruth
table
in
Table
I.
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RECEIVER
CLOCK
(RC
LO
CK)
:
Cl
oc
k
in
put with a frequen
cy
16 t
im
es
the
de·
si
red receiver shift rate.
TPB
:
,\
pos
it
ive
inJ)U
t
pu
l
se
used
as
a
da
tal
oad
or reset
st
ro
be.
DATA
AVAI
L
AB
LE(DA)
Al
ow
·le
vcl
vo
ltage at this output ind
ica
tes
tl
tat an entire c
ha
ract
er
has been received and t
rans
fe
rred
to the
Re
ce
i\
•er Holdi
ng
Register.
SERIAL
DATA
IN (SDI):
Serial data r
-cce
i
ved
on th
is
input
li
ne enters the Recei
ve
r
Sh
ift R
egi
ster at a point detennined by
th
e c
ha
r
ac
ter length. A hi
gh
·
leve
l input volta
ge
mus
t be present
whe
n data is not
be
ing
re
ceived.
CLEAR (C
LEAiR)
:
A l
ow
.l
eve
l vol
tage
at
this input
res
ets
tl
1e I
nt
errupt F
li
p.Flop,
Re
ceiver Holding
Regis
ter, Control
R
egis
ter,
ancl
S
ta
t
us
Re
gister,and sets SERIAL
DATA
OUT
(SDO) hi
gh
.
T
RA
NSMITTER
HO
L
DING
R
EGI
STER
EMPTY
(THRE):
A low.le
ve
l
vo
ltage
at
th
is output indicates that
tl
1e
Transmitter
Hol
di
ng
Regist
er
h
as
t
ra
nsferred its
contents
to
the Tran
sm
itter
Sh
ift
Re
gis
ter and
may
be
re
loa
de
d with a newcharacte
r.
CH
IP
S
ELEC
T
:I
(CS!):
A
hi
gh·l
eve
l voltage at tllis input
toge
th
er
wit.
h
CS2
and
CS3
se
lects the UART.
REQ
UEST
TO S
END
(RTS):
Tltis output si
gna
l
te
lls
the peripheral to to
ge
t ready to recei
ve
data. CLEAR TO SE
ND
(C
TS) is
the
res
ponse
from
the pe
ri
pheral. RTS
is
set to a low
·l
e
ve
l
vo
ltage
whe
n data
is
latched in the Tra
ns·
mi
lter
Mo
ld
ing
Re
gister or TR
is
se
t high, and
is
re
set high when both tbe Transrnitter Holding
Registerand TransmitterShift R
egis
ter a
re
em
pty and
TR
is l
ow
.
SE
RI
AL
DATA
OUT
P
UT
(S
DO
):
The contents of the Transmitter
Sh
i
ft
Reg;s
1er
(start bit, data bits, parity bit, and stop
bi
t(s) are
ser
ia
ll
y shifted out
on
this output.
Wh
en
no
cha
ra
cter is be
ing
transmitted, at high l
evel
is
mai
n·
t
ai
ncd. Start of transmi
ss
ion is defined
as
tlle trans
it
ion
of
the start
bi
t from a
hi
g
h.l
e
vel
to a
low
·
le
vel
oulpul voll
ag
e.
TRA
N
SMITTE
R
BUS
(T B
US
0 · T
BUS
7)
:
T
ra
nsmi
tter pa
ra
llel
data inpu
t.
Th
ese may be externa
ll
y connected to
co
rrespond
in
g
Recei
ve
r
bu
s
1c
nn
i
na
ls
.
RD
/
WR
:
A
low
.
Jcvel
volta
ge
at
this inp
ut
gates data
fr
om
th
e
tra
nsmitter
bu
s to
the
Transmitter
Mo
ldin
g
Re
gi
ster or
the
Con
tr
ol R
egis
ter aschosen
by
registe
r
sele
c
t.
A hi
gh-l
eve
l vohage
ga
t
es
data from
th
e
Re
ce
iver
Holding Register or the S
ta
tu
s Register,
as
chosen by re
gist
er
se
lect, 10 the
rece
i
ve
r
bus.
CH
IP SELE
CT
3
(CS3
)
With hig
h·
levcl
vo
l
ta
ge
at this input together w
it
h
CS
I and
CS2
se
lects the
UA
RT.
PE
R
IPH
E
RA
LST
AT
US INTERRUPT (
PSI
):
A
hi
gh
·t
O·l
ow
transition on this input line ·sets a bit in the Status Re
gis
ter and cau
ses
an
INT
E
R·
ROPT
(INT
=lo
w}
.
EX
TERNAL ST
AT
US (ES):
A low.J
cvc
l voltage at tllis input sets a bit in the Status R
egi
ster.
C
LEAR
TO
SEND (C
TS
):
When
th
is input from peripheral is hi
gh
,
tr
ansfer of a character
to
the T
ra
nsmitter Shiirt Register
and
shi
f
tin
g
of
se
ri
al
dala on\ is i
nh
ibited.
T
RA
NSM
I
TTE!R
CL
O
CK
(TCLO
CK):
Clock input
wi
th a
fr
equen
cy
16
ti
mes
the
desired transmi
tt
ershift rate.
17
Do
notsale this PDF!!!
All and more about Sharp PC-1500
at
http:f/www.PC-1500.info
7. IC PIN CONNECTION
TC40Hl38P
Pin
connections
DATA OUT
PU
T
•
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f>
"I •
A 8 C
SELECT
ffi
628
Gl
Y7
Vss
ENABLE
8Cf~UT
TC40H
07
4P
Block diagram
Logic d
iagram
SE
LE
CT B
• Protectivc
ci
rcuits pr
ov
i
de
d for a
ll
in
pu
ts
T
C40
HO
JOP
Pin
connections
Voo
14 13
IC
1Y
3C
38
2 0 0 5 12 0 0 g
3
CK
0 6 1t CK o 8
PR'
TR
• V
$S
: 7
10
TC
40H36
8P
I
Gl
11\
1Y
2A
2V
3A
18
8
Vss
1/\
18
2A
TC
40H027
P
Pi
n
con
ne
cti
o
ns
IC
Do notsale this PDF !!!
2C
w
y;
w
w
w
VS'
Vlf
VY
2Y
Vu
3A
v
..
D
ATA
OUTPUT
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