Silicon Laboratories UDP C8051F960/Si1020 User manual

Rev. 0.1 10/11 Copyright © 2011 by Silicon Laboratories UPMP-F960-EMIF
UPMP-F960-EMIF
UDP C8051F960/Si1020 MCU CARD WITH EMIF
USER’SGUIDE
1. Introduction
The Unified Development Platform (UDP) provides a development and demonstration platform for Silicon
Laboratories microcontrollers and the Silicon Laboratories software tools, including the Silicon Laboratories
Integrated Development Environment (IDE).
Figure 1. Unified Development Platform
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2. Relevant Documents
This document provides a hardware overview for the Unified Development Platform (UDP) system UDP
C8051F960/Si1020 MCU Card with EMIF. Additional information on the UDP system can be found in the
documents listed in this section.
2.1. Motherboard User’s Guide
The UDP Motherboard User’s Guide contains information on the motherboard features and can be found at
www.silabs.com.
2.2. Card User’s Guides
The UDP MCU Card and Radio Card User’s Guides can be found at www.silabs.com.
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3. Hardware Setup
3.1. Using the MCU Card Alone
Refer to Figure 2 for a diagram of the hardware configuration when using the MCU card without a UDP
motherboard.
1. Connect the USB Debug Adapter to the 2x5 debug connector on the MCU card with the 10-pin ribbon
cable.
2. Connect one end of the USB cable to the USB connector on the USB Debug Adapter.
3. Connect the other end of the USB cable to a USB Port on the PC.
4. Move the SW5 VBAT switch to the middle VREG position.
5. Move the SW7 VIO switch to the upper VBAT position.
6. Move the SW12 VIORF switch to the upper VBAT position.
7. Connect the 9 V DC adapter to P1.
Notes:
Use the Reset button in the IDE to reset the target when connected using a USB Debug Adapter.
Remove power from the MCU card and the USB Debug Adapter before connecting or disconnecting the
ribbon cable from the MCU card. Connecting or disconnecting the cable when the devices have power can
damage the device and/or the USB Debug Adapter.
Figure 2. Hardware Setup using the MCU Card Alone
USB Debug Adapter
USB
Connectivity
Power
Adapter (P1)
VBAT
Switch
VIORF
Switch
VIO
Switch
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3.2. Using the MCU Card with the UDP Motherboard
Refer to Figure 3 for a diagram of the hardware configuration when using the MCU card with a UDP motherboard.
1. Connect the MCU card to the UDP motherboard slot.
2. (Optional) Connect the I/O card to the UDP motherboard slot.
3. (Optional) Connect a radio card to the radio card slot in the UDP motherboard.
4. (Optional) Connect an EZLink card to the EZLink card slot in the UDP motherboard.
5. Connect the USB Debug Adapter to the 2x5 debug connector on the MCU card with the 10-pin ribbon
cable.
6. Connect one end of the USB cable to the USB connector on the USB Debug Adapter.
7. Connect the other end of the USB cable to a USB Port on the PC.
8. Connect the ac/dc power adapter to power jack J20 on the UDP motherboard. The board can also be
powered from the J16 USB or J1 mini USB connectors.
9. Move the SW5 VBAT switch on the MCU card to the VREG position.
10. Move the SW7 VIO switch on the MCU card to the upper VBAT position.
11. Move the SW12 VIORF switch on the MCU card to the upper VBAT position.
12. Move the S3 power switch on the UDP motherboard to the ON position.
Notes:
Use the Reset button in the IDE to reset the target when connected using a USB Debug Adapter.
Remove power from the target board and the USB Debug Adapter before connecting or disconnecting the
ribbon cable from the target board. Connecting or disconnecting the cable when the devices have power
can damage the device and/or the USB Debug Adapter.
The MCU card can be used alone without the motherboard. However, the motherboard must be powered if
an MCU card is connected.
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Figure 3. Hardware Setup using the Unified Development Platform
3.3. CP210x USB to UART VCP Driver Installation
The MCU Card includes a Silicon Labs CP210x USB-to-Dual-UART Bridge Controller. Device drivers for the
CP210x need to be installed before the PC software can communicate with the MCU through the UART interface.
If the "Install CP210x Drivers" option is selected during installation, a driver “unpacker” utility will launch.
1. Follow the steps to copy the driver files to the desired location. The default directory is
C:\SiLabs\MCU\CP210x.
2. The final window will give an option to install the driver on the target system. Select the “Launch the
CP210x VCP Driver Installer” option if you are ready to install the driver.
3. If selected, the driver installer will now launch, providing an option to specify the driver installation location.
After pressing the “Install” button, the installer will search your system for copies of previously installed
CP210x Virtual COM Port drivers. It will let you know when your system is up to date. The driver files
included in this installation have been certified by Microsoft.
4. If the “Launch the CP210x VCP Driver Installer” option was not selected in step 3, the installer can be
found in the location specified in step 2, by default C:\SiLabs\MCU\CP210x\Windows_2K_XP_S2K3_Vista.
At this location, run CP210xVCPInstaller.exe.
5. To complete the installation process, connect the included USB cable between the host computer and the
J17 USB connector on the UDP MCU card. Windows will automatically finish the driver installation.
Information windows will pop up from the taskbar to show the installation progress.
6. If needed, the driver files can be uninstalled by selecting “Silicon Labs CP210x USB to UART Bridge Driver
Removal” option in the “Add or Remove Programs” window.
USB Debug Adapter
Power
Adapter
(J20)
USB
Connector
(J16)
VBAT
Switch
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4. UDP C8051F960/Si1020 MCU Card with EMIF Overview
The UPMP-F960-EMIF MCU card enables application development on the C8051F960 MCU. The card connects
to the MCU Card expansion slot on the UDP motherboard and provides complete access to the MCU resources.
Each expansion board has a unique ID that can be read out of an EEPROM or MCU on the board, which enables
software tools to recognize the connected hardware and automatically select the appropriate firmware image. The
target MCU card can also be detached from the UDP and used alone as a development or demonstration tool.
Figure 4 shows the UPMP-F960-EMIF MCU card.
Figure 4. UPMP-F960-EMIF UDP MCU Card
Figure 5 highlights some of the features of the UDP C8051F960/Si1020 MCU Card with EMIF.
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Figure 5. UDP C8051F960/Si1020 MCU Card with EMIF
4.1. UPPI Pico Board Connector (J5, J6, J7, J8)
The UPPI Pico Board connector accommodates a variety of C8051F96x and Si102x/3x UPPI Pico Boards. The
C8051F960 MCU and Si1020 Wireless MCU UPPI Pico Boards share a common form factor. This enables the
MCU card to support a wide variety of wired and wireless applications.
The supported UPPI Pico Boards include:
UPPI-F960
UPPI-Si1020GMxxxTR
The Si1020/30 UPPI Pico Boards include an EZRadioPRO®transceiver. The C8051F960 UPPI Pico Boards do not
include an RF transceiver; instead, these boards support most Silicon Labs 40-pin radio test cards when used with
the Unified Development Platform Motherboard.
Debug Connector
9 V Wall Adapter
Connector
VIO Switch
VIORF Switch
VBAT Switch
UPPI Pico Board
Connector
Potentiometer Pulse Counter
Terminals
Reset Push-Button
Push-Button Switches
and LEDs
Mini-B USB
Connector
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4.2. Push-Button Switches and LEDs (SW1–SW4, LED1–LED4)
The UDP C8051F960/Si1020 MCU Card with EMIF has four push-button switches. The four switches connect to
P3.0 through P3.3. The switches are normally open and pull the pin voltage to ground when pressed.
Port pins P3.0 through P3.3 also connect to four LEDs: LED1 through LED4. The LEDs connect to VIO through a
current limiting resistor.
This multiplexing arrangement reduces the number of port pins used from eight to four. Firmware may easily use
either the LED or the switch for each port pin. When using both the LED and the switch on the same port pin,
firmware must momentarily toggle off the LED by writing a 1 to the pin’s port latch to read the push-button switch
status.
4.3. VBAT Selection Switch (SW5)
The UDP C8051F960/Si1020 MCU Card with EMIF has many power options. The VBAT selector switch (SW5)
selects the power source for the main C8051F960/Si1020 VBAT supply pin.
The center VREG position selects the output of the on-board 3.3 V regulator (U1). This is the primary supply option
for development. The on-board regulator has multiple 5 V and 9 V power sources connected via Schottky diodes to
the regulator input. The highest voltage power source will supply power to the regulator.
The power sources for the on-board regulator (U1) are as follows:
9 V DC Wall Adapter power receptacle (P1).
Mini-B USB receptacle (J17).
10-pin Debug connector (J13).
UDP motherboard +5 V (when connected).
The BATT position selects the ultra long life 3.6 V lithium thionyl chloride battery (BT1). This battery is a typical
power source for metering applications. The on-board regulator should be used primarily for development because
the battery has a limited peak current capacity.
The UDP position on the VBAT selector selects the UDP motherboard programmable supply (PWR_VDD_OUT) as
the power source for the UPPI Pico Board. Use this position when using the programmable power supply under
software control.
The UDP motherboard can also provide power to the on-board regulator. The VREG position will always work with
the motherboard, while the UDP switch position requires some motherboard configuration. The UDP motherboard
User’s Guide contains additional information.
The VBAT voltage and ground are available on test points in the top-left corner of the MCU card. Use these test
points to power the board from an external lab power supply. When using a lab supply, the VBAT selector switch
should be in the BATT position with the battery removed.
4.4. Debug Header (J13)
The standard 10-pin debug header supports the Silicon Labs USB Debug Adapter. This connector provides a C2
debug connection to C8051F960/Si1020 on the UPPI Pico Board. The USB Debug Adapter supports two types of
debug connections: C2 and JTAG. When using this MCU card with the Silicon Labs IDE, select C2 in the
connection options dialog before connecting.
The USB Debug Adapter also provides a 5 V power source that can power the regulator. When powering the MCU
from the debug connector, the VBAT switch must be in the VREG position. Additionally, select the Power Target
after Disconnect check box in the Silicon Labs IDE connections options dialog to ensure the MCU always has
power.
4.5. Reset Button (SW6)
The reset push-button switch is in the lower-right corner. Pushing this button will always reset the MCU. Note that
pushing this button while the IDE is connected to the MCU will result in the IDE disconnecting from the target.
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4.6. Pin Power Supply Select Switches
The C8051F960/Si1020 MCU has two VIO pins: VIO and VIORF. These VIO pins set the logic level and drive
voltage for the MCU port pins. The VIORF pin sets the level for the port pins normally supporting radio functionality:
P1.5 through P2.3. The Si1020 P2.0-2.3 pins are connected internally to the EZRadioPRO. The VIO pin sets the
level for all other port pins.
4.6.1. VIORF Select Switch (SW12)
When using the dc-dc buck converter to power the radio, set the VIORF selector switch to the VDC position. This
connects the output of the buck converter to the VIORF pin. When using the Si1020, this switch also selects the
power source for the radio. In this position, firmware controls the voltage on the VDC pin. The C8051F960/Si1020
buck converter also has a bypass switch that can power the radio from the full supply voltage. The dc-dc buck
converter and bypass switch are off by default after an MCU reset, so the VDC pin voltage is floating until firmware
turns on the bypass switch or configures the dc-dc converter.
When the VIORF selector switch is set to the VBAT position, the VIORF pin connects via hardware to the VBAT
pin. In this position, the dc-dc buck converter cannot power the radio.
The VBAT position powers the VIORF pin without any firmware. This position is more convenient for simple code
examples. Use this position for the code examples provided unless otherwise indicated.
4.6.2. VIO Select Switch (SW7)
The VIO selector switch provides the same functionality as the VIORF switch for the main VIO pin. Normally this
switch should be in the VBAT position, which will set the drive and input levels of the pins to VBAT.
Setting the switch to the VDC position connects the VIO pin to the output of the buck converter. In this position, the
battery powers the MCU, and all of the I/O ports operate at a lower voltage set by the buck converter. This option is
best if most of the I/O pins connect to a low voltage radio or other low-voltage peripherals. Most applications should
use the VBAT position.
The C2 connection requires a VIO power source and VDC is not powered by default, so the VBAT position must be
used for initial development.
4.7. UART VCP Connection Options
The MCU card features a USB virtual COM port (VCP) UART connection via the mini-B USB connector (J17). The
VCP connection uses the CP2102 USB-to-UART bridge chip.
The UART pins on the target MCU either connect to the CP2102 USB-to-UART bridge chip or to the UDP
motherboard. The MCU card has level translators with enables that normally route the UART connections to the
on-board USB-to-UART bridge chip. However, the UDP motherboard can drive the enable pins to route the UART
connections to the UDP motherboard instead of the on-board USB-to-UART bridge chip. There are two enable
signals: one with a default pull-down (UART_VCP_EN) and one with a default pull-up (UART_SYS_EN).
When using the UART with either the on-board USB-to-UART bridge or the UDP motherboard, install shorting
blocks on header P12 to connect P0.4 to MCU_TX and P0.5 to MCU_RX.
If desired, install shorting blocks for hardware handshaking on P0.6 and P0.7 on the P12 header. Hardware
handshaking is not required for most applications. Firmware must implement hardware handshaking on the target
MCU using P0.6 and P0.7. These pins also connect to the 40-pin radio card I2C signals by default. If necessary,
disconnect these signals by cutting the traces on R9 and R10.
The MCU card includes provisions to facilitate ultra-low power measurements. The UART pins of the target MCU
are completely disconnected from the USB-to-UART bridge by removing all the shorting blocks on P12. The VIO
supply powers the level translator. To remove the level-shifter current from the ultra-low power measurement, cut
the trace on the bottom of the board between the two pins of header J20. This will completely disconnect the level
translators from VIO. After cutting this trace, a shorting block is required on J20 to use the USB-to-UART bridge or
UDP UART connection.
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4.8. Potentiometer (R50)
The potentiometer is available on P1.4. To facilitate a low-power potentiometer, P2.7 connects to bottom of the
potentiometer as a potentiometer enable (POT_EN). Drive P2.7 low to enable the potentiometer. Alternatively,
install a 0 resistor for R51 to continuously enable the potentiometer.
4.9. Pulse Counter Terminals (J14)
The MCU card includes a 4-position screw terminal connection. These field-wiring terminals will accept large wire
for a commercial water or gas meter. The PC0 and PC1 signals connect to P1.0 and P1.1 on the target MCU.
These are dedicated pins for the C8051F960/Si1020 low-power pulse counter. The VIO and ground connections
are also available for Form C meters. Refer to the C8051F960 data sheet for additional information about the pulse
counter.
4.10. Port Pin Headers (J9-J12)
All of the MCU port pins are available on the 0.100 inch headers on either side of the UPPI Pico Board.
Pins P1.2 and P1.3 are normally used for the RTC and are not connected by default to the P1.2 and P1.3 headers.
To use P1.2 and P1.3 for other purposes, remove the RTC crystal on the UPPI Pico Board and populate the two
small adjacent resistors with 0 resistors.
When using the Si1020 UPPI Pico Board, the SPI1 pins are connected internally and do not connect to the header
pins.
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4.11. UPMP-F960-EMIF Board Default and Optional Connections
The UPMP-F960-EMIF MCU card has many default and optional connections for use with different radios and the
UDP motherboard. The default connections have shorting jumpers consisting of a 603 resistor footprint with a trace
between the pads. To disconnect a default connection, cut the trace between the pads. To reconnect, install a 0 
603 resistor or connect the two pads with solder. The optional connections are non-populated (no-pop) resistor
footprints. To connect, install a 0 603 resistor or connect the two pads with solder.
When using the Si1020 UPPI Pico Board, some of the MCU port pins connect to EZRadioPRO port pins by default.
Note that plugging the UPPI Pico Board into the MCU card will connect some pins together.
Table 1 shows a summary of the default and optional connections for each pin.
Table 1. MCU Pin Functions
MCU Pin MCU Card Function UDP Motherboard Signal
Default Optional Default Optional
P0.0 SPI_LCD_SCK EBID_SCK
P0.1 SPI_LCD_MISO EBID_MISO
P0.2 SPI_LCD_MOSI EBID_MOSI
P0.3 VREF SPI_LCD_NSS
P0.4/TX TX
P0.5/RX RX
P0.6 CTS EZR_I2C_SDA
P0.7 RTS EZR_I2C_SCL GPIO2
P1.0 PC0
P1.1 PC1
P1.2 XTAL3
P1.3 XTAL4
P1.4 POT EZR_ARSSI
P1.5 GPIO_1 EZRP_RX_DOUT/
EZRP_GPI0_1 EZR_FFIT
P1.6 EZRP_NIRQ
P1.7 EZRP_SDN
P2.0/SCK1 EZRP_SCK
P2.1/MISO1 EZRP_MISO
P2.2/MOSI1 EZRP_MOSI
P2.3/NSS1 EZRP_NSS
P2.4 PIEZO
P2.5 GPIO_0 EZRP_TX_DATA_IN/
EZRP_GPIO_0
P2.6 SPI_LCD_A0
P2.7 POT_EN
P3.0 SW1/LED1
P3.1 SW2/LED2
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4.11.1. P0.0 through P0.3
Pins P0.0 through P0.3 connect to the UDP SPI_LCD signals (SPI_LCD_SCK, SPI_LCD_MISO, SPI_LCD_MOSI,
SPI_LCD_NSS) by default. These signals support the optional Graphical LCD display I/O card when used with the
UDB motherboard. To disconnect these default connections, cut the traces on R1 through R4. Optionally, these
signals can also connect to the EBID SPI on the 40-pin radio card. R8 provides an option to use P0.0 as a voltage
reference.
4.11.2. P0.6
Pin P0.6 connects to EZRP_I2C_SDA by default. This signal supports I2C radios and EZRadio transceivers using
the 40-pin radio connector on the UDP motherboard.
4.11.3. P0.7
Pin P0.7 connects to EZRP_I2C_SCL by default. This signal supports I2C radios using the 40-pin radio connector
on the UDP motherboard. The MCU card provides optional connections to connect P0.7 to EZRP_RX_CLKOUT or
use P0.7 as the IREF current reference pin.
4.11.4. P1.4
Pin P1.4 normally connects to the potentiometer. Optionally, P1.4 can connect to EZR_ARSSI. This signal supports
an analog RSSI measurement using an EZRadio 40-pin test card.
4.11.5. P1.5
Pin P1.5 connects to GPIO_1 via R15 and R29 by default. To disconnect this signal, cut the trace on R15. This
signal supports the clear-to-send (CTS) signal for EZRadioPRO.
4.11.6. P1.6
Pin P1.6 normally connects to nIRQ using R17. Cut the trace on R17 to disconnect these signals. Note that P1.7
also connects to nIRQ on the UPPI Pico Board, so a trace on the UPPI Pico Board must also be cut.
4.11.7. P1.7
Pin P1.7 connects to SDN via R18. To disconnect these signals, cut the trace on R18. P1.7 also connects to SDN
on the UPPI Pico Board, so it is necessary to also cut a trace on the UPPI Pico Board.
4.11.8. P2.4
P2.4 normally connects to the PIEZO signal. This signal drives a piezo transducer on the graphical LCD I/O card.
4.11.9. P2.5
Pin P2.5 connects to the GPIO_0 via R20 and R28 by default. Cut the trace on R20 to disconnect these signals.
This signal supports direct mode communication with the Si1020 EZRadio.
4.11.10. P3.6
P3.6 normally connects to SPI_LCD_A0. This signal supports the Graphical LCD display I/O card.
P3.2 SW3/LED3
P3.3 SW4/LED4
P3.4 RF_EBIF_NSS
P4.6 ANT_A EZR_CLKIN/
EZRP2_GPIO3
P4.7 GPIO2 EZRP_RX_CLKOUT/
EZRP_GPIO2
Table 1. MCU Pin Functions
MCU Pin MCU Card Function UDP Motherboard Signal
Default Optional Default Optional
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4.11.11. EZRadio GPIO Signals
When using a Si1020 UPPI Pico Board, the four EZRadioPRO GPIO signals connect to the SMA connectors on
the motherboard.
GPIO_0 connects to EZRP_TX_DATA_IN via R20. This signal supports direct mode TX input data from an external
source using the SMA connector.
GPIO_1 connects to EZRP_RX_DOUT via R21. This signal supports direct mode RX data out of the SMA
connector. Normally, the RX data out is used with the RX clock out.
GPIO_2 connects to EZRP_RX_CLK_OUT via R22. This signal supports direct mode RX data out of the SMA
connector.
ANT_A connects to EZR_CLK_IN using R23. This provides a connection to the forth SMA connector. Cut the trace
on R23 when using an external 10 MHz clock with EZRadio.
4.11.12. EMIF Connections
Some of the EMIF lines also connect to the 40-pin radio card connector. EMIF_A15/- connects to GPIO_2, and
EMIF_A14/- connects to GPIO_3. Disconnect these signals when using the EMIF in 16-bit address non-
multiplexed mode.
Table 2 describes the UPMP-F960-EMIF MCU card’s EMIF connections.
Table 2. MCU EMIF Connections
MCU Pin EMIF Configurations MCU Card Signal
Name UDP Motherboard Signal Name
Non-Multiplexed Multiplexed
16-bit 8-bit 16-bit 8-bit
P3.5 ALE ALE EMIF_ALE EMIF_ALE
P3.6 /RD /RD /RD /RD EMIF_RD EMIF_OEB
P3.7 /WR /WR /WR /WR EMIF_WR EMIF_WRB
P4.0 A8 EMIF_A8/- EMIF_A16
P4.1 A9 EMIF_A9/- EMIF_A17
P4.2 A10 EMIF_A10/- EMIF_A18
P4.3 A11 EMIF_A11/- EMIF_A19
P4.4 A12 EMIF_A12/- EMIF_A20
P4.5 A13 EMIF_A13/- EMIF_A21
P4.6 A14 EMIF_A14/- EMIF_A22
P4.7 A15 EMIF_A15/- EMIF_A23
P5.0 A0 A0 A8 EMIF_A0/A8/- EMIF_A8
P5.1 A1 A1 A9 EMIF_A1/A9/- EMIF_A9
P5.2 A2 A2 A10 EMIF_A2/A10/- EMIF_A10
P5.3 A3 A3 A11 EMIF_A3/A11/- EMIF_A11
P5.4 A4 A4 A12 EMIF_A4/A12/- EMIF_A12
P5.5 A5 A5 A13 EMIF_A5/A13/- EMIF_A13
P5.6 A6 A6 A14 EMIF_A6/A14/- EMIF_A14
P5.7 A7 A7 A15 EMIF_A7/A15/- EMIF_A15
P6.0 D0 D0 AD0 AD0 EMIF_D0/AD0 EMIF_A0
P6.1 D1 D1 AD1 AD1 EMIF_D1/AD1 EMIF_A1
P6.2 D2 D2 AD2 AD2 EMIF_D2/AD1 EMIF_A2
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P6.3 D3 D3 AD3 AD3 EMIF_D3/AD3 EMIF_A3
P6.4 D4 D4 AD4 AD4 EMIF_D4/AD4 EMIF_A4
P6.5 D5 D5 AD5 AD5 EMIF_D5/AD5 EMIF_A5
P6.6 D6 D6 AD6 AD6 EMIF_D6/AD6 EMIF_A6
P6.7 D7 D7 AD7 AD7 EMIF_D7/AD7 EMIF_A7
Table 2. MCU EMIF Connections (Continued)
MCU Pin EMIF Configurations MCU Card Signal
Name UDP Motherboard Signal Name
Non-Multiplexed Multiplexed
16-bit 8-bit 16-bit 8-bit
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5. Using the UPMP-F960-EMIF with the UDP Motherboard
5.1. VBAT Selector Switch
When used with the UDP motherboard, the motherboard can power the UPMP-F960-EMIF MCU card. With the
VBAT selector switch in the VREG position, the motherboard powers the regulator on the card. With the VBAT
selector switch in the UDP position, the UDP motherboard powers VBAT directly. This position supports software
control of the variable voltage power supply and current measurements.
The S1 switch on the UDP motherboard selects between the fixed or programmable voltage. The variable supply is
controlled by the C8051F384 board control MCU through the U1 digital potentiometer. Use the fixed supply when
the variable supply is not under software control.
5.2. Current Measurement
The power measurement circuitry on the UDP motherboard consists of a Silicon Labs C8051F351 8051 MCU that
measures both input voltage and current consumption of the MCU card, I/O expander, and radio card. When using
the VBAT selector in the UDP position, install a shorting block on the UDP Motherboard J13 connecting the two left
pins together.
Figure 6. Power Measurement Diagram with Shorting Block
UDP motherboard
power
to I/O card
power
I/O card IN
power
to Radio card
power
Radio card IN
power
to MCU card
power
MCU card IN
power
J15 J14 J13
C8051F351
JP3 JP2 JP1R24 R15 R6
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5.3. MCU Card Header Connections
The UPMP-F960-EMIF MCU card has four connectors with 100 pins each. These 400 pins are directly tied to the
UDP motherboard and I/O cards. These signals are named and designed to support a wide variety of features and
applications, and the UDP C8051F960/Si1020 MCU Card with EMIF card implements a subset of these
connections.
The MCU cards and I/O cards are designed so that a maximum number of functions are shared between each
card. This allows a particular type of I/O card to be shared amongst all MCU cards that connect to the same
signals.
The MCU card slot includes the following components:
J1 MCU card connector H1
J2 MCU card connector H2
J3 MCU card connector H3
J4 MCU card connector H4
The UPMP-F960-EMIF MCU card implements the signals described in Table 4, Table 5, Table 6, and Table 7 in the
Appendix.
5.4. Shorting Blocks: Factory Defaults
The UDP C8051F960/Si1020 MCU Card with EMIF comes from the factory with pre-installed shorting blocks on
several headers. Figure 7 shows the positions of the factory default shorting blocks.
Figure 7. Shorting Blocks: Factory Defaults
Shorting blocks are installed on P2 to connect P0.4 to MCU_TX and P0.5 to MCU_RX.
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6. Schematics
Figure 8. UPMP-F960-EMIF UDP MCU Card Schematic (1 of 6)
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Figure 9. UPMP-F960-EMIF UDP MCU Card Schematic (2 of 6)
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Figure 10. UPMP-F960-EMIF UDP MCU Card Schematic (3 of 6)
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Figure 11. UPMP-F960-EMIF UDP MCU Card Schematic (4 of 6)
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