Silicon Laboratories EFR32xG14 Wireless Gecko User manual

EFR32xG14 Wireless Gecko
Reference Manual
The Wireless Gecko portfolio of SoCs (EFR32) includes Mighty
Gecko (EFR32MG14), Blue Gecko (EFR32BG14), and Flex
Gecko (EFR32FG14) families. With support for Zigbee®, Thread,
Bluetooth Low Energy (BLE) and proprietary protocols, the Wire-
less Gecko portfolio is ideal for enabling energy-friendly wireless
networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable high-power amplifier, an integrated balun and no-compromise MCU
features.
KEY FEATURES
• 32-bit ARM® Cortex-M4 core with 40 MHz
maximum operating frequency
• Scalable Memory and Radio configuration
options available in several footprint
compatible QFN packages
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Integrated balun for 2.4 GHz and
integrated PA with up to 19 dBm transmit
power for 2.4 GHz and 20 dBm transmit
power for Sub-GHz radios
• Integrated DC-DC with RF noise mitigation
Timers and Triggers
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports Analog I/F
Lowest power mode with peripheral operational:
USART
Low Energy
UARTTM
I2C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
ADC
VDAC
Analog
Comparator
EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Other
Op-Amp
IDAC
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
RFSENSE
MOD
FRC
RAC
Frequency
Synthesizer
PGA
PA
I
Q
RF Frontend
LNA
RFSENSE
PA
I
Q
RF Frontend
LNA
To 2.4 GHz receive
I/Q mixers and PA
To Sub GHz
receive I/Q
mixers and PA
To Sub GHz
and 2.4 GHz PA
Sub GHz
2.4 GHz
BALUN
CRYPTO
CRC
True Random
Number Generator
SMU
Core / Memory
ARM CortexTM M4 processor
with DSP extensions, FPU and MPU
Debug Interface RAM Memory LDMA Controller
Flash Program
Memory
Real Time
Counter and
Calendar
Cryotimer
Timer/Counter
Low Energy
Timer
Pulse Counter Watchdog Timer
Protocol Timer
Low Energy
Sensor Interface
Clock Management
H-F Crystal
Oscillator
L-F Crystal
Oscillator
L-F
RC Oscillator
H-F
RC Oscillator
Auxiliary H-F RC
Oscillator
Ultra L-F RC
Oscillator
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Table of Contents
1. About This Document ........................... 26
1.1 Introduction...............................26
1.2 Conventions ..............................26
1.3 Related Documentation ..........................27
2. System Overview ............................. 28
2.1 Introduction...............................28
2.2 Block Diagrams .............................29
2.3 MCU Features Overview ..........................30
2.4 Oscillators and Clocks ...........................32
2.5 RF Frequency Synthesizer .........................32
2.6 Modulation Modes ............................32
2.7 Transmit Mode .............................33
2.8 Receive Mode ..............................33
2.9 Data Buffering ..............................33
2.10 Unbuffered Data Transfer .........................33
2.11 Frame Format Support ..........................33
2.12 Hardware CRC Support ..........................34
2.13 Convolutional Encoding / Decoding ......................34
2.14 Binary Block Encoding / Decoding ......................34
2.15 Data Encryption and Authentication ......................35
2.16 Timers ................................36
2.17 RF Test Modes .............................36
3. System Processor ............................ 37
3.1 Introduction...............................37
3.2 Features................................38
3.3 Functional Description ...........................38
3.3.1 Interrupt Operation ..........................39
3.3.2 Interrupt Request Lines (IRQ) ......................40
4. Memory and Bus System .......................... 41
4.1 Introduction...............................42
4.2 Functional Description ...........................43
4.2.1 Peripheral Non-Word Access Behavior ...................45
4.2.2 Bit-banding .............................45
4.2.3 Peripheral Bit Set and Clear .......................46
4.2.4 Peripherals .............................47
4.2.5 Bus Matrix .............................48
4.3 Access to Low Energy Peripherals (Asynchronous Registers) ..............51
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4.3.1 Writing ..............................52
4.3.2 Reading ..............................54
4.3.3 FREEZE Register ..........................54
4.4 Flash .................................54
4.5 SRAM ................................55
4.6 DI Page Entry Map ............................56
4.7 DI Page Entry Description ..........................58
4.7.1 CAL - CRC of DI-page and calibration temperature ...............58
4.7.2 EXTINFO - External Component description .................59
4.7.3 EUI48L - EUI48 OUI and Unique identifier ..................60
4.7.4 EUI48H - OUI ...........................60
4.7.5 CUSTOMINFO - Custom information ...................60
4.7.6 MEMINFO - Flash page size and misc. chip information .............61
4.7.7 UNIQUEL - Low 32 bits of device unique number ...............62
4.7.8 UNIQUEH - High 32 bits of device unique number ...............62
4.7.9 MSIZE - Flash and SRAM Memory size in kB .................62
4.7.10 PART - Part description ........................63
4.7.11 DEVINFOREV - Device information page revision ...............65
4.7.12 EMUTEMP - EMU Temperature Calibration Information .............65
4.7.13 ADC0CAL0 - ADC0 calibration register 0 ..................66
4.7.14 ADC0CAL1 - ADC0 calibration register 1 ..................67
4.7.15 ADC0CAL2 - ADC0 calibration register 2 ..................68
4.7.16 ADC0CAL3 - ADC0 calibration register 3 ..................68
4.7.17 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) ..............69
4.7.18 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) ..............70
4.7.19 HFRCOCAL6 - HFRCO Calibration Register (13 MHz) .............71
4.7.20 HFRCOCAL7 - HFRCO Calibration Register (16 MHz) .............72
4.7.21 HFRCOCAL8 - HFRCO Calibration Register (19 MHz) .............73
4.7.22 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) .............74
4.7.23 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) .............75
4.7.24 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) .............76
4.7.25 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) ..........77
4.7.26 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) ..........78
4.7.27 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz) ..........79
4.7.28 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz) ..........80
4.7.29 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz) ..........81
4.7.30 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz) .........82
4.7.31 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz) ..........83
4.7.32 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz) .........84
4.7.33 VMONCAL0 - VMON Calibration Register 0 .................85
4.7.34 VMONCAL1 - VMON Calibration Register 1 .................86
4.7.35 VMONCAL2 - VMON Calibration Register 2 .................87
4.7.36 IDAC0CAL0 - IDAC0 Calibration Register 0 .................88
4.7.37 IDAC0CAL1 - IDAC0 Calibration Register 1 .................89
4.7.38 DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0 ...........89
4.7.39 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 ...........90
4.7.40 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 ...........91
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4.7.41 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 ...........92
4.7.42 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 ...........93
4.7.43 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0 .........93
4.7.44 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 .........94
4.7.45 VDAC0MAINCAL - VDAC0 Cals for Main Path ................95
4.7.46 VDAC0ALTCAL - VDAC0 Cals for Alternate Path ...............96
4.7.47 VDAC0CH1CAL - VDAC0 CH1 Error Cal ..................97
4.7.48 OPA0CAL0 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 .....98
4.7.49 OPA0CAL1 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 .....99
4.7.50 OPA0CAL2 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 ....100
4.7.51 OPA0CAL3 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 ....101
4.7.52 OPA1CAL0 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 ....102
4.7.53 OPA1CAL1 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 ....103
4.7.54 OPA1CAL2 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 ....104
4.7.55 OPA1CAL3 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 ....105
4.7.56 OPA0CAL4 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 ....106
4.7.57 OPA0CAL5 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 ....107
4.7.58 OPA0CAL6 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 ....108
4.7.59 OPA0CAL7 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 ....109
4.7.60 OPA1CAL4 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 ....110
4.7.61 OPA1CAL5 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 ....111
4.7.62 OPA1CAL6 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 ....112
4.7.63 OPA1CAL7 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 ....113
5. Radio Transceiver ............................114
5.1 Introduction..............................115
6. DBG - Debug Interface ...........................116
6.1 Introduction..............................116
6.2 Features...............................116
6.3 Functional Description ..........................116
6.3.1 Debug Pins............................117
6.3.2 Debug and EM2 Deep Sleep/EM3 Stop ..................117
6.3.3 Authentication Access Point ......................117
6.3.4 Debug Lock ...........................118
6.3.5 AAP Lock ............................118
6.3.6 Debugger Reads of Actionable Registers .................119
6.3.7 Debug Recovery ..........................119
6.4 Register Map .............................119
6.5 Register Description ...........................120
6.5.1 AAP_CMD - Command Register ....................120
6.5.2 AAP_CMDKEY - Command Key Register .................120
6.5.3 AAP_STATUS - Status Register ....................121
6.5.4 AAP_CTRL - Control Register .....................121
6.5.5 AAP_CRCCMD - CRC Command Register ................122
6.5.6 AAP_CRCSTATUS - CRC Status Register .................122
6.5.7 AAP_CRCADDR - CRC Address Register .................123
6.5.8 AAP_CRCRESULT - CRC Result Register .................123
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6.5.9 AAP_IDR - AAP Identification Register ..................124
7. MSC - Memory System Controller ......................125
7.1 Introduction..............................125
7.2 Features...............................126
7.3 Functional Description ..........................127
7.3.1 User Data (UD) Page Description ....................127
7.3.2 Lock Bits (LB) Page Description.....................128
7.3.3 Device Information (DI) Page .....................128
7.3.4 Bootloader ............................129
7.3.5 Device Revision ..........................129
7.3.6 Post-reset Behavior .........................129
7.3.7 Flash Startup ...........................130
7.3.8 Wait-states ............................130
7.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP) ............131
7.3.10 Cortex-M4 If-Then Block Folding ....................131
7.3.11 Instruction Cache .........................132
7.3.12 Low Voltage Flash Read .......................133
7.3.13 Erase and Write Operations......................133
7.4 Register Map .............................134
7.5 Register Description ...........................135
7.5.1 MSC_CTRL - Memory System Control Register ...............135
7.5.2 MSC_READCTRL - Read Control Register ................136
7.5.3 MSC_WRITECTRL - Write Control Register ................137
7.5.4 MSC_WRITECMD - Write Command Register ...............138
7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer ..............139
7.5.6 MSC_WDATA - Write Data Register ...................139
7.5.7 MSC_STATUS - Status Register ....................140
7.5.8 MSC_IF - Interrupt Flag Register ....................141
7.5.9 MSC_IFS - Interrupt Flag Set Register ..................142
7.5.10 MSC_IFC - Interrupt Flag Clear Register .................143
7.5.11 MSC_IEN - Interrupt Enable Register ..................144
7.5.12 MSC_LOCK - Configuration Lock Register ................145
7.5.13 MSC_CACHECMD - Flash Cache Command Register ............146
7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter ............146
7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter ..........147
7.5.16 MSC_MASSLOCK - Mass Erase Lock Register ..............148
7.5.17 MSC_STARTUP - Startup Control ...................149
7.5.18 MSC_CMD - Command Register ...................150
7.5.19 MSC_BOOTLOADERCTRL - Bootloader Read and Write Enable, Write Once Register . 150
7.5.20 MSC_AAPUNLOCKCMD - Software Unlock AAP Command Register .......151
7.5.21 MSC_CACHECONFIG0 - Cache Configuration Register 0 ...........152
8. LDMA - Linked DMA Controller........................153
8.1 Introduction..............................153
8.1.1 Features ............................154
8.2 Block Diagram.............................155
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8.3 Functional Description ..........................156
8.3.1 Channel Descriptor .........................156
8.3.2 Channel Configuration ........................161
8.3.3 Channel Select Configuration .....................161
8.3.4 Starting a Transfer .........................161
8.3.5 Managing Transfer Errors .......................162
8.3.6 Arbitration ............................162
8.3.7 Channel Descriptor Data Structure ....................165
8.3.8 Interaction With the EMU .......................167
8.3.9 Interrupts ............................168
8.3.10 Debugging ...........................168
8.4 Examples ..............................168
8.4.1 Single Direct Register DMA Transfer ...................168
8.4.2 Descriptor Linked List ........................169
8.4.3 Single Descriptor Looped Transfer ....................171
8.4.4 Descriptor List With Looping ......................172
8.4.5 Simple Inter-Channel Synchronization...................173
8.4.6 2D Copy.............................175
8.4.7 Ping-Pong ............................177
8.4.8 Scatter-Gather ..........................178
8.5 Register Map .............................179
8.6 Register Description ...........................180
8.6.1 LDMA_CTRL - DMA Control Register ..................180
8.6.2 LDMA_STATUS - DMA Status Register ..................181
8.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW) .....182
8.6.4 LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW) ........182
8.6.5 LDMA_CHBUSY - DMA Channel Busy Register ...............183
8.6.6 LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW) .....183
8.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register ............184
8.6.8 LDMA_SWREQ - DMA Channel Software Transfer Request Register ........184
8.6.9 LDMA_REQDIS - DMA Channel Request Disable Register ...........185
8.6.10 LDMA_REQPEND - DMA Channel Requests Pending Register .........185
8.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register ............186
8.6.12 LDMA_REQCLEAR - DMA Channel Request Clear Register ..........186
8.6.13 LDMA_IF - Interrupt Flag Register ...................187
8.6.14 LDMA_IFS - Interrupt Flag Set Register .................187
8.6.15 LDMA_IFC - Interrupt Flag Clear Register ................188
8.6.16 LDMA_IEN - Interrupt Enable Register .................188
8.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register .......189
8.6.18 LDMA_CHx_CFG - Channel Configuration Register .............192
8.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register ............193
8.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register .........194
8.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register ......197
8.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register .....197
8.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register ......198
9. RMU - Reset Management Unit ........................199
9.1 Introduction..............................199
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9.2 Features...............................199
9.3 Functional Description ..........................200
9.3.1 Reset Levels ...........................201
9.3.2 RMU_RSTCAUSE Register ......................202
9.3.3 Power-On Reset (POR) .......................203
9.3.4 Brown-Out Detector (BOD) ......................203
9.3.5 RESETn Pin Reset .........................204
9.3.6 Watchdog Reset ..........................204
9.3.7 Lockup Reset ...........................204
9.3.8 System Reset Request ........................204
9.3.9 Reset State ...........................204
9.3.10 Register Reset Signals .......................204
9.4 Register Map .............................206
9.5 Register Description ...........................207
9.5.1 RMU_CTRL - Control Register .....................207
9.5.2 RMU_RSTCAUSE - Reset Cause Register ................209
9.5.3 RMU_CMD - Command Register ....................210
9.5.4 RMU_RST - Reset Control Register ...................210
9.5.5 RMU_LOCK - Configuration Lock Register .................211
10. EMU - Energy Management Unit .......................212
10.1 Introduction .............................212
10.2 Features ..............................213
10.3 Functional Description .........................214
10.3.1 Energy Modes ..........................215
10.3.2 Entering Low Energy Modes .....................219
10.3.3 Exiting a Low Energy Mode .....................221
10.3.4 Power Configurations ........................222
10.3.5 DC-to-DC Interface ........................226
10.3.6 Analog Peripheral Power Selection ...................228
10.3.7 Digital LDO Power Selection .....................229
10.3.8 IOVDD Connection.........................229
10.3.9 Voltage Scaling ..........................230
10.3.10 EM23 Peripheral Retention Disable...................232
10.3.11 Brown Out Detector (BOD)......................232
10.3.12 Voltage Monitor (VMON) ......................233
10.3.13 Powering Off SRAM Blocks .....................234
10.3.14 Temperature Sensor ........................234
10.3.15 Registers latched in EM4 ......................235
10.3.16 Register Resets .........................235
10.4 Register Map.............................236
10.5 Register Description ..........................238
10.5.1 EMU_CTRL - Control Register ....................238
10.5.2 EMU_STATUS - Status Register ....................240
10.5.3 EMU_LOCK - Configuration Lock Register ................242
10.5.4 EMU_RAM0CTRL - Memory Control Register ...............242
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10.5.5 EMU_CMD - Command Register ...................243
10.5.6 EMU_EM4CTRL - EM4 Control Register .................244
10.5.7 EMU_TEMPLIMITS - Temperature Limits for Interrupt Generation ........245
10.5.8 EMU_TEMP - Value of Last Temperature Measurement ............245
10.5.9 EMU_IF - Interrupt Flag Register ...................246
10.5.10 EMU_IFS - Interrupt Flag Set Register .................248
10.5.11 EMU_IFC - Interrupt Flag Clear Register ................250
10.5.12 EMU_IEN - Interrupt Enable Register .................252
10.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register ...........254
10.5.14 EMU_PWRCTRL - Power Control Register ................255
10.5.15 EMU_DCDCCTRL - DCDC Control ..................256
10.5.16 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register ........257
10.5.17 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register
................................259
10.5.18 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register . 260
10.5.19 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register ...261
10.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register ..........262
10.5.21 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register .........263
10.5.22 EMU_DCDCLPCTRL - DCDC Low Power Control Register ..........264
10.5.23 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control ....265
10.5.24 EMU_DCDCSYNC - DCDC Read Status Register .............265
10.5.25 EMU_VMONAVDDCTRL - VMON AVDD Channel Control ..........266
10.5.26 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control ......267
10.5.27 EMU_VMONDVDDCTRL - VMON DVDD Channel Control ..........268
10.5.28 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control ...........269
10.5.29 EMU_RAM1CTRL - Memory Control Register ...............270
10.5.30 EMU_RAM2CTRL - Memory Control Register ...............271
10.5.31 EMU_DCDCLPEM01CFG - Configuration Bits for Low Power Mode to Be Applied During
EM01, This Field is Only Relevant If LP Mode is Used in EM01 ...........272
10.5.32 EMU_EM23PERNORETAINCMD - Clears Corresponding Bits in EM23PERNORETAINSTA-
TUS Unlocking Access to Peripheral ....................273
10.5.33 EMU_EM23PERNORETAINSTATUS - Status Indicating If Peripherals Were Powered Down
in EM23, Subsequently Locking Access to It .................275
10.5.34 EMU_EM23PERNORETAINCTRL - When Set Corresponding Peripherals May Get Powered
Down in EM23 ...........................277
11. CMU - Clock Management Unit .......................279
11.1 Introduction .............................279
11.2 Features ..............................279
11.3 Functional Description..........................280
11.3.1 System Clocks ..........................281
11.3.2 Oscillators............................284
11.3.3 Configuration for Operating Frequencies .................302
11.3.4 Energy Modes ..........................303
11.3.5 Clock Output on a Pin ........................304
11.3.6 Clock Input From a Pin .......................304
11.3.7 Clock Output on PRS ........................304
11.3.8 Error Handling ..........................304
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11.3.9 Interrupts ............................304
11.3.10 Wake-up ............................305
11.3.11 Protection ...........................305
11.4 Register Map .............................306
11.5 Register Description ..........................308
11.5.1 CMU_CTRL - CMU Control Register ..................308
11.5.2 CMU_HFRCOCTRL - HFRCO Control Register ..............310
11.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register ...........312
11.5.4 CMU_LFRCOCTRL - LFRCO Control Register ...............313
11.5.5 CMU_HFXOCTRL - HFXO Control Register ................315
11.5.6 CMU_HFXOSTARTUPCTRL - HFXO Startup Control .............317
11.5.7 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State Control .........318
11.5.8 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control ............319
11.5.9 CMU_LFXOCTRL - LFXO Control Register ................322
11.5.10 CMU_CALCTRL - Calibration Control Register ..............324
11.5.11 CMU_CALCNT - Calibration Counter Register ...............326
11.5.12 CMU_OSCENCMD - Oscillator Enable/Disable Command Register .......327
11.5.13 CMU_CMD - Command Register ...................328
11.5.14 CMU_DBGCLKSEL - Debug Trace Clock Select ..............329
11.5.15 CMU_HFCLKSEL - High Frequency Clock Select Command Register ......329
11.5.16 CMU_LFACLKSEL - Low Frequency A Clock Select Register .........330
11.5.17 CMU_LFBCLKSEL - Low Frequency B Clock Select Register .........330
11.5.18 CMU_LFECLKSEL - Low Frequency E Clock Select Register .........331
11.5.19 CMU_STATUS - Status Register ...................332
11.5.20 CMU_HFCLKSTATUS - HFCLK Status Register ..............334
11.5.21 CMU_HFXOTRIMSTATUS - HFXO Trim Status ..............335
11.5.22 CMU_IF - Interrupt Flag Register ...................336
11.5.23 CMU_IFS - Interrupt Flag Set Register .................338
11.5.24 CMU_IFC - Interrupt Flag Clear Register ................340
11.5.25 CMU_IEN - Interrupt Enable Register .................342
11.5.26 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0 ......344
11.5.27 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 ....345
11.5.28 CMU_HFRADIOALTCLKEN0 - High Frequency Alternate Radio Peripheral Clock Enable
Register 0 .............................346
11.5.29 CMU_LFACLKEN0 - Low Frequency a Clock Enable Register 0 (Async Reg) ....346
11.5.30 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) ....347
11.5.31 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg) ....347
11.5.32 CMU_HFPRESC - High Frequency Clock Prescaler Register .........348
11.5.33 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register .....349
11.5.34 CMU_HFPERPRESC - High Frequency Peripheral Clock Prescaler Register ....349
11.5.35 CMU_HFRADIOPRESC - High Frequency Radio Peripheral Clock Prescaler Register . 350
11.5.36 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register .....350
11.5.37 CMU_LFAPRESC0 - Low Frequency a Prescaler Register 0 (Async Reg) .....351
11.5.38 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) .....352
11.5.39 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg) .....353
11.5.40 CMU_HFRADIOALTPRESC - High Frequency Alternate Radio Peripheral Clock Prescaler
Register .............................353
11.5.41 CMU_SYNCBUSY - Synchronization Busy Register .............354
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11.5.42 CMU_FREEZE - Freeze Register ...................357
11.5.43 CMU_PCNTCTRL - PCNT Control Register ...............358
11.5.44 CMU_ADCCTRL - ADC Control Register ................359
11.5.45 CMU_ROUTEPEN - I/O Routing Pin Enable Register ............360
11.5.46 CMU_ROUTELOC0 - I/O Routing Location Register ............361
11.5.47 CMU_ROUTELOC1 - I/O Routing Location Register ............362
11.5.48 CMU_LOCK - Configuration Lock Register ................363
12. SMU - Security Management Unit ......................364
12.1 Introduction .............................364
12.2 Features ..............................364
12.3 Functional Description .........................365
12.3.1 PPU - Peripheral Protection Unit ....................365
12.3.2 Programming Model ........................366
12.4 Register Map.............................367
12.5 Register Description ..........................368
12.5.1 SMU_IF - Interrupt Flag Register ...................368
12.5.2 SMU_IFS - Interrupt Flag Set Register ..................368
12.5.3 SMU_IFC - Interrupt Flag Clear Register .................369
12.5.4 SMU_IEN - Interrupt Enable Register ..................369
12.5.5 SMU_PPUCTRL - PPU Control Register .................370
12.5.6 SMU_PPUPATD0 - PPU Privilege Access Type Descriptor 0 ..........371
12.5.7 SMU_PPUPATD1 - PPU Privilege Access Type Descriptor 1 ..........373
12.5.8 SMU_PPUFS - PPU Fault Status ...................374
13. RTCC - Real Time Counter and Calendar ...................376
13.1 Introduction .............................376
13.2 Features ..............................376
13.3 Functional Description .........................377
13.3.1 Counter ............................378
13.3.2 Capture/Compare Channels .....................382
13.3.3 Interrupts and PRS Output ......................384
13.3.4 Energy Mode Availability .......................385
13.3.5 Register Lock ..........................385
13.3.6 Oscillator Failure Detection ......................385
13.3.7 Retention Registers ........................385
13.3.8 Debug Session ..........................385
13.4 Register Map.............................386
13.5 Register Description ..........................387
13.5.1 RTCC_CTRL - Control Register (Async Reg) ...............387
13.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg) ..........389
13.5.3 RTCC_CNT - Counter Value Register (Async Reg) .............389
13.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register ......390
13.5.5 RTCC_TIME - Time of Day Register (Async Reg) ..............391
13.5.6 RTCC_DATE - Date Register (Async Reg) ................392
13.5.7 RTCC_IF - RTCC Interrupt Flags ...................393
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