Silicon Laboratories I2C User manual

Rev. 1.2 8/12 Copyright © 2012 by Silicon Laboratories Si5338
Si5338
I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT
QUAD CLOCK GENERATOR
Features
Applications
Description
The Si5338 is a high-performance, low-jitter clock generator capable of
synthesizing any frequency on each of the device's four output drivers. This timing
IC is capable of replacing up to four different frequency crystal oscillators or
operating as a frequency translator. Using its patented MultiSynth™ technology,
the Si5338 allows generation of four independent clocks with 0 ppm precision.
Each output clock is independently configurable to support various signal formats
and supply voltages. The Si5338 provides low-jitter frequency synthesis in a
space-saving 4 x 4 mm QFN package. The device is programmable via an I2C/
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
3.3 V core supply. I2C device programming is made easy with the ClockBuilder™
Desktop software available at www.silabs.com/ClockBuilder.
Low power MultiSynth™ technology
enables independent, any-frequency
synthesis on four differential output
drivers
Highly-configurable output drivers with
up to four differential outputs, eight
single-ended clock outputs, or a
combination of both
Low phase jitter of 0.7 ps RMS typ
High precision synthesis allows true
zero ppm frequency accuracy on all
outputs
Flexible input reference:
External crystal: 8 to 30 MHz
CMOS input: 5 to 200 MHz
SSTL/HSTL input: 5 to 350 MHz
Differential input: 5 to 710 MHz
Independently configurable outputs
support any frequency or format:
LVPECL/LVDS: 0.16 to 710 MHz
HCSL: 0.16 to 250 MHz
CMOS: 0.16 to 200 MHz
SSTL/HSTL: 0.16 to 350 MHz
Independent output voltage per driver:
1.5, 1.8, 2.5, or 3.3 V
Single supply core with excellent
PSRR: 1.8, 2.5, 3.3 V
Independent frequency increment/
decrement feature enables
glitchless frequency adjustments in
1 ppm steps
Independent phase adjustment on
each of the output drivers with an
accuracy of <20 ps steps
Highly configurable spread
spectrum (SSC) on any output:
Any frequency from 5 to 350 MHz
Any spread from 0.5 to 5.0%
Any modulation rate from 33 to
63 kHz
External feedback mode allows
zero-delay mode
Loss of lock and loss of signal
alarms
I2C/SMBus compatible interface
Easy to use programming software
Small size: 4 x 4 mm, 24-QFN
Low power: 45 mA core supply typ
Wide temperature range: –40 to
+85 °C
Ethernet switch/router
PCI Express 2.0/3.0
Broadcast video/audio timing
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
Ordering Information:
See page 41.
Pin Assignments
IN1
CLK2B
CLK2A
VDDO2
VDDO1
CLK1B
CLK1A
VDD VDD
SCL
CLK3A CLK3B
INTR
SDA VDDO0
CLK0B
CLK0A
RSVD_GND
VDDO3
GND
GND
Pad
5
4
3
2
1
613
10
987
IN2
IN3
IN4
IN5
IN6
Top View
11 12
15
14
16
17
18
192021
222324

Si5338
2 Rev. 1.2
Functional Block Diagram
Phase
Frequency
Detector
Loop
Filter VCO
CLK0A
÷P2
VDDO1
VDDO2
VDDO3
VDDO0
MultiSynth
÷M0
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷P1
IN3
IN2
IN1
÷R1
MultiSynth
÷M1
MultiSynth
÷M2
MultiSynth
÷M3
IN6
IN4
IN5
Osc
MultiSynth
÷N
Control NVM
(OTP)
÷R0
÷R2
÷R3
Synthesis
Stage 1
(PLL)
Synthesis
Stage 2 Output
Stage
P1DIV_IN
Control & Memory
SCL
SDA
INTR
VDD
ref
fb
RAM
P2DIV_IN
noclk
noclk

Si5338
Rev. 1.2 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.5. Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.8. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.9. Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.10. Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6. Si5338 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
9. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
10. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11.1. Si5338 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
12. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
13. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13.1. Description: Spread Modulation Rate and Nominal Frequency Error . . . . . . . . . . .42
13.2. Affected Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13.3. Impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13.4. Workarounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13.5. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Si5338
4 Rev. 1.2
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA–40 25 85 °C
Core Supply Voltage VDD
2.97 3.3 3.63 V
2.25 2.5 2.75 V
1.71 1.8 1.98 V
Output Buffer Supply
Voltage VDDOn 1.4 — 3.63 V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. Absolute Maximum Ratings1
Parameter Symbol Test Condition Value Unit
DC Supply Voltage VDD –0.5 to 3.8 V
Storage Temperature Range TSTG –55 to 150 °C
ESD Tolerance HBM
(100 pF, 1.5 k)2.5 kV
ESD Tolerance CDM 550 V
ESD Tolerance MM 175 V
Latch-up Tolerance JESD78 Compliant
Junction Temperature TJ150 °C
Peak Soldering Reflow Temperature2260 °C
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. Refer to JEDEC J-STD-020 standard for more information.

Si5338
Rev. 1.2 5
Table 3. DC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Core Supply Current IDD 100 MHzonall outputs,
25 MHz refclk —4560mA
Core Supply Current
(Buffer Mode) IDDB 50 MHz refclk — 12 — mA
Output Buffer Supply Current IDDOx
LVPECL, 710 MHz — — 30 mA
LVDS, 710 MHz — — 8 mA
HCSL, 250 MHz
2pFload ——20mA
CML, 350 MHz — 12 — mA
SSTL, 350 MHz — — 19 mA
CMOS, 50 MHz
15 pF load1—6 9mA
CMOS, 200 MHz1,2
3.3 V VDD0 —1318mA
CMOS, 200 MHz1,2
2.5 V —1014mA
CMOS, 200 MHz1,2
1.8 V —710mA
HSTL, 350 MHz — — 19 mA
Notes:
1. Single CMOS driver active.
2. Measured into a 5” 50 trace with 2 pF load.
Table 4. Thermal Characteristics
Parameter Symbol Test Condition Value Unit
Thermal Resistance
Junction to Ambient JA Still Air 37 °C/W
Thermal Resistance
Junction to Case JC Still Air 25 °C/W

Si5338
6 Rev. 1.2
Table 5. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
PLL Acquisition Time tACQ ——25 ms
PLL Tracking Range fTRACK 5000 20000 — ppm
PLL Loop Bandwidth fBW —1.6— MHz
MultiSynth Frequency
Synthesis Resolution fRES Output frequency < Fvco/8 0 0 1 ppb
CLKIN Loss of Signal Detect
Time tLOS —2.6 5 µs
CLKIN Loss of Signal Release
Time tLOSRLS 0.01 0.2 1 µs
PLL Loss of Lock Detect Time tLOL —510ms
POR to Output Clock Valid
(Pre-programmed Devices) tRDY —— 2 ms
Input-to-Output Propagation
Delay tPROP Buffer Mode
(PLL Bypass) —2.5 4 ns
Output-Output Skew tDSKEW Rn divider = 11——100 ps
POR to I2C Ready ——15 ms
Programmable Initial
Phase Offset POFFSET –45 — +45 ns
Phase Increment/Decrement
Accuracy PSTEP ——20 ps
Phase Increment/Decrement
Range PRANGE –45 — +45 ns
MultiSynth range for phase
increment/decrement fPRANGE 5—Fvco/8
2MHz
Phase Increment/Decrement
Update Time PUPDATE Pin control2,3
MultiSynth output >18 MHz 667 — — ns
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase
Offset" on page 26.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.

Si5338
Rev. 1.2 7
Phase Increment/Decrement
Update Time PUPDATE Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—1012Periods
Frequency Increment/
Decrement Step Size fSTEP R divider not used 1 — See
Note 2ppm
MultiSynth range for frequency
increment/decrement fRANGE R divider not used 5 — Fvco/8 MHz
Frequency Increment/
Decrement Update Time fUPDATE Pin control2,3
MultiSynth output >18 MHz ——667 ns
Frequency Increment/
Decrement Update Time fUPDATE Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—1012Periods
Spread Spectrum PP
Frequency Deviation SSDEV MultiSynth Output < ~Fvco/8 0.1 — 5.04%
Spread Spectrum Modulation
Rate SSDEV MultiSynthOutput<~Fvco/8 30 — 635kHz
Table 5. Performance Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase
Offset" on page 26.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.

Si5338
8 Rev. 1.2
Table 6. Input and Output Clock Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)1
Frequency fIN 5—710MHz
Differential Voltage
Swing VPP 710 MHz input 0.4 — 2.4 VPP
Rise/Fall Time2tR/tF20%–80% — — 1.0 ns
Duty Cycle DC < 1 ns tr/tf 40 — 60 %
Duty Cycle DC
(PLL bypass)3< 1 ns tr/tf 45 — 55 %
Input Impedance1RIN 10 — — k
Input Capacitance CIN —3.5—pF
Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)
Frequency fIN CMOS 5 — 200 MHz
Input Voltage VI–0.1 — 3.73 V
Input Voltage Swing 200 MHz 0.8 — VDD+10% Vpp
Rise/Fall Time4tR/tF10%–90% — — 4 ns
Rise/Fall Time4tR/tF20%–80% — — 2.3 ns
Duty Cycle5DC < 4 ns tr/tf 40 — 60 %
Input Capacitance CIN —2.0—pF
Output Clocks (Differential)
Frequency6fOUT LVPECL, LVDS,
CML 0.16 — 350 MHz
367 — 473.33 MHz
550 — 710 MHz
HCSL 0.16 — 250 MHz
Notes:
1. Use an external 100 resistor to provide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 18.
7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at the receiver.
8. Includes effect of internal series 22 resistor.

Si5338
Rev. 1.2 9
LVPECL Output
Voltage VOC common mode — VDDO– 1.45 V —V
VSEPP peak-to-peak sin-
gle-ended swing 0.55 0.8 0.96 VPP
LVDS Output Voltage
(2.5/3.3 V) VOC common mode 1.125 1.2 1.275 V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.25 0.35 0.45 VPP
LVDS Output
Voltage (1.8 V) VOC Common Mode 0.8 0.875 0.95 V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.25 0.35 0.45 VPP
HCSL Output Voltage VOC Common Mode 0.35 0.375 0.400 V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.575 0.725 0.85 VPP
CML Output Voltage VOC Common Mode — See Note 7—V
VSEPP Peak-to-Peak
Single-Ended
Swing
0.67 0.860 1.07 VPP
Rise/Fall Time tR/tF20%–80% — — 450 ps
Duty Cycle5DC 45 — 55 %
Output Clocks (Single-Ended)
Frequency fOUT CMOS 0.16 — 200 MHz
SSTL, HSTL 0.16 — 350 MHz
CMOS 20%–80%
Rise/Fall Time tR/tF2 pF load — 0.45 0.85 ns
CMOS 20%–80%
Rise/Fall Time tR/tF15 pF load — — 2.0 ns
Table 6. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
Notes:
1. Use an external 100 resistor to provide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 18.
7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at the receiver.
8. Includes effect of internal series 22 resistor.

Si5338
10 Rev. 1.2
CMOS Output
Resistance —50—
SSTL Output
Resistance —50—
HSTL Output
Resistance —50—
CMOS Output
Voltage8VOH 4 mA load VDDO – 0.3 — V
VOL 4 mA load — 0.3 V
SSTL Output Voltage VOH SSTL-3
VDDOx = 2.97 to
3.63 V
0.45xVDDO+0.41 — — V
VOL — — 0.45xVDDO
–0.41 V
VOH SSTL-2
VDDOx = 2.25to
2.75 V
0.5xVDDO+0.41 — — V
VOL — — 0.5xVDDO–
0.41 V
VOH SSTL-18
VDDOx = 1.71 to
1.98 V
0.5xVDDO+0.34 — V
VOL — — 0.5xVDDO–
0.34 V
HSTL Output Voltage VOH VDDO = 1.4 to
1.6 V 0.5xVDDO+0.3 — — V
VOL — — 0.5xVDDO –
0.3 V
Duty Cycle5DC 45 — 55 %
Table 6. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
Notes:
1. Use an external 100 resistor to provide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 18.
7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at the receiver.
8. Includes effect of internal series 22 resistor.

Si5338
Rev. 1.2 11
Table 7. Control Pins
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Condition Min Typ Max Unit
Input Control Pins (IN3, IN4)
Input Voltage Low VIL –0.1 — 0.3 x VDD V
Input Voltage High VIH 0.7 x VDD —3.73V
Input Capacitance CIN —— 4pF
Input Resistance RIN —20—k
Output Control Pins (INTR)
Output Voltage Low VOL ISINK =3mA 0 — 0.4 V
Rise/Fall Time 20–80% tR/tFCL< 10 pf, pull up 1k— — 10 ns
Table 8. Crystal Specifications for 8 to 11 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 8—11MHz
Load Capacitance (on-chip differential) cL(supported)* 11 12 13 pF
cL(recommended) 17 18 19 pF
Crystal Output Capacitance cO—— 6pF
Equivalent Series Resistance rESR ——300
Crystal Max Drive Level dL100 — — µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to
accommodate a 12 pF crystal CL.
Table 9. Crystal Specifications for 11 to 19 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 11 — 19 MHz
Load Capacitance (on-chip differential) cL(supported)* 11 12 13 pF
cL(recommended) 17 18 19 pF
Crystal Output Capacitance cO—— 5pF
Equivalent Series Resistance rESR ——200
Crystal Max Drive Level dL100 — — µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to
accommodate a 12 pF crystal CL.

Si5338
12 Rev. 1.2
Table 10. Crystal Specifications for 19 to 26 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 19 26 MHz
Load Capacitance (on-chip differential) cL(supported)* 11 12 13 pF
cL(recommended) 17 18 19 pF
Crystal Output Capacitance cO5pF
Equivalent Series Resistance rESR 100 
Crystal Max Drive Level dL100 µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to
accommodate a 12 pF crystal CL.
Table 11. Crystal Specifications for 26 to 30 MHz
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 26 30 MHz
Load Capacitance (on-chip differential) cL(supported)* 11 12 13 pF
cL(recommended) 17 18 19 pF
Crystal Output Capacitance cO5pF
Equivalent Series Resistance rESR 75 
Crystal Max Drive Level dL100 µW
*Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to
accommodate a 12 pF crystal CL.

Si5338
Rev. 1.2 13
Table 12. Jitter Specifications1,2,3
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
GbE Random Jitter
(12kHz–20MHz)
4JGbE CLKIN = 25 MHz
All CLKn at 125 MHz5— 0.7 1 ps RMS
GbE Random Jitter
(1.875–20 MHz) RJGbE CLKIN = 25 MHz
All CLKn at 125 MHz5— 0.38 0.79 ps RMS
OC-12 Random Jitter
(12 kHz–5 MHz) JOC12 CLKIN = 19.44 MHz
All CLKn at
155.52 MHz5— 0.7 1 ps RMS
PCI Express 1.1 Common
Clocked Total Jitter6— 20.1 33.6 ps pk-pk
PCI Express 2.1 Common
Clocked
RMS Jitter6, 10 kHz to
1.5 MHz — 0.15 1.47 ps RMS
RMSJitter6,1.5 MHzto
50 MHz — 0.58 0.75 ps RMS
PCI Express 3.0 Common
Clocked RMS Jitter6— 0.15 0.45 ps RMS
Period Jitter JPER N = 10,000 cycles7— 10 30 ps pk-pk
Cycle-Cycle Jitter JCC
N = 10,000 cycles
Output MultiSynth
operated in integer or
fractional mode7
— 9 29 ps pk8
Random Jitter
(12kHz–20MHz) RJOutput and feedback
MultiSynth in integer or
fractional mode7— 0.7 1.5 ps RMS
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. DJfor PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver. 1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.

Si5338
14 Rev. 1.2
Deterministic Jitter DJ
Output MultiSynth
operated in fractional
mode7—315pspk-pk
Output MultiSynth
operated in integer
mode7—210pspk-pk
Total Jitter
(12kHz–20MHz) TJ=D
J+14xRJ
(See Note 9)
Output MultiSynth
operated in fractional
mode7— 13 36 ps pk-pk
Output MultiSynth
operated in integer
mode7— 12 20 ps pk-pk
Table 13. itter Specifications, Clock Buffer Mode (PLL Bypass)*
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Additive Phase Jitter
(12kHz–20MHz) tRPHASE
0.7 Vpk-pkdifferentialinput
clock at 622.08 MHz with
70 ps rise/fall time — 0.165 — ps RMS
Additive Phase Jitter
(50kHz–80MHz) tRPHASEWB
0.7 Vpk-pkdifferentialinput
clock at 622.08 MHz with
70 ps rise/fall time — 0.225 — ps RMS
*Note: All outputs are in Clock Buffer mode (PLL Bypass).
Table 12. Jitter Specifications1,2,3 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. DJfor PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver. 1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.

Si5338
Rev. 1.2 15
Table 14. Typical Phase Noise Performance
Offset Frequency 25 MHz XTAL
to 156.25 MHz 27 MHz Ref In to 148.3517 MHz 19.44 MHz Ref In to 155.52 MHz Units
100 Hz –90 –87 –110 dBc/Hz
1 kHz –120 –117 –116 dBc/Hz
10 kHz –126 –123 –123 dBc/Hz
100 kHz –132 –130 –128 dBc/Hz
1 MHz –132 –132 –128 dBc/Hz
10 MHz –145 –145 –145 dBc/Hz
Table 15. I2C Specifications (SCL,SDA)1
Parameter Symbol Test Condition Standard Mode Fast Mode Unit
Min Max Min Max
LOW Level
Input Voltage VILI2C –0.5 0.3 x VDDI2
C–0.5 0.3 x VDDI2C2V
HIGH Level
Input Voltage VIHI2C 0.7 x VDDI2
C
3.63 0.7 x VDDI2C23.63 V
Hysteresis of
Schmitt Trigger
Inputs
VHYS N/A N/A 0.1 — V
LOW Level Out-
put Voltage
(open drain or
open collector)
at 3 mA Sink
Current
VOLI2C2V
DDI2C2= 2.5/3.3 V 0 0.4 0 0.4 V
VDDI2C2= 1.8 V N/A N/A 0 0.2 x VDDI2C V
Input Current II2C –10 10 –10 10 µA
Capacitance for
each I/O Pin CI2C V
IN = –0.1 to VDDI2C —4 — 4pF
I2C Bus Time-
out — Timeout Enabled 25 35 25 35 ms
Data Rate Standard Mode 100 400 kbps
Notes:
1. Refer to NXP’s UM10204 I2C-bus specification and user manual, Revision 03, for further details:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. I2C pullup voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I2C bus voltage is less
than 2.5 V to maintain compatibility with the I2C bus standard.

Si5338
16 Rev. 1.2
2. Typical Application Circuits
Si5338C
16 15 1120247
VDDOA VDDOB
VDDOC
VDDOD
VDD VDD
23
GND GND
PAD23 PAD
+3.3 V
0.1 uF Power Supply
Decoupling Capacitors
(1 per VDD or VDDOx pin)
1
2
27 MHz
XTAL IN1
IN2
Optional XTAL for
Free-run Applications
I2C Bus
I2C Address = 111 0000 or 111 0001
+3.3 V
1k1k1k
8INTR
19
12 SDA
SCL
4I2C_LSB
3IN3
5
6
IN5
IN6
Single-ended or
Differential Inputs
for Synchronous
Applications 100
27 MHz
74.25 MHz
74.25/1.001 MHz
148.5 MHz
148.5/1.001 MHz
SD/HD/3G-SDI
Video/Audio
Format Converter
10
9
CLK3A
CLK3B
14
CLK2A 13
CLK2B
18
CLK1A 17
CLK1B
CLK0A
CLK0B
22
21
SDI
Serializer
Video
Processor
SD/HD/3G
SDI IN SD/HD/3G
SDI OUT
100
x
IN3
x
x
SDI
Deserializer
x
Audio
Processor
Audio Out
Si5338C
16 15 1120247
VDDOA VDDOB
VDDOC
VDDOD
VDD VDD
23
GND GND
PAD23 PAD
+3.3 V
0.1 uF Power Supply
Decoupling Capacitors
(1 per VDD or VDDOx pin)
1
2
25 MHz
XTAL IN1
IN2
I2C Bus
I2C Address = 111 0000 or 111 0001
+3.3V
1k1k1k
8INTR
19
12 SDA
SCL
4I2C_LSB
3IN3
5
6
IN5
IN6
10
9
14
13
18
17
22
21
x
Storage Area
Network
37.5/75/120/150 MHz
100 MHz
x
Ethernet
Fiber
Channel
PCIe
Switch
Network
Processor
SAS2
4/8 Port
Controller
disk
disk
disk
disk
SAS2
4/8 Port
Controller
66 MHz
x
x
106.25 MHz
74.25 MHz, 74.25/1.001 MHz
148.5 MHz, 148.5/1.001 MHz
24.576 MHz / 6.144 MHz
100 MHz
CLK3A
CLK3B
CLK2A
CLK2B
CLK1A
CLK1B
CLK0A
CLK0B

Si5338
Rev. 1.2 17
3. Functional Description
Figure 1. Si5338 Block Diagram
3.1. Overview
The Si5338 is a high-performance, low-jitter clock
generator capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz
and select frequencies up to 710 MHz. The device
supports free-run operation using an external crystal, or
it can lock to an external clock for generating
synchronous clocks. The output drivers support four
differential clocks or eight single-ended clocks or a
combination of both. The output drivers are configurable
to support common signal formats, such as LVPECL,
LVDS, HCSL, CMOS, HSTL, and SSTL. Separate
output supply pins allow supply voltages of 3.3, 2.5, 1.8,
and 1.5 V to support the multi-format output driver. The
core voltage supply accepts 3.3, 2.5, or 1.8 V and is
independent from the output supplies.
Using its two-stage synthesis architecture and patented
high-resolution MultiSynth technology, the Si5338 can
generate four independent frequencies from a single
input frequency. In addition to clock generation, the
inputs can bypass the synthesis stage enabling the
Si5338 to be used as a high-performance clock buffer or
a combination of a buffer and generator.
For applications that need fine frequency adjustments,
such as clock margining, each of the synthesized
frequencies can be incremented or decremented in
user-defined steps as low as 1 ppm per step.
Output-to-output phase delays are also adjustable in
user-defined steps with an error of <20 ps to
compensate for PCB trace delays or for fine tuning of
setup and hold margins.
A zero-delay mode is also available to help minimize
input-to-output delay. Spread spectrum is available on
each of the clock outputs for EMI-sensitive applications,
such as PCI Express.
Configuration and control of the Si5338 is mainly
handled through the I2C/SMBus interface. Some
features, such as output enable and frequency or phase
adjustments, can optionally be pin controlled. The
device has a maskable interrupt pin that can be
monitored for loss of lock or loss of input signal
conditions.
The device also provides the option of storing a user-
definable clock configuration in its non-volatile memory
(NVM), which becomes the default clock configuration
at power-up.
3.1.1. ClockBuilder™ Desktop Software
To simplify device configuration, Silicon Labs provides
ClockBuilder Desktop software, which can operate
stand alone or in conjunction with the Si5338 EVB.
When the software is connected to an Si5338 EVB it will
control both the supply voltages to the Si5338 as well as
the entire clock path within the Si5338. Clockbuilder
Desktop can also measure the current delivered by the
EVB regulators to each supply voltage of the Si5338. A
Si5338 configuration can be written to a text file to be
used by any system to configure the Si5338 via I2C.
ClockBuilder Desktop can be downloaded from
www.silabs.com/ClockBuilder and runs on Windows XP,
Windows Vista, and Windows 7.
Phase
Frequency
Detector
Loop
Filter VCO
CLK0A
÷P2
VDDO1
VDDO2
VDDO3
VDDO0
MultiSynth
÷M0
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷P1
IN3
IN2
IN1
÷R1
MultiSynth
÷M1
MultiSynth
÷M2
MultiSynth
÷M3
IN6
IN4
IN5
Osc
MultiSynth
÷N
Control NVM
(OTP)
÷R0
÷R2
÷R3
Input
Stage Synthesis
Stage 1
(PLL)
Synthesis
Stage 2 Output
Stage
CLKIN
Control & Memory
SCL
SDA
INTR
VDD
ref
fb
RAM
FDBK

Si5338
18 Rev. 1.2
3.2. Input Stage
The input stage supports four inputs. Two are used as
the clock inputs to the synthesis stage, and the other
two are used as feedback inputs for zero delay or
external feedback mode. In cases where external
feedback is not required, all four inputs are available to
the synthesis stage. The reference selector selects one
of the inputs as the reference to the synthesis stage.
The input configuration is selectable through the IC
interface. The input MUXes are set automatically in
ClockBuilder Desktop (see “3.1.1. ClockBuilder™
Desktop Software”). For information on setting the input
MUXs manually, see the Si5338 Reference Manual:
Configuring the Si5338 without ClockBuilder Desktop.
Figure 2. Input Stage
IN1/IN2 and IN5/IN6 are differential inputs capable of
accepting clock rates from 5 to 710 MHz. The
differential inputs are capable of interfacing to multiple
signals, such as LVPECL, LVDS, HSCT, HCSL, and
CML. Differential signals must be ac-coupled as shown
in Figure 3. A termination resistor of 100 placed close
to the input pins is also required. Refer to Table 6 for
signal voltage limits.
Figure 3. Interfacing Differential and Single-
Ended Signals to the Si5338
IN3 and IN4 accept single-ended signals from 5 MHz to
200 MHz. The single-ended inputs are internally ac-
coupled; so, they can accept a wide variety of signals
without requiring a specific dc level. The input signal
only needs to meet a minimum voltage swing and must
not exceed a maximum VIH or a minimum VIL. Refer to
Table 6 for signal voltage limits. A typical single-ended
connection is shown in Figure 3. For additional
termination options, refer to “AN408: Termination
Options for Any-Frequency, Any-Output Clock
Generators and Clock Buffers—Si5338, Si5334,
Si5330”.
For free-run operation, the internal oscillator can
operate from a low-frequency fundamental mode crystal
(XTAL) with a resonant frequency between 8 and
30 MHz. A crystal can easily be connected to pins IN1
and IN2 without external components as shown in
Figure 4. See Tables 8–11 for crystal specifications that
are guaranteed to work with the Si5338.
Figure 4. Connecting an XTAL to the Si5338
Refer to “AN360: Crystal Selection Guide for Si533x/5x
Devices” for information on the crystal selection.
3.2.1. Loss-of-Signal (LOS) Alarm Detectors
There are two LOS detectors: LOS_CLKIN and
LOS_FDBK. These detectors are tied to the outputs of
the P1 and P2 frequency dividers, which are always
enabled. See "3.6. Status Indicators" on page 23 for
details on the alarm indicators. These alarms are used
during programming to ensure that a valid input clock is
detected. The input MUXs are set automatically in
ClockBuilder Desktop (see the Si5338 Reference
Manual to set manually).
3.3. Synthesis Stages
Next-generation timing applications require a wide
range of frequencies that are often non-integer related.
Traditional clock architectures address this by using
multiple single PLL ICs, often at the expense of BOM
complexity and power. The Si5338 uses patented
MultiSynth technology to dramatically simplify timing
architectures by integrating the frequency synthesis
capability of four Phase-Locked Loops (PLLs) in a
single device, greatly reducing size and power
requirements versus traditional solutions.
÷P2
÷P1
IN3
IN2
IN1
IN6
IN4
IN5
Osc
P1DIV_IN
To Synthesis Stage
P2DIV_IN
noclk
noclk
IN2/ IN6
IN1/ IN5
100
50
50
0.1 uF
0.1 uF
IN3 / IN4
50
Rs
IN2
IN1
XTAL Osc To synthesis stage
or output selectors

Si5338
Rev. 1.2 19
Synthesis of the output clocks is performed in two
stages, as shown in Figure 5. The first stage consists of
a high-frequency analog phase-locked loop (PLL) that
multiplies the input stage to a frequency within the
range of 2.2 to 2.84 GHz. Multiplication of the input
frequency is accomplished using a proprietary and
highly precise MultiSynth feedback divider (N), which
allows the PLL to generate any frequency within its
VCO range with much less jitter than typical fractional N
PLL.
Figure 5. Synthesis Stages
The second stage of synthesis consists of the output
MultiSynth dividers (MSx). Based on a fractional N
divider, the MultiSynth divider shown in Figure 6
switches seamlessly between the two closest integer
divider values to produce the exact output clock
frequency with 0 ppm error.
To eliminate phase error generated by this process, the
MultiSynth block calculates the relative phase difference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
This architecture allows the output of each MultiSynth to
produce any frequency from 5 to Fvco/8 MHz. To
support higher frequency operation, the MultiSynth
divider can be bypassed. In bypass mode, integer divide
ratios of 4 and 6 are supported. This allows for output
frequencies of Fvco/4 and Fvco/6 MHz, which translates
to 367–473.33 MHz and 550–710 MHz respectively.
Because each MultiSynth uses the same VCO output,
there are output frequency limitations when output
frequencies greater than Fvco/8 are desired.
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce Fvco/4 = 562.5 MHz or Fvco/6 = 375 MHz. Only
two unique frequencies above Fvco/8 can be output:
Fvco/6 and Fvco/4.
Figure 6. Silicon Labs’ MultiSynth Technology
Phase
Frequency
Detector
Loop
Filter VCO
MultiSynth
÷MS0
MultiSynth
÷MS1
MultiSynth
÷MS2
MultiSynth
÷MS3
MultiSynth
÷N
Synthesis
Stage 1
(APLL)
Synthesis
Stage 2
ref
fb
From Input Stage
To Output Stage
2.2-2.84 GHz
Fractional-N
Divider Phase Adjust
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
fVCO fOUT
MultiSynth

Si5338
20 Rev. 1.2
3.4. Output Stage
The output stage consists of output selectors, output
dividers, and programmable output drivers as shown in
Figure 7.
Figure 7. Output Stage
The output selectors select the clock source for the
output drivers. By default, each output driver is
connected to its own MultiSynth block (e.g. MS0 to
CLK0, MS1 to CLK1, etc), but other combinations are
possible by reconfiguring the device. The PLL can be
bypassed by connecting the input stage signals (osc,
ref, refdiv, fb, or fbdiv) directly to the output divider.
Bypassing an input directly to an output will not allow
phase alignment of that output to other outputs. Each of
the output drivers can also connect to the first
MultiSynth block (MS0) enabling a fan-out function. This
allows the Si5338 to act as a clock generator, a fanout
buffer, or a combination of both in the same package.
The output dividers (R0, R1, R2, R3) allow another
stage of clock division.These dividers are configurable
as divide by 1 (default), 2, 4, 8, 16, or 32. When an Rn
does not equal 1, the phase alignment function for that
output will not work.
The output drivers are configurable to support common
signal formats, such as LVPECL, LVDS, HCSL, CMOS,
HSTL, and SSTL. Separate output supply pins (VDDOn)
are provided for each output buffer.
The voltage on these supply pins can be 3.3, 2.5, 1.8, or
1.5 V as needed for the possible output formats.
Additionally, the outputs can be configured to stop high,
low, or tri-state when the PLL has lost lock. If the Si5338
is used in a zero delay mode, the output that is fed back
must be set for always on, which will override any
output disable signal.
Each of the outputs can also be enabled or disabled
through the I2C port. A single pin to enable/disable all
outputs is available in the Si5338K/L/M.
3.5. Configuring the Si5338
The Si5338 is a highly-flexible clock generator that is
entirely configurable through its I2C interface. The
device’s default configuration is stored in non-volatile
memory (NVM) as shown in Figure 8. The NVM is a
one-time programmable memory (OTP), which can
store a custom user configuration at power-up. This is a
useful feature for applications that need a clock present
at power-up (e.g., for providing a clock to a processor).
Figure 8. Si5338 Memory Configuration
During a power cycle or a power-on reset (POR), the
contents of the NVM are copied into random access
memory (RAM), which sets the device configuration that
will be used during operation. Any changes to the
device configuration after power-up are made by
reading and writing to registers in the RAM space
through the I2C interface. ClockBuilder Desktop (see
"3.1.1. ClockBuilder™ Desktop Software" on page 17)
can be used to easily configure register map files that
can be written into RAM (see “3.5.2. Creating a New
Configuration for RAM” for details). Alternatively, the
register map file can be created manually with the help
of the equations in the Si5338 Reference Manual.
Two versions of the Si5338 are available. First,
standard, non-customized Si5338 devices are available
in which the RAM can be configured in-circuit via I2C
(example part number Si5338C-A-GM). Alternatively,
standard Si5338 devices can be field-programmed
using the Si5338/56-PROG-EVB field programmer.
Second, custom factory-programmed Si5338 devices
are available that include a user-specified startup
frequency configuration (example part number
Si5338C-Axxxxx-GM). See "12. Ordering Information"
on page 41 for details.
CLK0A
VDDO1
VDDO2
VDDO3
VDDO0
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷R1
÷R0
÷R2
÷R3
Output
Stage
From Synthesis Stage
or Input Stage
Power-Up/POR
I2C
RAM
NVM
(OTP)
Default
Config