Silicon Laboratories Si8410 User manual

Rev. 1.1 8/11 Copyright © 2011 by Silicon Laboratories Si8410/20/21 / Si8422/23
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
LOW-POWER, SINGLE AND DUAL-CHANNEL
DIGITAL ISOLATORS
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering
substantial data rate, propagation delay, power, size, reliability, and external BOM
advantages when compared to legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges and
throughout device service life for ease of design and highly uniform performance.
All device versions have Schmitt trigger inputs for high noise immunity and only
require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case
propagation delays of less than 10 ns. Ordering options include a choice of
isolation ratings (up to 5 kV) and a selectable fail-safe operating mode to control
the default output state during power loss. All products are safety certified by UL,
CSA, and VDE, and products in wide-body packages support reinforced insulation
withstanding up to 5 kVRMS.
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.6–5.5 V
Up to 5000 VRMS isolation
High electromagnetic immunity
Ultra low power (typical)
5 V Operation:
< 2.6 mA/channel at 1 Mbps
< 6.8 mA/channel at 100 Mbps
2.70 V Operation:
< 2.3 mA/channel at 1 Mbps
< 4.6 mA/channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
Precise timing (typical)
11 ns propagation delay max
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient immunity 45 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1 (reinforced insulation)
Ordering Information:
See page 29.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2 Rev. 1.1

Rev. 1.1 3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12. Top Marking: 8-Pin Narrow-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
4 Rev. 1.1
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteresis VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—50—
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 5
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0 1.1 3.0 1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5 1.9 5.3 2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.4 1.9 5.1 2.9 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.1 1.5 3.1 2.1 mA
Si8420Bx
VDD1
VDD2
—
—3.6 2.6 5.4 3.6 mA
Si8421Bx
VDD1
VDD2
—
—3.2 3.2 4.5 4.5 mA
Si8422Bx
VDD1
VDD2
—
—3.2 3.2 4.5 4.5 mA
Si8423Bx
VDD1
VDD2
—
—3.4 2.5 5.1 3.5 mA
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
6 Rev. 1.1
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.1 5.0 3.1 6.3 mA
Si8420Bx
VDD1
VDD2
—
—3.7 9.8 5.4 12.3 mA
Si8421Bx
VDD1
VDD2
—
—6.8 6.8 8.5 8.5 mA
Si8422Bx
VDD1
VDD2
—
—6.8 6.8 8.5 8.5 mA
Si8423Bx
VDD1
VDD2
—
—3.4 9.2 5.1 11.5 mA
Timing Characteristics
Si8422Ax, Si8423Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si8422Bx, Si8423Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
All Models
Output Rise Time trCL= 15 pF — 2.0 4.0 ns
Output Fall Time tfCL= 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 20 45 — kV/µs
Start-up Time3tSU —1540µs
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 7
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Figure 1. Propagation Delay Timing
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
8 Rev. 1.1
Table 2. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteresis VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance (Si8410/20)1ZO—50—
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 9
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0 1.1 3.0 1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5 1.9 5.3 2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.4 1.9 5.1 2.9 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0 1.3 3.0 1.8 mA
Si8420Bx
VDD1
VDD2
—
—3.5 2.3 5.3 3.2 mA
Si8421Bx
VDD1
VDD2
—
—3.0 3.0 4.4 4.4 mA
Si8422Bx
VDD1
VDD2
—
—3.0 3.0 4.4 4.4 mA
Si8423Bx
VDD1
VDD2
—
—3.4 2.2 5.1 3.1 mA
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
10 Rev. 1.1
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0 3.6 3.0 4.5 mA
Si8420Bx
VDD1
VDD2
—
—4.5 7.0 5.3 8.8 mA
Si8421Bx
VDD1
VDD2
—
—5.3 5.3 6.6 6.6 mA
Si8422Bx
VDD1
VDD2
—
—5.3 5.3 6.6 6.6 mA
Si8423Bx
VDD1
VDD2
—
—3.4 6.6 5.1 8.3 mA
Timing Characteristics
Si8422Ax, Si8423Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si8422Bx, Si8423Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.