Silicon Laboratories Si8410 User manual

Rev. 1.1 8/11 Copyright © 2011 by Silicon Laboratories Si8410/20/21 / Si8422/23
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
LOW-POWER, SINGLE AND DUAL-CHANNEL
DIGITAL ISOLATORS
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering
substantial data rate, propagation delay, power, size, reliability, and external BOM
advantages when compared to legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges and
throughout device service life for ease of design and highly uniform performance.
All device versions have Schmitt trigger inputs for high noise immunity and only
require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case
propagation delays of less than 10 ns. Ordering options include a choice of
isolation ratings (up to 5 kV) and a selectable fail-safe operating mode to control
the default output state during power loss. All products are safety certified by UL,
CSA, and VDE, and products in wide-body packages support reinforced insulation
withstanding up to 5 kVRMS.
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.6–5.5 V
Up to 5000 VRMS isolation
High electromagnetic immunity
Ultra low power (typical)
5 V Operation:
< 2.6 mA/channel at 1 Mbps
< 6.8 mA/channel at 100 Mbps
2.70 V Operation:
< 2.3 mA/channel at 1 Mbps
< 4.6 mA/channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
Precise timing (typical)
11 ns propagation delay max
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient immunity 45 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1 (reinforced insulation)
Ordering Information:
See page 29.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2 Rev. 1.1

Rev. 1.1 3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12. Top Marking: 8-Pin Narrow-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
4 Rev. 1.1
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteresis VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—50—
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 5
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0 1.1 3.0 1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5 1.9 5.3 2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.4 1.9 5.1 2.9 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.1 1.5 3.1 2.1 mA
Si8420Bx
VDD1
VDD2
—
—3.6 2.6 5.4 3.6 mA
Si8421Bx
VDD1
VDD2
—
—3.2 3.2 4.5 4.5 mA
Si8422Bx
VDD1
VDD2
—
—3.2 3.2 4.5 4.5 mA
Si8423Bx
VDD1
VDD2
—
—3.4 2.5 5.1 3.5 mA
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
6 Rev. 1.1
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.1 5.0 3.1 6.3 mA
Si8420Bx
VDD1
VDD2
—
—3.7 9.8 5.4 12.3 mA
Si8421Bx
VDD1
VDD2
—
—6.8 6.8 8.5 8.5 mA
Si8422Bx
VDD1
VDD2
—
—6.8 6.8 8.5 8.5 mA
Si8423Bx
VDD1
VDD2
—
—3.4 9.2 5.1 11.5 mA
Timing Characteristics
Si8422Ax, Si8423Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si8422Bx, Si8423Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
All Models
Output Rise Time trCL= 15 pF — 2.0 4.0 ns
Output Fall Time tfCL= 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 20 45 — kV/µs
Start-up Time3tSU —1540µs
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 7
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Figure 1. Propagation Delay Timing
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
8 Rev. 1.1
Table 2. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteresis VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance (Si8410/20)1ZO—50—
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 9
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0 1.1 3.0 1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5 1.9 5.3 2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.4 1.9 5.1 2.9 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0 1.3 3.0 1.8 mA
Si8420Bx
VDD1
VDD2
—
—3.5 2.3 5.3 3.2 mA
Si8421Bx
VDD1
VDD2
—
—3.0 3.0 4.4 4.4 mA
Si8422Bx
VDD1
VDD2
—
—3.0 3.0 4.4 4.4 mA
Si8423Bx
VDD1
VDD2
—
—3.4 2.2 5.1 3.1 mA
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
10 Rev. 1.1
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0 3.6 3.0 4.5 mA
Si8420Bx
VDD1
VDD2
—
—4.5 7.0 5.3 8.8 mA
Si8421Bx
VDD1
VDD2
—
—5.3 5.3 6.6 6.6 mA
Si8422Bx
VDD1
VDD2
—
—5.3 5.3 6.6 6.6 mA
Si8423Bx
VDD1
VDD2
—
—3.4 6.6 5.1 8.3 mA
Timing Characteristics
Si8422Ax, Si8423Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si8422Bx, Si8423Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 11
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
All Models
Output Rise Time trCL= 15 pF — 2.0 4.0 ns
Output Fall Time tfCL= 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 20 45 — kV/µs
Start-up Time3tSU —1540µs
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
12 Rev. 1.1
Table 3. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteresis VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.
42.3 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance2ZO—50—
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 13
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0 1.1 3.0 1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5 1.9 5.3 2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8 2.8 4.2 4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.3 1.8 5.0 2.8 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0 1.1 3.0 1.7 mA
Si8420Bx
VDD1
VDD2
—
—3.5 2.1 5.3 3.0 mA
Si8421Bx
VDD1
VDD2
—
—2.9 2.9 4.3 4.3 mA
Si8422Bx
VDD1
VDD2
—
—2.9 2.9 4.3 4.3 mA
Si8423Bx
VDD1
VDD2
—
—3.4 2.0 5.1 2.9 mA
Table 3. Electrical Characteristics1(Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
14 Rev. 1.1
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0 2.0 3.0 3.0 mA
Si8420Bx
VDD1
VDD2
—
—3.5 5.5 5.3 6.9 mA
Si8421Bx
VDD1
VDD2
—
—4.6 4.6 5.8 5.8 mA
Si8422Bx
VDD1
VDD2
—
—4.6 4.6 5.8 5.8 mA
Si8423Bx
VDD1
VDD2
—
—3.4 5.2 5.1 6.5 mA
Timing Characteristics
Si8422Ax, Si8423Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew3tPSK(P-P) ——40ns
Channel-Channel Skew tPSK ——35ns
Si8422Bx, Si8423Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew3tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
Table 3. Electrical Characteristics1(Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.

Rev. 1.1 15
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
All Models
Output Rise Time trCL= 15 pF — 2.0 4.0 ns
Output Fall Time tfCL= 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 20 45 — kV/µs
Start-up Time4tSU —1540µs
Table 4. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 C°
Operating Temperature TA–40 — 125 C°
Supply Voltage VDD1, VDD2 –0.5 — 6.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive Channel IO——10mA
Lead Solder Temperature (10 s) — — 260 C°
Maximum Isolation Voltage (1 s) NB SOIC-8 — — 4500 VRMS
Maximum Isolation Voltage (1 s) WB SOIC-16 — — 6500 VRMS
Notes:
1. Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
Table 3. Electrical Characteristics1(Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
16 Rev. 1.1
Table 5. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 C°
Supply Voltage VDD1 2.70 — 5.5 V
VDD2 2.70 — 5.5 V
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working volt-
age.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working volt-
age.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 29.

Rev. 1.1 17
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 7. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
WB
SOIC-16 NB SOIC-8
Nominal Air Gap (Clearance)1L(IO1) 8.0 min 4.9 min mm
Nominal External Tracking (Creepage)1L(IO2) 8.0 min 4.01 min mm
Minimum Internal Gap (Internal Clearance) 0.014 0.008 mm
Tracking Resistance
(Proof Tracking Index) PTI IEC60112 600 600 VRMS
Erosion Depth ED 0.019 0.040 mm
Resistance (Input-Output)2RIO 101,2 101,2 
Capacitance (Input-Output)2CIO f = 1 MHz 2.0 1.0 pF
Input Capacitance3CI4.0 4.0 pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline:
16-Pin Wide Body SOIC”, “9. Package Outline: 8-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage
limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB SOIC-8 package. UL does
not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and
creepage limits as 3.9 mm minimum for the NB SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8)
are shorted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Test Conditions Specification
NB SOIC8 WB SOIC 16
Basic Isolation Group Material Group I I
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV I-IV
Rated Mains Voltages < 300 VRMS I-III I-IV
Rated Mains Voltages < 400 VRMS I-II I-III
Rated Mains Voltages < 600 VRMS I-II I-III

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
18 Rev. 1.1
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxx*
Parameter Symbol Test Condition Characteristic Unit
WB
SOIC-16 NB SOIC-8
Maximum Working Insulation
Voltage VIORM 891 560 Vpeak
Input to Output Test Voltage
Method b1
(VIORM x1.875=V
PR, 100%
Production Test, tm= 1 sec,
Partial Discharge < 5 pC)
1671 1050
Transient Overvoltage VIOTM t = 60 sec 6000 4000 Vpeak
Pollution Degree
(DIN VDE 0110, Table 1) 22
Insulation Resistance at TS,
VIO =500V RS>109>109
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter Symbol Test Condition Min Typ Max Unit
WB
SOIC-16 NB SOIC-8
Case Temperature TS— — 150 150 °C
Safety Input, Output, or
Supply Current ISJA = 140 °C/W (NB SOIC-8),
100 °C (WB SOIC-16),
VI=5.5V,T
J=150°C,T A=25°C
— — 220 160 mA
Device Power
Dissipation2PD— — 150 150 mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 2 and 3.
2. The Si84xx is tested with VDD1 = VDD2 = 5.5 V, TJ=150ºC,C
L= 15 pF, input a 150 Mbps 50% duty cycle square
wave.

Rev. 1.1 19
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Figure 3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 11. Thermal Characteristics
Parameter Symbol WB SOIC-16 NB SOIC-8 Unit
IC Junction-to-Air Thermal Resistance JA 100 140 ºC/W
0 20015010050
500
250
125
0
Case Temperature (ºC)
Safety-Limiting Values (mA)
460
375 VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.3 V
VDD1, VDD2 = 5.5 V
360
220
0 20015010050
400
200
100
0
Case Temperature (ºC)
Safety-Limiting Values (mA)
320
300 VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.3 V
VDD1, VDD2 = 5.5 V
270
160

Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
20 Rev. 1.1
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 4.
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Figure 5. Modulation Scheme
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Input Signal
Output Signal
Modulation Signal