Silicon Laboratories EFM32JG1 User manual

EFM32 Jade Gecko Family
EFM32JG1 Reference Manual
The EFM32 Jade Gecko MCUs are the world’s most energy-
friendly microcontrollers.
EFM32JG1 features a powerful 32-bit ARM® Cortex-M3 and a wide selection of periph-
erals, including a unique cryptographic hardware engine supporting AES, ECC, and
SHA. These features, combined with ultra-low current active mode and short wake-up
time from energy-saving modes, make EFM32JG1 microcontrollers well suited for any
battery-powered application, as well as other systems requiring high performance and
low-energy consumption.
Example applications:
ENERGY FRIENDLY FEATURES
• ARM Cortex-M3 at 40 MHz
• Ultra low energy operation:
• 2.1 μA EM3 Stop current (CRYOTIMER
running with state/RAM retention)
• 2.5 μA EM2 DeepSleep current (RTCC
running with state and RAM retention)
• 63 μA/MHz in Energy Mode 0 (EM0)
• Hardware cryptographic engine supports
AES, ECC, and SHA
• Integrated dc-dc converter
• CRYOTIMER operates down to EM4
• 5 V tolerant I/O
• IoT devices and sensors
• Health and fitness
• Smart accessories
• Home automation and security
• Industrial and factory automation
Peripheral Reflex System
32-bit bus
Core / Memory
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Hibernate EM4 - Shutoff
EM0 - Active EM3 - Stop
Serial Interfaces
USART
Low Energy UARTTM
I2C
I/O Ports Timers and Triggers
CRYOTIMER
Real Time Counter
and Calendar
Other
CRYPTO
CRC
Analog Interfaces
ADC
IDAC
Analog Comparator
Timer/Counter Low Energy Timer
Pulse Counter
Watchdog Timer
External Interrupts
General Purpose I/O
Pin Reset
Pin Wakeup
Flash Program
Memory RAM Memory
ARM CortexTM M3 processor
Debug Interface DMA Controller
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Clock Management
Low Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Ultra Low
Frequency RC
Oscillator
Auxiliary High
Frequency RC
Oscillator
Memory
Protection Unit
High Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1. About This Document
1.1 Introduction
This document contains reference material for the EFM32 Jade Gecko devices. All modules and peripherals in the EFM32 Jade Gecko
devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such
differences, including pinout, are covered in the device data sheets.
EFM32JG1 Reference Manual
About This Document
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 1

1.2 Conventions
Register Names
Register names are given with a module name prefix followed by the short register name:
TIMERn_CTRL - Control Register
The "n" denotes the module number for modules which can exist in more than one instance.
Some registers are grouped which leads to a group name following the module prefix:
GPIO_Px_DOUT - Port Data Out Register
The "x" denotes the different ports.
Bit Fields
Registers contain one or more bit fields which can be 1 to 32 bits wide. Bit fields wider than 1 bit are given with start (x) and stop (y) bit
[y:x].
Bit fields containing more than one bit are unsigned integers unless otherwise is specified.
Unspecified bit field settings must not be used, as this may lead to unpredictable behaviour.
Address
The address for each register can be found by adding the base address of the module found in the Memory Map (see Figure 4.2 Sys-
tem Address Space with Core and Code Space Listing on page 15), and the offset address for the register (found in module Register
Map).
Access Type
The register access types used in the register descriptions are explained in Table 1.1 Register Access Types on page 2.
Table 1.1. Register Access Types
Access Type Description
R Read only. Writes are ignored
RW Readable and writable
RW1 Readable and writable. Only writes to 1 have effect
(R)W1 Sometimes readable. Only writes to 1 have effect. Currently only
used for IFC registers (see 3.3.1.2 IFC Read-clear Operation)
W1 Read value undefined. Only writes to 1 have effect
W Write only. Read value undefined.
RWH Readable, writable, and updated by hardware
RW(nB), RWH(nB), etc. "(nB)" suffix indicates that register explicitly does not support pe-
ripheral bit set or clear (see 4.2.2 Peripheral Bit Set and Clear)
RW(a), R(a), etc. "(a)" suffix indicates that register has actionable reads (see
5.3.6 Debugger reads of actionable registers)
Number format
0x prefix is used for hexadecimal numbers
0b prefix is used for binary numbers
Numbers without prefix are in decimal representation.
Reserved
Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the
Register Description. Reserved bits might be read as 1 in future devices.
EFM32JG1 Reference Manual
About This Document
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 2

Reset Value
The reset value denotes the value after reset.
Registers denoted with X have unknown value out of reset and need to be initialized before use. Note that read-modify-write operations
on these registers before they are initialized results in undefined register values.
Pin Connections
Pin connections are given with a module prefix followed by a short pin name:
CMU_CLKOUT1 (Clock management unit, clock output pin number 1)
The location for the pin names given in the module documentation can be found in the device-specific datasheet.
1.3 Related Documentation
Further documentation on the EFM32 Jade Gecko devices and the ARM Cortex-M3 can be found at the Silicon Labs and ARM web
pages:
www.silabs.com
www.arm.com
EFM32JG1 Reference Manual
About This Document
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 3

2. System Overview
0 1 2 3 4
Quick Facts
What?
The EFM32 Jade Gecko is a highly integrated, con-
figurable and low power MCU with a complete set of
peripherals.
Why?
EFM32 Jade Gecko features an Cortex-M3 core, a
unique cryptographic hardware engine supporting
AES, ECC, and SHA, ultra-low current active mode,
and short wake-up time from energy-saving modes.
How?
EFM32 Jade Gecko microcontrollers are well suited
for any batter-powered application, as well as other
systems requiring high performance and low-energy
consumption
2.1 Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32
Jade Gecko microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption.
EFM32JG1 Reference Manual
System Overview
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 4

2.2 Block Diagrams
The block diagram for the EFM32 Jade Gecko MCU series is shown in (Figure 2.1 EFM32 Jade Gecko System-On-Chip Block Diagram
on page 5).
Peripheral Reflex System
32-bit bus
Core / Memory
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Hibernate EM4 - Shutoff
EM0 - Active EM3 - Stop
Serial Interfaces
USART
Low Energy UARTTM
I2C
I/O Ports Timers and Triggers
CRYOTIMER
Real Time Counter
and Calendar
Other
CRYPTO
CRC
Analog Interfaces
ADC
IDAC
Analog Comparator
Timer/Counter Low Energy Timer
Pulse Counter
Watchdog Timer
External Interrupts
General Purpose I/O
Pin Reset
Pin Wakeup
Flash Program
Memory RAM Memory
ARM CortexTM M3 processor
Debug Interface DMA Controller
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Clock Management
Low Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Ultra Low
Frequency RC
Oscillator
Auxiliary High
Frequency RC
Oscillator
Memory
Protection Unit
High Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
Figure 2.1. EFM32 Jade Gecko System-On-Chip Block Diagram
EFM32JG1 Reference Manual
System Overview
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 5

2.3 MCU Features overview
•ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 40 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
•Flexible Energy Management System
• Power routing configurations including DCDC control
• Voltage Monitoring and Brown Out Detection
• State Retention
•256 KB Flash
•32 KB RAM
•Up to 32 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
•8 Channel DMA Controller
• Alternate/primary descriptors with scatter-gather/ping-pong operation
•12 Channel Peripheral Reflex System
• Autonomous inter-peripheral signaling enables smart operation in low energy modes
•CRYPTO Advanced Encryption Standard Accelerator
• AES encryption / decryption, with 128 or 256 bit keys
• Multiple AES modes of operation, including Counter (CTR), Galois/Counter Mode (GCM), Cipher Block Chaining (CBC), Cipher
Feedback (CFB) and Output Feedback (OFB).
• Accelerated SHA-1 and SHA-2
• Accelerated Elliptic Curve Cryptography (ECC), with binary or prime fields
• Flexible 256-bit ALU and sequencer
•General Purpose Cyclic Redundancy Check
• Programmable 16-bit polynomial, fixed 32-bit polynomial
•Communication interfaces
• 2×Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Hardware flow control
• 4-16 data bits
• 1× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
•1×I2C Interface with SMBus support
• Address recognition in Stop Mode
•Timers/Counters
• 2× 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 32-bit Ultra Low Energy Timer/Counter (CRYOTIMER) for periodic wake-up from any Energy Mode
• 32-bit Real-Time Counter and Calendar
• 16+16+32 bit Protocol Timer
• 16-bit Pulse Counter
• Asynchronous pulse counting/quadrature decoding
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 input channels and on-chip temperature sensor
EFM32JG1 Reference Manual
System Overview
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 6

• Single ended or differential operation
• Conversion tailgating for predictable latency
• Current Digital to Analog Converter
• Source or sink a configurable constant current
• 2× Analog Comparator
• Programmable speed/current
• Capacitive sensing with up to 8 inputs
• Analog Port
•Ultra efficient Power-on Reset and Brown-Out Detector
•Debug Interface
• 4-pin Joint Test Action Group (JTAG) interface
• 2-pin serial-wire debug (SWD) interface
2.4 Oscillators and Clocks
EFM32 Jade Gecko has six different oscillators integrated, as shown in Table 2.1 EFM32 Jade Gecko Oscillators on page 7
Table 2.1. EFM32 Jade Gecko Oscillators
Oscillator Frequency Optional? External
components
Description
HFXO 38 MHz - 40 MHz No Crystal High accuracy, low jitter high frequency crystal oscillator. Tun-
able crystal loading capacitors are fully integrated.
HFRCO 1 MHz - 38 MHz No - Medium accuracy RC oscillator, typically used for timing dur-
ing startup of the HFXO or if a precise oscillator is not re-
quired.
AUXHFRCO 1 MHz - 38 MHz No - Medium accuracy RC oscillator, typically used as alternative
clock source for Analog to Digital Converter or Debug Trace.
LFRCO 32768 Hz No - Medium accuracy frequency reference typically used for medi-
um accuracy RTCC timing.
LFXO 32768 Hz Yes Crystal High accuracy frequency reference typically used for high ac-
curacy RTCC timing. Tunable crystal loading capacitors are
fully integrated.
ULFRCO 1000 Hz No - Ultra low frequency oscillator typically used for the watchdog
timer.
The RC oscillators can be calibrated against either of the crystal oscillators in order to compensate for temperature and voltage supply
variations. Hardware support is included to measure the frequency of various oscillators against each other.
Oscillator and clock management is available through the Clock Management Unit (CMU), see section 10. CMU - Clock Management
Unit for details.
2.5 Hardware CRC Support
EFM32 Jade Gecko supports a configurable CRC generation:
• 8, 16, 24 or 32 bit CRC value
• Configurable polynomial and initialization value
• Optional inversion of CRC value over air
• Configurable CRC byte ordering
• Support for multiple CRC values calculated and verified per transmitted or received frame
EFM32JG1 Reference Manual
System Overview
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 7

2.6 Data Encryption and Authentication
EFM32 Jade Gecko has hardware support for AES encryption, decryption and authentication modes. These security operations can be
performed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits.
AES modes of operations directly supported by the EFM32 Jade Gecko hardware are listed in Table 2.2 AES modes of operation with
hardware support on page 8. In addition to these modes, other modes can also be implemented by using combinations of modes.
For example, the CCM mode can be implemented using the CTR and CBC-MAC modes in combination.
Table 2.2. AES modes of operation with hardware support
AES Mode Encryption / Decryption Authentication Comment
ECB Yes - Electronic Code Book
CTR Yes - Counter mode
CCM Yes Yes Counter with CBC-MAC
CCM* Yes Yes CCM with encryption-only and
integrity-only capabilities
GCM Yes Yes Galois Counter Mode
CBC Yes - Cipher Block Chaining
CBC-MAC - Yes Cipher Block Chaining, Mes-
sage Authentication Code
CMAC - Yes Cipher-basec MAC
CFB Yes - Cipher Feedback
OFB Yes - Output Feedback
The CRYPTO module can provide data directly from the embedded Cortex-M3 or via DMA.
EFM32JG1 Reference Manual
System Overview
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 8

2.7 Timers
EFM32 Jade Gecko includes multiple timers, as can be seen from Table 2.3 EFM32 Jade Gecko Timers Overview on page 9.
Table 2.3. EFM32 Jade Gecko Timers Overview
Timer Number of instances Typical clock source Overview
RTCC 1 Low frequency (LFXO or
LFRCO)
32 bit Real Time Counter and
Calendar, typically used to ac-
curately time inactive periods
and enable wakeup on compare
match.
TIMER 2 High frequency (HFXO or
HFRCO)
16 bit general purpose timer.
Systick timer 1 High frequency (HFXO or
HFRCO)
32 bit systick timer integrated in
the Cortex-M3. Typically used
as an Operating System timer.
WDOG 1 Low frequency (LFXO, LFRCO
or ULFRCO)
Watch dog timer. Once enabled,
this module must be periodically
accessed. If not, this is consid-
ered an error and the EFM32
Jade Gecko is reset in order to
recover the system.
LETIMER 1 Low frequency (LFXO, LFRCO
or ULFRCO)
Low energy general purpose
timer.
Advanced interconnect features allows synchronization between timers. This includes:
• Start / stop any high frequency timer synchronized with the RTCC
• Trigger RSM state transitions based on compare timer compare match, for instance to provide clock cycle accuracy on frame trans-
mit timing
EFM32JG1 Reference Manual
System Overview
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 9

3. System Processor
0 1 2 3 4
CM3Core
32-bit ALU
Control Logic Thumb & Thumb-2
Decode
Instruction Interface Data Interface
NVIC Interface
Single cycle
32-bit multiplier
Hardware divider
Memory Protection Unit
Quick Facts
What?
The industry leading Cortex-M3 processor from
ARM is the CPU in the EFM32 Jade Gecko devices.
Why?
The ARM Cortex-M3 is designed for exceptionally
short response time, high code density, and high 32-
bit throughput while maintaining a strict cost and
power consumption budget.
How?
Combined with the ultra low energy peripherals
available in EFM32 Jade Gecko devices, the Cortex-
M3 processor's Harvard architecture, 3 stage pipe-
line, single cycle instructions, Thumb-2 instruction
set support, and fast interrupt handling make it per-
fect for 8-bit, 16-bit, and 32-bit applications.
3.1 Introduction
The ARM Cortex-M3 32-bit RISC processor provides outstanding computational performance and exceptional system response to inter-
rupts while meeting low cost requirements and low power consumption.
The ARM Cortex-M3 implemented is revision r2p1.
EFM32JG1 Reference Manual
System Processor
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 10

3.2 Features
• Harvard architecture
• Separate data and program memory buses (No memory bottleneck as in a single bus system)
• 3-stage pipeline
• Thumb-2 instruction set
• Enhanced levels of performance, energy efficiency, and code density
• Single cycle multiply and hardware divide instructions
• 32-bit multiplication in a single cycle
• Signed and unsigned divide operations between 2 and 12 cycles
• Atomic bit manipulation with bit banding
• Direct access to single bits of data
• Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions
• Atomic operation, cannot be interrupted by other bus activities
• 1.25 DMIPS/MHz
• Memory Protection Unit
• Up to 8 protected memory regions
• 24 bits System Tick Timer for Real Time OS
• Excellent 32-bit migration choice for 8/16 bit architecture based designs
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplici-
ty of legacy 8-bit and 16-bit architectures
• Alligned or unaligned data storage and access
• Contiguous storage of data requiring different byte lengths
• Data access in a single core access cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
3.3 Functional Description
For a full functional description of the ARM Cortex-M3 implementation in the EFM32 Jade Gecko family, the reader is referred to the
ARM Cortex-M3 documentation.
EFM32JG1 Reference Manual
System Processor
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 11

3.3.1 Interrupt Operation
Module Cortex-M4 NVIC
IEN[n]
IF[n]
set clear
IFS[n] IFC[n]
Interrupt
condition
IRQ
SETENA[n]/CLRENA[n]
Interrupt
request
SETPEND[n]/CLRPEND[n]
set clear
Active interrupt
Software generated interrupt
Figure 3.1. Interrupt Operation
The interrupt request (IRQ) lines are connected to the Cortex-M3. Each of these lines (shown in Table 3.1 Interrupt Request Lines (IRQ)
on page 13) is connected to one or more interrupt flags in one or more modules. The interrupt flags are set by hardware on an inter-
rupt condition. It is also possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its
own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the IRQ. A high IRQ line will set the
corresponding pending bit (can also be set/cleared with the SETPEND/CLRPEND bits in ISPR0/ICPR0) in the Cortex-M3 NVIC. The
pending bit is then qualified with an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt
request to the core. Figure 3.1 Interrupt Operation on page 12 illustrates the interrupt system. For more information on how the inter-
rupts are handled inside the Cortex-M3, the reader is referred to the EFM32 Cortex-M3 Reference Manual.
3.3.1.1 Avoiding Extraneous Interrupts
There can be latencies in the system such that clearing an interrupt flag could take longer than leaving an Interrupt Service Routine
(ISR). This can lead to the ISR being re-entered as the interrupt flag has yet to clear immediately after leaving the ISR. To avoid this,
when clearing an interrupt flag at the end of an ISR, the user should execute ARM's Data Synchronization Barrier (DSB) instruction.
Another approach is to clear the interrupt flag immediately after identifying the interrupt source and then service the interrupt as shown
in the pseudo-code below. The ISR typically is sufficiently long to more than cover the few cycles it may take to clear the interrupt sta-
tus, and also allows the status to be checked for further interrupts before exiting the ISR.
irqXServiceRoutine() {
do {
clearIrqXStatus();
serviceIrqX();
} while(irqXStatusIsActive());
}
3.3.1.2 IFC Read-clear Operation
In addition to the normal interrupt setting and clearing operations via the IFS/IFC registers, there is an additional atomic Read-clear
operation that can be enabled by setting IFCREADCLEAR=1 in the MSC_CTRL register. When enabled, reads of peripheral IFC regis-
ters will return the interrupt vector (mirroring the IF register), while at the same time clearing whichever interrupt flags are set. This oper-
ation is functionally equivalent to reading the IF register and then writing the result immediately back to the IFC register.
EFM32JG1 Reference Manual
System Processor
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 12

3.3.2 Interrupt Request Lines (IRQ)
Table 3.1. Interrupt Request Lines (IRQ)
IRQ # Source
0 EMU
2 WDOG0
8 LDMA
9 GPIO_EVEN
10 TIMER0
11 USART0_RX
12 USART0_TX
13 ACMP0
14 ADC0
15 IDAC0
16 I2C0
17 GPIO_ODD
18 TIMER1
19 USART1_RX
20 USART1_TX
21 LEUART0
22 PCNT0
23 CMU
24 MSC
25 CRYPTO
26 LETIMER0
29 RTCC
31 CRYOTIMER
33 FPUEH
EFM32JG1 Reference Manual
System Processor
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 13

4. Memory and Bus System
0 1 2 3 4
ARM Cortex-M
DMA Controller
RAM
Peripherals
Flash
Quick Facts
What?
A low latency memory system including low energy
Flash and RAM with data retention which makes the
energy modes attractive.
Why?
RAM retention reduces the need for storing data in
Flash and enables frequent use of the ultra low en-
ergy modes EM2 DeepSleep and EM3 Stop.
How?
Low energy and non-volatile Flash memory stores
program and application data in all energy modes
and can easily be reprogrammed in system. Low
leakage RAM with data retention in EM0 Active to
EM3 Stop removes the data restore time penalty,
and the DMA ensures fast autonomous transfers
with predictable response time.
4.1 Introduction
The EFM32 Jade Gecko contains an AMBA AHB Bus system to allow bus masters to access the memory mapped address space. A
multilayer AHB bus matrix connects the 4 master bus interfaces to the AHB slaves (Figure 4.1 EFM32 Jade Gecko Bus System on
page 14). The bus matrix allows several AHB slaves to be accessed simultaneously. An AMBA APB interface is used for the peripher-
als, which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The 4 AHB bus masters are:
•Cortex-M3 ICode: Used for instruction fetches from Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
•Cortex-M3 DCode: Used for debug and data access to Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
•Cortex-M3 System: Used for data and debug access to system space. It can access entire memory space except Code memory
(valid address range: 0x20000000 - 0xFFFFFFFF)
•DMA: Can access entire memory space except internal core memory region and Code memory (valid address range: 0x20000000 -
0xDFFFFFFF)
ARM
Cortex-M
AHB Multilayer
Bus Matrix
DCode
System
DMA
Flash
RAM
AHB/
APB
Bridge
ICode
CRYPTO
Peripheral 0
Peripheral n
Figure 4.1. EFM32 Jade Gecko Bus System
EFM32JG1 Reference Manual
Memory and Bus System
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 14

4.2 Functional Description
The memory segments are mapped together with the internal segments of the Cortex-M3 into the system memory map shown by Fig-
ure 4.2 System Address Space with Core and Code Space Listing on page 15.
Figure 4.2. System Address Space with Core and Code Space Listing
Additionally, the peripheral address map is detailed by Figure 4.3 System Address Space with Peripheral Listing on page 16.
EFM32JG1 Reference Manual
Memory and Bus System
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 15

Figure 4.3. System Address Space with Peripheral Listing
The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32 Jade Gecko. When running code located in
SRAM starting at this address, the Cortex-M3 uses the System bus interface to fetch instructions. This results in reduced performance
as the Cortex-M3 accesses stack, other data in SRAM and peripherals using the System bus interface. To be able to run code from
SRAM efficiently, the SRAM is also mapped in the code space at address 0x10000000. When running code from this space, the Cortex-
M3 fetches instructions through the I/D-Code bus interface, leaving the System bus interface for data access. The SRAM mapped into
the code space can however only be accessed by the CPU, i.e. not the DMA.
EFM32JG1 Reference Manual
Memory and Bus System
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 16

4.2.1 Bit-banding
The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and 0x42000000 respectively. Read and
write operations to these regions are converted into masked single-bit reads and atomic single-bit writes to the embedded SRAM and
peripherals of the EFM32 Jade Gecko.
Note: Bit-banding is only available through the CPU. No other AHB masters (e.g., DMA) can perform Bit-banding operations.
Using a standard approach to modify a single register or SRAM bit in the aliased regions, would require software to read the value of
the byte, half-word or word containing the bit, modify the bit, and then write the byte, half-word or word back to the register or SRAM
address. Using bit-banding, this can be done in a single operation, consuming only two bus cycles. As read-writeback, bit-masking and
bit-shift operations are not necessary in software, code size is reduced and execution speed improved.
The bit-band regions allow each bit in the SRAM and Peripheral areas of the memory map to be addressed. To set or clear a bit in the
embedded SRAM, write a 1 or a 0 to the following address:
bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4
where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word.
To modify a bit in the Peripheral area, use the following address:
bit_address = 0x42000000 + (address – 0x40000000) × 32 + bit × 4
EFM32JG1 Reference Manual
Memory and Bus System
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 17

4.2.2 Peripheral Bit Set and Clear
The EFM32 Jade Gecko supports bit set and bit clear access to all peripherals except those listed in Table 4.1 Peripherals that Do Not
Support Bit Set and Bit Clear on page 18. The bit set and bit clear functionality (also called Bit Access) enables modification of bit
fields (single bit or multiple bit wide) without the need to perform a read-modify-write (though it is functionally equivalent). Also, the op-
eration is contained within a single bus access (for HF peripherals), unlike the Bit-banding operation described in section 4.2.1 Bit-
banding which consumes two bus accesses per operation. All AHB masters can utilize this feature.
The bit clear aliasing region starts at 0x44000000 and the bit set aliasing region starts at 0x46000000. Thus, to apply a bit set or clear
operation, write the bit set or clear mask to the following addresses:
bit_clear_address = address + 0x04000000
bit_set_address = address + 0x06000000
For bit set operations, bit locations that are 1 in the bit mask will be set in the destination register:
register = (register OR mask)
For bit clear operations, bit locations that are 1 in the bit mask will be cleared in the destination register:
register = (register AND (NOT mask))
Note: It is possible to combine bit clear and bit set operations in order to arbitrarily modify multi-bit register fields, without affecting other
fields in the same register. In this case, care should be taken to ensure that the field does not have intermediate values that can lead to
erroneous behavior. For example, if bit clear and bit set operations are used to change an analog tuning register field from 25 to 26, the
field would initially take on a value of zero. If the analog module is active at the time, this could lead to undesired behavior.
The peripherals listed in Table 4.1 Peripherals that Do Not Support Bit Set and Bit Clear on page 18 do not support Bit Access for any
registers. All other peripherals do support Bit Access, however, there may be cases of certain registers that do not support it. Such
registers have a note regarding this lack of support.
Table 4.1. Peripherals that Do Not Support Bit Set and Bit Clear
Module
EMU
RMU
CRYOTIMER
EFM32JG1 Reference Manual
Memory and Bus System
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 18

4.2.3 Peripherals
The peripherals are mapped into the peripheral memory segment, each with a fixed size address range according to Table 4.2 Periph-
erals on page 19, Table 4.3 Low Energy Peripherals on page 19 , and Table 4.4 Core Peripherals on page 19.
Table 4.2. Peripherals
Address Range Module Name
0x400E6000 - 0x400E6400 PRS
0x4001E000 - 0x4001E400 CRYOTIMER
0x4001C000 - 0x4001C400 GPCRC
0x40018400 - 0x40018800 TIMER1
0x40018000 - 0x40018400 TIMER0
0x40010400 - 0x40010800 USART1
0x40010000 - 0x40010400 USART0
0x4000C000 - 0x4000C400 I2C0
0x4000A000 - 0x4000B000 GPIO
0x40006000 - 0x40006400 IDAC0
0x40002000 - 0x40002400 ADC0
0x40000400 - 0x40000800 ACMP1
0x40000000 - 0x40000400 ACMP0
Table 4.3. Low Energy Peripherals
Address Range Module Name
0x40052000 - 0x40052400 WDOG0
0x4004E000 - 0x4004E400 PCNT0
0x4004A000 - 0x4004A400 LEUART0
0x40046000 - 0x40046400 LETIMER0
0x40042000 - 0x40042400 RTCC
Table 4.4. Core Peripherals
Address Range Module Name
0x400F0000 - 0x400F0400 CRYPTO
0x400E2000 - 0x400E3000 LDMA
0x400E1000 - 0x400E1400 FPUEH
0x400E0000 - 0x400E0800 MSC
4.2.4 Bus Matrix
The Bus Matrix connects the memory segments to the bus masters as detailed in 4.1 Introduction.
EFM32JG1 Reference Manual
Memory and Bus System
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 19