Silicon Laboratories EFM32JG1 User manual

EFM32 Jade Gecko Family
EFM32JG1 Reference Manual
The EFM32 Jade Gecko MCUs are the world’s most energy-
friendly microcontrollers.
EFM32JG1 features a powerful 32-bit ARM® Cortex-M3 and a wide selection of periph-
erals, including a unique cryptographic hardware engine supporting AES, ECC, and
SHA. These features, combined with ultra-low current active mode and short wake-up
time from energy-saving modes, make EFM32JG1 microcontrollers well suited for any
battery-powered application, as well as other systems requiring high performance and
low-energy consumption.
Example applications:
ENERGY FRIENDLY FEATURES
• ARM Cortex-M3 at 40 MHz
• Ultra low energy operation:
• 2.1 μA EM3 Stop current (CRYOTIMER
running with state/RAM retention)
• 2.5 μA EM2 DeepSleep current (RTCC
running with state and RAM retention)
• 63 μA/MHz in Energy Mode 0 (EM0)
• Hardware cryptographic engine supports
AES, ECC, and SHA
• Integrated dc-dc converter
• CRYOTIMER operates down to EM4
• 5 V tolerant I/O
• IoT devices and sensors
• Health and fitness
• Smart accessories
• Home automation and security
• Industrial and factory automation
Peripheral Reflex System
32-bit bus
Core / Memory
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Hibernate EM4 - Shutoff
EM0 - Active EM3 - Stop
Serial Interfaces
USART
Low Energy UARTTM
I2C
I/O Ports Timers and Triggers
CRYOTIMER
Real Time Counter
and Calendar
Other
CRYPTO
CRC
Analog Interfaces
ADC
IDAC
Analog Comparator
Timer/Counter Low Energy Timer
Pulse Counter
Watchdog Timer
External Interrupts
General Purpose I/O
Pin Reset
Pin Wakeup
Flash Program
Memory RAM Memory
ARM CortexTM M3 processor
Debug Interface DMA Controller
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Clock Management
Low Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Ultra Low
Frequency RC
Oscillator
Auxiliary High
Frequency RC
Oscillator
Memory
Protection Unit
High Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1. About This Document
1.1 Introduction
This document contains reference material for the EFM32 Jade Gecko devices. All modules and peripherals in the EFM32 Jade Gecko
devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such
differences, including pinout, are covered in the device data sheets.
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1.2 Conventions
Register Names
Register names are given with a module name prefix followed by the short register name:
TIMERn_CTRL - Control Register
The "n" denotes the module number for modules which can exist in more than one instance.
Some registers are grouped which leads to a group name following the module prefix:
GPIO_Px_DOUT - Port Data Out Register
The "x" denotes the different ports.
Bit Fields
Registers contain one or more bit fields which can be 1 to 32 bits wide. Bit fields wider than 1 bit are given with start (x) and stop (y) bit
[y:x].
Bit fields containing more than one bit are unsigned integers unless otherwise is specified.
Unspecified bit field settings must not be used, as this may lead to unpredictable behaviour.
Address
The address for each register can be found by adding the base address of the module found in the Memory Map (see Figure 4.2 Sys-
tem Address Space with Core and Code Space Listing on page 15), and the offset address for the register (found in module Register
Map).
Access Type
The register access types used in the register descriptions are explained in Table 1.1 Register Access Types on page 2.
Table 1.1. Register Access Types
Access Type Description
R Read only. Writes are ignored
RW Readable and writable
RW1 Readable and writable. Only writes to 1 have effect
(R)W1 Sometimes readable. Only writes to 1 have effect. Currently only
used for IFC registers (see 3.3.1.2 IFC Read-clear Operation)
W1 Read value undefined. Only writes to 1 have effect
W Write only. Read value undefined.
RWH Readable, writable, and updated by hardware
RW(nB), RWH(nB), etc. "(nB)" suffix indicates that register explicitly does not support pe-
ripheral bit set or clear (see 4.2.2 Peripheral Bit Set and Clear)
RW(a), R(a), etc. "(a)" suffix indicates that register has actionable reads (see
5.3.6 Debugger reads of actionable registers)
Number format
0x prefix is used for hexadecimal numbers
0b prefix is used for binary numbers
Numbers without prefix are in decimal representation.
Reserved
Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the
Register Description. Reserved bits might be read as 1 in future devices.
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Reset Value
The reset value denotes the value after reset.
Registers denoted with X have unknown value out of reset and need to be initialized before use. Note that read-modify-write operations
on these registers before they are initialized results in undefined register values.
Pin Connections
Pin connections are given with a module prefix followed by a short pin name:
CMU_CLKOUT1 (Clock management unit, clock output pin number 1)
The location for the pin names given in the module documentation can be found in the device-specific datasheet.
1.3 Related Documentation
Further documentation on the EFM32 Jade Gecko devices and the ARM Cortex-M3 can be found at the Silicon Labs and ARM web
pages:
www.silabs.com
www.arm.com
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2. System Overview
0 1 2 3 4
Quick Facts
What?
The EFM32 Jade Gecko is a highly integrated, con-
figurable and low power MCU with a complete set of
peripherals.
Why?
EFM32 Jade Gecko features an Cortex-M3 core, a
unique cryptographic hardware engine supporting
AES, ECC, and SHA, ultra-low current active mode,
and short wake-up time from energy-saving modes.
How?
EFM32 Jade Gecko microcontrollers are well suited
for any batter-powered application, as well as other
systems requiring high performance and low-energy
consumption
2.1 Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32
Jade Gecko microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption.
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2.2 Block Diagrams
The block diagram for the EFM32 Jade Gecko MCU series is shown in (Figure 2.1 EFM32 Jade Gecko System-On-Chip Block Diagram
on page 5).
Peripheral Reflex System
32-bit bus
Core / Memory
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Hibernate EM4 - Shutoff
EM0 - Active EM3 - Stop
Serial Interfaces
USART
Low Energy UARTTM
I2C
I/O Ports Timers and Triggers
CRYOTIMER
Real Time Counter
and Calendar
Other
CRYPTO
CRC
Analog Interfaces
ADC
IDAC
Analog Comparator
Timer/Counter Low Energy Timer
Pulse Counter
Watchdog Timer
External Interrupts
General Purpose I/O
Pin Reset
Pin Wakeup
Flash Program
Memory RAM Memory
ARM CortexTM M3 processor
Debug Interface DMA Controller
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Clock Management
Low Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Ultra Low
Frequency RC
Oscillator
Auxiliary High
Frequency RC
Oscillator
Memory
Protection Unit
High Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
Figure 2.1. EFM32 Jade Gecko System-On-Chip Block Diagram
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2.3 MCU Features overview
•ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 40 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
•Flexible Energy Management System
• Power routing configurations including DCDC control
• Voltage Monitoring and Brown Out Detection
• State Retention
•256 KB Flash
•32 KB RAM
•Up to 32 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
•8 Channel DMA Controller
• Alternate/primary descriptors with scatter-gather/ping-pong operation
•12 Channel Peripheral Reflex System
• Autonomous inter-peripheral signaling enables smart operation in low energy modes
•CRYPTO Advanced Encryption Standard Accelerator
• AES encryption / decryption, with 128 or 256 bit keys
• Multiple AES modes of operation, including Counter (CTR), Galois/Counter Mode (GCM), Cipher Block Chaining (CBC), Cipher
Feedback (CFB) and Output Feedback (OFB).
• Accelerated SHA-1 and SHA-2
• Accelerated Elliptic Curve Cryptography (ECC), with binary or prime fields
• Flexible 256-bit ALU and sequencer
•General Purpose Cyclic Redundancy Check
• Programmable 16-bit polynomial, fixed 32-bit polynomial
•Communication interfaces
• 2×Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Hardware flow control
• 4-16 data bits
• 1× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
•1×I2C Interface with SMBus support
• Address recognition in Stop Mode
•Timers/Counters
• 2× 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 32-bit Ultra Low Energy Timer/Counter (CRYOTIMER) for periodic wake-up from any Energy Mode
• 32-bit Real-Time Counter and Calendar
• 16+16+32 bit Protocol Timer
• 16-bit Pulse Counter
• Asynchronous pulse counting/quadrature decoding
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 input channels and on-chip temperature sensor
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• Single ended or differential operation
• Conversion tailgating for predictable latency
• Current Digital to Analog Converter
• Source or sink a configurable constant current
• 2× Analog Comparator
• Programmable speed/current
• Capacitive sensing with up to 8 inputs
• Analog Port
•Ultra efficient Power-on Reset and Brown-Out Detector
•Debug Interface
• 4-pin Joint Test Action Group (JTAG) interface
• 2-pin serial-wire debug (SWD) interface
2.4 Oscillators and Clocks
EFM32 Jade Gecko has six different oscillators integrated, as shown in Table 2.1 EFM32 Jade Gecko Oscillators on page 7
Table 2.1. EFM32 Jade Gecko Oscillators
Oscillator Frequency Optional? External
components
Description
HFXO 38 MHz - 40 MHz No Crystal High accuracy, low jitter high frequency crystal oscillator. Tun-
able crystal loading capacitors are fully integrated.
HFRCO 1 MHz - 38 MHz No - Medium accuracy RC oscillator, typically used for timing dur-
ing startup of the HFXO or if a precise oscillator is not re-
quired.
AUXHFRCO 1 MHz - 38 MHz No - Medium accuracy RC oscillator, typically used as alternative
clock source for Analog to Digital Converter or Debug Trace.
LFRCO 32768 Hz No - Medium accuracy frequency reference typically used for medi-
um accuracy RTCC timing.
LFXO 32768 Hz Yes Crystal High accuracy frequency reference typically used for high ac-
curacy RTCC timing. Tunable crystal loading capacitors are
fully integrated.
ULFRCO 1000 Hz No - Ultra low frequency oscillator typically used for the watchdog
timer.
The RC oscillators can be calibrated against either of the crystal oscillators in order to compensate for temperature and voltage supply
variations. Hardware support is included to measure the frequency of various oscillators against each other.
Oscillator and clock management is available through the Clock Management Unit (CMU), see section 10. CMU - Clock Management
Unit for details.
2.5 Hardware CRC Support
EFM32 Jade Gecko supports a configurable CRC generation:
• 8, 16, 24 or 32 bit CRC value
• Configurable polynomial and initialization value
• Optional inversion of CRC value over air
• Configurable CRC byte ordering
• Support for multiple CRC values calculated and verified per transmitted or received frame
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2.6 Data Encryption and Authentication
EFM32 Jade Gecko has hardware support for AES encryption, decryption and authentication modes. These security operations can be
performed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits.
AES modes of operations directly supported by the EFM32 Jade Gecko hardware are listed in Table 2.2 AES modes of operation with
hardware support on page 8. In addition to these modes, other modes can also be implemented by using combinations of modes.
For example, the CCM mode can be implemented using the CTR and CBC-MAC modes in combination.
Table 2.2. AES modes of operation with hardware support
AES Mode Encryption / Decryption Authentication Comment
ECB Yes - Electronic Code Book
CTR Yes - Counter mode
CCM Yes Yes Counter with CBC-MAC
CCM* Yes Yes CCM with encryption-only and
integrity-only capabilities
GCM Yes Yes Galois Counter Mode
CBC Yes - Cipher Block Chaining
CBC-MAC - Yes Cipher Block Chaining, Mes-
sage Authentication Code
CMAC - Yes Cipher-basec MAC
CFB Yes - Cipher Feedback
OFB Yes - Output Feedback
The CRYPTO module can provide data directly from the embedded Cortex-M3 or via DMA.
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2.7 Timers
EFM32 Jade Gecko includes multiple timers, as can be seen from Table 2.3 EFM32 Jade Gecko Timers Overview on page 9.
Table 2.3. EFM32 Jade Gecko Timers Overview
Timer Number of instances Typical clock source Overview
RTCC 1 Low frequency (LFXO or
LFRCO)
32 bit Real Time Counter and
Calendar, typically used to ac-
curately time inactive periods
and enable wakeup on compare
match.
TIMER 2 High frequency (HFXO or
HFRCO)
16 bit general purpose timer.
Systick timer 1 High frequency (HFXO or
HFRCO)
32 bit systick timer integrated in
the Cortex-M3. Typically used
as an Operating System timer.
WDOG 1 Low frequency (LFXO, LFRCO
or ULFRCO)
Watch dog timer. Once enabled,
this module must be periodically
accessed. If not, this is consid-
ered an error and the EFM32
Jade Gecko is reset in order to
recover the system.
LETIMER 1 Low frequency (LFXO, LFRCO
or ULFRCO)
Low energy general purpose
timer.
Advanced interconnect features allows synchronization between timers. This includes:
• Start / stop any high frequency timer synchronized with the RTCC
• Trigger RSM state transitions based on compare timer compare match, for instance to provide clock cycle accuracy on frame trans-
mit timing
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