Singmai Electronics SM06 User manual

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SM06
Advanced Composite Video Interface:
HD-SDI to aCVi
converter module
User Manual
Revision 0.4
1st May 2017

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Revision History
Date Revisions Version
17-07-2016 First Draft. 0.1
28-08-2016 Added support for NTSC/PAL encoding. 0.2
30-12-2016 Updates for Revision 2 PCB. 0.3
01-05-2017 DVI inputs removed.
NTSC/PAL inputs removed.
Minor schematic changes.
Auto standard detection of 29/59Hz
standards.
0.4

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Contents
Revision History....................................................................................................................................... 2
Contents................................................................................................................................................... 3
Tables ....................................................................................................................................................... 3
Figures...................................................................................................................................................... 3
1. Introduction ...................................................................................................................................4
2. aCVi Overview ................................................................................................................................ 5
3. Connecting up the module ............................................................................................................ 7
4. Automatic Cable length compensation. ..................................................................................... 10
5. Circuit description .........................................................................................................................12
6. Specification................................................................................................................................. 24
7. Power Supply Specification......................................................................................................... 25
Tables
Table 1 aCVi supported video formats....................................................................................................5
Figures
Figure 1 SM06 module.............................................................................................................................4
Figure 2 aCVi Spectrum. ..........................................................................................................................6
Figure 3 SM06 Interconnections. ........................................................................................................... 7
Figure 4 UTP connector pin assignments...............................................................................................8
Figure 5 SM06 Data slicing selection - J9. ..............................................................................................8
Figure 6 aCVi cable length compensation (lines 7,8 and 9 of the VBI). .............................................. 10
Figure 7 Original HD-SDI image (screen capture). ................................................................................ 11
Figure 8 aCVi image after transmission through 300m of RG59 cable (screen capture).................... 11
Figure 9 SM06 Schematics - Sheet 1. .................................................................................................... 14
Figure 10 SM06 Schematics - Sheet 2. ...................................................................................................15
Figure 11 SM06 Schematics - Sheet 3. ................................................................................................... 16
Figure 12 SM06 Schematics - Sheet 4. ...................................................................................................17
Figure 13 SM06 Schematics - Sheet 5. .................................................................................................. 18
Figure 14 SM06 Schematics - Sheet 6. .................................................................................................. 19
Figure 15 SM06 Schematics - Sheet 7. ..................................................................................................20
Figure 16 SM06 Schematics - Sheet 8. ...................................................................................................21
Figure 17 SM06 Schematics - Sheet 9. .................................................................................................. 22
Figure 18 SM06 Schematics - Sheet 10.................................................................................................. 23
Figure 19 Power supply specification, Page 1....................................................................................... 25
Figure 20 Power supply specification, Page 2......................................................................................26

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1. Introduction
SM06 is a transmitter module compatible with the aCVi Advanced Composite Video Interface
format. SM06 accepts HD-SDI input format which it converts to analogue aCVi encoded video for
driving both twisted pair and coaxial cable.
aCVi is a method to transmit HD video over long distances of existing coaxial or twisted-pair cable
networks or allow the use of less expensive RG-59/UTP cable in long distance installations.
SM06 supports the following HD standards: 720p-25/30/50/59.94/60Hz, 1080p-24/25/29.97/30Hz
and 1080i-50/59.94/60Hz. Switching between standards is automatic.
Figure 1 SM06 module.

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2. aCVi Overview
The following is a brief overview of the aCVi interface.
The basic concept of the aCVi interface is to build on the proven and reliable transport method of
NTSC. NTSC is capable of transmitting more than 1km across RG-59 cable but the bandwidth is
limited to 5MHz. Because the cable system is a closed system, it is only necessary for the
transmitter and receiver to ‘understand’ each other and we can modify the basic NTSC method to
suit HD transmissions.
According to the SMPTE-296M specification, HD (74.25MHz sampling) video transmission requires
a luma bandwidth of 30MHz and chroma bandwidth of 15MHz. To save on system costs aCVi
supports the 30MHz luma bandwidth but constrains the chroma bandwidth to 7.5MHz (4:1:1
sampling).
The colour difference signals are modulated onto a carrier in quadrature so they effectively use
the same bandwidth: the chroma subcarrier is ~24.75MHz.. The high frequency luma and the
modulated chroma overlap above 12.4MHz but because of the line to line phase relationship of the
chroma, may be separated using a line comb filter (and also because of the use of single chip
image sensors, there is usually little high frequency content to cause image artifacts).
The effective bandwidth of the complete signal is therefore approximately 12.3MHz (chroma
upper sideband + filter roll off) + 24.75MHz or about 37MHz, setting a minimum sampling
frequency of 2 x 37MHz or 74MHz. For convenience we choose 74.25MHz as a sampling frequency
as this is related to the SMPTE272M standard; (see Figure 2).
For transmission over 300m of RG-59 cable we can expect 18dB loss at higher frequencies
(6.2dB/100m @ 50MHz). However the synchronizing signals are at a much lower frequency where
the loss is only about 1-2dB so reliable rastering of the received signal should always be assured.
The peak to peak video level of aCVi is 1.8V (75% colour bars) which maintains compatibility with
any legacy SD equipment on the network and also allows common low-power 5V drivers to be
used. Table 1 lists the currently supported video formats for aCVi.
Format Pixels/line Line
frequency
FSC/FH
ratio
Subcarrier
720p/25Hz 3960 18.75kHz 1320.5 24.759375MHz
720p/30Hz 3300 22.5kHz 1100.5 24.76125MHz
720p/50Hz 1980 37.500kHz 660.5 24.76875MHz
720p/59.94Hz
1
1650 44.955kHz 550.5 24.74775226MHz
720p/60Hz 1650 45.000kHz 550.5 24.7725MHz
1080p/24Hz 2750 27.0kHz 916.5 24.7455MHz
1080p/25Hz 2640 28.125kHz 880.5 24.7640625MHz
1080p/29.97Hz
1
2200 33.716kHz 734.5 24.73089411MHz
1080p/30Hz 2200 33.750kHz 733.5 24.755625MHz
1080i/50Hz 2640 28.125kHz 880.5 24.7640625MHz
1080i/59.94Hz
1
2200 33.716kHz 734.5 24.73089411MHz
1080i/60Hz 2200 33.750kHz 733.5 24.755625MHz
Table 1 aCVi supported video formats.
1Input clock is 148.3516484MHz (else 148.5MHz).

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Figure 2 aCVi Spectrum.

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3. Connecting up the module
The SM06 module is powered by a universal input (90-260VAC) AC-DC adaptor (see Chapter 7 for
the power supply specification). The 5VDC, 12W output of this adaptor should be connected to the
jack input, ‘+5V IN’, of the SM06. Once connected, the yellow LED, ‘FPGA OK’ should light,
indicating the FPGA has been correctly configured and the module is running.
Figure 3 shows the SM06 interconnections.
Figure 3 SM06 Interconnections.
SM06 accepts HD-SDI inputs: switching between the input standards is automatic. If a valid HD-SDI
clock is detected on the input, the ‘SDI LOCK’ LED will light. If the HD-SDI input has valid TRS
timing pulses and is one of the supported aCVi video standards shown in Table 1 the aCVi encoder
will convert the HD-SDI signal to an aCVi output.
SM06 provides simultaneous single ended coaxial and differential twisted-pair (UTP) outputs. The
UTP outputs are connected via a RJ45 style connector. Figure 4 shows the pin assignments for the
connector: aCVi assumes the UTP cable connections are ‘straight’ so both the transmitter and
receiver use pin 1 for the ‘VIDEO+’ (non-inverted) signal, and pin 2 ‘VIDEO-‘ (inverted) signal.

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Figure 4 UTP connector pin assignments.
Should the input to the SM06 be removed or fail, the SM06 will switch to an internal colour bar
generator. The output video standard will be whatever was last detected on the inputs (e.g. if the
last detected input was 1080p/30Hz, the output will be 75% colour bars at 1080p/30Hz standard). If
no valid input has previously been detected, the colour bar output will default to 720p/60Hz. Note
that the colour bar generator will not operate if the input standard is 720p/59.94Hz,
1080p/29.97Hz or 1080i/59.94Hz.
The SM06 will be shipped set for your requested cable choice (i.e. coaxial or UTP) and is indicated
in the serial number label on the bottom of the module (COAX or UTP). For the automatic cable
compensation and data transfer to operate correctly it is necessary to select the cable input to
extract the data from. To do this, remove the end panel with the HD-SDI input and RS232
connector from the SM06 by removing the four screws in the corners of the panel and pulling off
the panel and black bezel. The top panel can then be slid off (see Figure 5).
Figure 5 SM06 Data slicing selection - J9.

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Data from the receiver to the transmitter in aCVi mode is selected by J9. J9 pins 1-2 should be
connected to select the coaxial aCVi input, or J9 pins 2-3 connected for the UTP aCVi input: Pull off
the small pin header and place over the pins you require for your cable type. The panels can then
be refitted.

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4. Automatic Cable length compensation.
aCVi automatically compensates for the cable length. It does this using a special test signal that is
inserted into the aCVi video source signal.
The aCVi transmitter inserts a video test signal into line 9 of the vertical blanking interval (VBI).
This test signal comprises a reference white and black bar and a high frequency sinewave burst
signal. The amplitude difference between the white and black references and the peak to peak
frequency burst are measured by the aCVi receiver (SM08) – the difference indicates the high
frequency loss of the cable.
To compensate for the high frequency loss the aCVi transmitter uses a pre-emphasis filter which
attenuates the lower frequencies with a frequency response characteristic similar to that of the
cable. The aCVi receiver transmits data to the transmitter (on line 8 of VBI) which the transmitter
decodes and uses to control the amount of pre-emphasis. The pre-emphasis is increased until the
high frequency amplitude and the DC amplitude are equal. The transmitter also echoes back the
pre-emphasis value to the receiver to check the transmission is working correctly (on line 7 of the
VBI).
Figure 6 shows lines 7, 8 and 9 of the VBI.
Figure 6 aCVi cable length compensation (lines 7,8 and 9 of the VBI).
Adjusting the pre-emphasis reduces the amplitude of the lower frequencies, which includes the
synchronizing pulses. This is compensated for by an analogue automatic gain control (AGC) at the
receiver. Up to 18dB of analogue gain can be applied on the SM08, allowing full compensation
beyond 300m of RG-59 type coaxial cable.
Beyond this distance, or with cable that attenuates high frequencies more, the SM08 can apply
automatic chroma gain to maintain saturation of the colours. At these extreme distances the luma
frequency response will be reduced below the specification and the transmission may switch to
monochrome.
Figure 7 shows a screen capture of a camera test pattern image (HD-SDI) and Figure 8 shows that
same image after aCVi transmission through 300m of RG-59 coaxial cable.

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Figure 7 Original HD-SDI image (screen capture).
Figure 8 aCVi image after transmission through 300m of RG59 cable (screen capture).

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5. Circuit description
Figures 9-18 show the schematics for the SM06. Below is a brief technical description of the
module.
Sheet 1.
J3 is the 5VDC power input connector to the SM06 module. The 5VDC is protected from reverse
polarity and over-range inputs by D1, D2 and the resettable fuse, F1. The input is then filtered by L1
and C2 to provide the ‘clean’ 5VDC for the analogue output stage and also linearly regulated by U1
and U20 to provide the 3.3VDC and 2.5VDC supply voltages.
Sheet 2.
U2 provides the 1.2VDC for the internal voltage of the FPGA. U3 provides the 2.5VDC for the
analogue PLL circuity of the FPGA and L2 and C25 filter the VCCINT for the FPGA PLL digital blocks.
U12 provides the 1.8V for the HDMI receiver with LC networks providing isolation for the various
individual rails.
Sheet 3.
J1 is the DVI/HDMI input connector. U13 and U14 protect the HDMI receiver from overshoots on
the TMDS signals and U15 does the same for the control signals. The hot plug detect signal,
indicating the presence of a HDMI source, is shown by LED, D5.
Sheet 4.
U16 is the HDMI receiver IC, an Analog Devices ADV7611. The output from this IC is Y,Cb,Cr in 4:2:2
format. In free-run mode this IC provides the fixed 74.25MHz clock. The video input standard is
read from the ADV7611 status registers.
Sheet 5.
U4 is the cable equalizer for the HD-SDI input. U18 deserialises the 1.485GHz input to five LVDS
inputs and a DDR clock. Further demuxing, extraction of the TRS timing signals and the video
formatting is performed by the FPGA. LED D9 lights if U18 is able to lock to incoming HD-SDI signal.
The input standard is also determined by the FPGA.
Sheet 6.
U19 is the FPGA. The FPGA is an Altera EP4CE15 device in a 144 pin 0.5mm TQFP package. The FPGA
contains the PT55 aCVi encoder, a SingMai PT13 control microprocessor, a colour bar generator
and the HD-SDI input decoder.
Sheet 7.
The FPGA is a volatile device and needs configuring on switch on, which it does using U5, a 4Mb
EEPROM. The device is automatically configured on switch on, and successful configuration is
indicated by LED, ‘FPGA OK’. The EEPROM may also be reprogrammed via J4, which is compatible
with the Altera ‘USB-Blaster’ and the Quartus Programmer.
Sheet 8.
X1 is a 27MHz crystal oscillator, and is used to clock the PT13 microprocessor and also as a fixed
time-base to determine the HD-SDI input standard.
U7 is a proprietary copy-protection IC. U7 calculates a checksum from a PT13 generated data
stream, and the calculated checksum from U7 is compared with an FPGA internally generated
checksum. If the two do not match the SM06 module is shut down. This means that even if the bit
stream of the FPGA/EEPROM is captured the PT55 IP core will not run without U7 being fitted.
U17 is an RS232 level translator.

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Sheet 9.
U8 is a 10 bit digital to analogue converter (DAC). The DAC converts the aCVi encoded digital data
to an analogue signal of 0 - 1.0V amplitude. The DAC is clocked at 148.5MHz. U6 provides a ‘clean’
3.3V for the DAC. U21 amplifies the DAC output to provide a 1.8V pk-pk output for driving the
outputs and U9 provides a programmable low pass filter to remove the clock from output video
and reconstitute the waveform.
Sheet 10.
U10-A buffers the coaxial aCVi video while U23 converts the differential aCVi to a single ended
output. J9 selects the input from either the coaxial connector (connect J9 pins 1-2) or the UTP
connector (connect J9 pins 2-3). U10-B filters the input signal and C50 and D3 form a sync tip clamp
to ensure stable DC levels into the data slicer. The data slicer is formed by comparator U10-D and
buffered by U11 before being decoded by the PT55 aCVi encoder IP core.

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Figure 9 SM06 Schematics - Sheet 1.

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Figure 10 SM06 Schematics - Sheet 2.

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Figure 11 SM06 Schematics - Sheet 3.

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Figure 12 SM06 Schematics - Sheet 4.

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Figure 13 SM06 Schematics - Sheet 5.

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Figure 14 SM06 Schematics - Sheet 6.

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Figure 15 SM06 Schematics - Sheet 7.