Sony HCD-MD333 - Hi Fi Cd/minidisc Component User manual

– 1 –
MICROFILM
HCD-MD333
SPECIFICATIONS
SERVICE MANUAL
COMPACT DISC DECK RECEIVER
— Continued on next page —
US Model
Canadian Model
AEP Model
UK Model
E Model
Australian Model
Tourist Model
HCD-MD333 is the amplifier, CD, MD and
tuner section in DHC-MD333.
Model Name Using Similar Mechanism NEW
Mechanism Type CDM13C-5BD19
Base Unit Type BU-5BD19
Optical Pick-upType KSS-213B/K-N
Model Name Using Similar Mechanism NEW
Mechanism Type MDM-3J
Optical Pick-upType KSM-260A-JIN
CD
SECTION
MD
SECTION

HCD-MD333
7-3. SCHEMATIC DIAGRAM – CD SECTION –
• See page 39 forWaveforms.
• See page 81 for IC Block Diagrams.
– 41 – – 42 –
(Page 55)

HCD-MD333
– 45 – – 46 –
7-5. SCHEMATIC DIAGRAM – MD (1/3) SECTION –
• See page 40 forWaveforms.
• See page 51 for PrintedWiring Board.
(Page 47) (Page 47) (Page 48) (Page 48)
• See page 84 for IC Block Diagrams.
• See page 88 for IC Pin Functions.

HCD-MD333
– 47 – – 48 –
7-6. SCHEMATIC DIAGRAM – MD (2/3) SECTION –
• See page 40 forWaveforms.
• See page 51 for Printed Wiring Board.
• See page 85 for IC Block Diagrams.
• See page 89 for IC Pin Functions.
(Page 45) (Page 45) (Page 46) (Page 46)
(Page 49) (Page 49) (Page 50)
(Page 55)

HCD-MD333
– 49 – – 50 –
7-7. SCHEMATIC DIAGRAM – MD (3/3) SECTION –
• See page 40 forWaveforms.
• See page 83 for IC Block Diagrams.
• See page 92 for IC Pin Functions.
(Page 53)
(Page 47) (Page 47) (Page 48)

– 53 –
7-9. SCHEMATIC DIAGRAM – MD SWITCH SECTION –
(Page 50)

HCD-MD333
– 55 – – 56 –
(Page 73) (Page 61) (Page 62)
(Page 57)
(Page 66)
(Page 73)
(Page 47)
(Page
42)
(Page 69)
• See page 86 for IC Block Diagrams.
• See page 94 for IC Pin Functions.
7-11. SCHEMATIC DIAGRAM – MAIN (1/3) SECTION –
• See page 40 forWaveforms.
• See page 59 for PrintedWiring Board.

HCD-MD333
– 57 – – 58 –
(Page 56)
(Page 77)
(Page 75)
7-12. SCHEMATIC DIAGRAM – MAIN (2/3),(3/3) SECTION –
• See page 86 for IC Block Diagrams.

HCD-MD333
– 61 – – 62 –
(Page 69)
(Page 55, 56) (Page 56)
7-14. SCHEMATIC DIAGRAM – AUDIO SECTION –
• See page 87 for IC Block Diagrams.

HCD-MD333
– 65 – – 66 –
7-16. SCHEMATIC DIAGRAM – PANEL SECTION –
(Page 55)
(Page 70)

HCD-MD333
– 69 – – 70 –
7-18. SCHEMATIC DIAGRAM – JACK SECTION –
(Page 61)
(Page 65)
(Page 55) (Page 78)

HCD-MD333
– 73 – – 74 –
7-20. SCHEMATIC DIAGRAM – STTERMINAL/LOADING SECTION – 7-21. PRINTED WIRING BOARD – STTERMINAL/LOADING SECTION –
• See page 31 for Circuit Boards Location.
11
(11)
CN291
S291
(LOAD OUT)
1
2
3
4
5
M904
(LOADING
MOTOR)
M
LOADING BOARD
S292
(LOAD IN)
1-634-461-
(Page 59)
(Page 59)
(Page 55)
(Page 55)

– 75 –
7-22. SCHEMATIC DIAGRAM – TRANS SECTION –
(Page 78)
(Page 58)

HCD-MD333
– 77 – – 78 –
7-24. SCHEMATIC DIAGRAM – POWER AMP SECTION –
(Page 57)
(Page 70)
(Page 75)

7-26. IC BLOCK DIAGRAMS
• CD section
IC101 CXA1782BQ
– 81 –
36
PHD2 PHD1 PHD
33
LD
32
RF M
31
RF O
30
RF I
29
CP
28
CB
27
CC1
26
CC2
25
FOK
24 SENS
23 C. OUT
22 XRST
21 DATA
20 XLT
19 CLK
18 VCC
17 ISET
16 SL 0
15 SL M
14 SL P
13
12
TA O
TA M
11
FSET
10
TG2
9
TGU
8
SRCH
7
FE M
6
FE O
5
FLB
4
FGD
3
FDFCT
2
FEI
1
FEO
48VC
47TDFCT
46TZC
45ATSC
44TEI
43LPFI
42TEO
41VEE
40EI
39E
38F
37FE BIAS
+
+
–
+
+
–
+
–
+
–
+
–
+
–
+
–
+
+
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
–
+
+
–
–
+
+
–
+
–
+
–
+
–
+
–
APC
–
–
–
–
LEVELS
FOK
MIRR
DFCT
RF IV AMP2
RF IV AMP1
FE AMP
F IV AMP
E IV AMP
TE AMP
FZC COMP
BAL1 BAL2 BAL3
TOG1 TOG2 TOG3
TTL
IIL
IIL
TTL
TTL
IIL
• IIL DATA RESISTOR • INPUT SHIFT RESISTOR
• ADDRESS DECODER
• OUTPUT DECODER
HPF COMP LPF COMP
TZC COMP
DFCT
DFCT
TM1
FS4
ATSC
• WINDOW COMP
• FCS PHASE
COMPENSATION
• TRACKING
• PHASE
COMPENSATION
• ISET
FS1
FS2
TM4
TM5
TM6
TM3
TM7
TG2
• F SET
TG1
TM2
+
–
TOG1-3 FS1-4 TG1-2 TM1-7 PS1-4
BAL1-3
35 34

– 82 –
IC102 BA6397FP
1 2 3 4 7 8 9
10 11 12 13 14
28 27 26 24 22 21 20 19 18 17
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT DOWN
REGULATOR DRIVER MUTE
LEVEL
SHIFT
DRIVE
BUFFER DRIVE BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
DRIVE
BUFFER DRIVE
BUFFER
15 16 23 25
5 6
OUT1A OUT1B
IN1A IN1B
TR-B
REG 0
XRST
GND
IN2A IN2B
OUT2A OUT2B
GND
OP-OUT
GND OUT4
A
OUT4B IN4A IN4B VC V
CC
V CC V CC
V
CC
IN3B IN3A OUT3B OUT3
A
OP+ OP–
IC103 CXD2507AQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32313029282726252423222120
52535455565758596061626364
19
FOK
MON
MDP
MDS
LOCK
TEST
FILO
FILI
PCO
VSS
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
WDCK
DATA
XRST
SENS
MUTE
SQCK
SQSO
EXCK
SBSO
SCOR
VSS
WFCK
EMPH
DOUT
C4M
FSTT
XTSL
XTAO
XTAI
MNTO
SERVO AUTO
SEQUENCER
CPU
INTERFACE DIGITAL
CLV
SUB CODE
PROCESSOR
EFM
DEMODULATOR
DIGITAL
PLL
ASYMMETRY
CORRECTOR D/A
INTERFACE
ERROR
CORRECTOR
16K
RAM
DIGITAL
OUT
CLOCK
GENERATOR
LRCK
PCMD
BCLK
GTOP
XUGF
XPCK
VDD
GFS
RFCK
CZPO
XROF
MNT3 MNT1
XLON SPOD SPOC SPOB SPOA CLKO VDD
XLTO DATO CNIN SEIN CLOK XLAT
3
5
14
4
5
3
6

– 83 –
– MD Section –
IC104 PCM1710U-B
IC153 LB1830-S-TE-L IC201 AK4520A-VF-E2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
25
24
23
22
21
20
19
18
17
16
15
28
INPUT
INTERFACE DIGITAL
FILTER
NOISE
SHAPER
5-LEVEL DAC
RIGHT
LOW-PASS FILTER
RIGHT
3-STAGE AMP
RIGHT
LOW-PASS FILTER
LEFT
3-STAGE AMP
LEFT
5-LEVEL DAC
LEFT
MODE
CONTROL
TIMING
CONTROL
LRCIN
DIN
BCKIN
CLKO
XTI
XTO
DGND
VDD
VCC2R
GND2R
EXT1R
EXT2R
VOUTR
GND1
ML/DSD
MC/DM2
MD/DM1
MUTE
MODE
CKSL
DGND
VDD
VCC2L
VCC1
GND2L
EXT1L
EXT2L
VOUTL
1
LOGIC
PREDRIVER
VREF
2 3 45
10 9 8 7 6
IN2 IN1 VM VREF VCONT
VCC OUT2 GND OUT1 VS
∆Σ
MODULATOR
8×
INTERPOLATOR
COMMON
VOLTAGE
CLOCK
DIVIDER
SERIAL I/O
INTERFACE
LPF ∆Σ
MODULATOR
∆Σ
MODULATOR
∆Σ
MODULATOR
8×
INTERPOLATOR
DECIMATION
FILTER
DECIMATION
FILTER
LPF
16 15171819202122232425262728
12 3 45 6 7 8 9 10 14131211
VCOM AOUTR AOUTL CMODE PWAD PWDA DGND VD TST1 TST2 TST3 DEM1 DEM0 MCLK
SDTO
SDTI
SCLK
LRCK
DIF1 DIF0
AGND
VA
AINL– AINL+
AINR–
VREFH
AINR+
VREFL

– 84 –
IC101 CXA2523AR
–1
–2
+
–
IVR BB
+
–
IVR AA
+
–
IVR CC
+
–
IVR DD
+
–
IVR +
–
EE EE'
EFB TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36 BOTM
35 ABCD
34 FE
33 AUX
32 ADFG
31 ADAGC
30 ADIN
29 ADFM
28 SE
27 CSLED
26 TE
25 WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12APCREF
11APC
10PD
9F
8E
7D
6C
5B
4A
3VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+ –
+ –
AUXSW
COMMAND
+
–
IVR
GSW IV
+
–
FF
FBAL
FF'
TG
SEA
–
+
–
+
–1
–2
TG
TEA
WBL
3T
EQ
–
–
+
+
+
+
–
–
+
+
+
+
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
–
+
CVB
+ –
RFA1
–
–
–
–
1
2
–
–
–
1
2
GRVA
CFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC EQ
EQ
DET
P-P
WBL
3T WBL TEMP
PBH
–
+
USROP
+
–USRC
3T
BPF3T
PEAK3T
1I
2J

– 85 –
IC121 CXD2652AR
100 99 98 97 96 95 94 93
EFMO DVSS TEST3 TEST2 TEST1 TEST0 SPFD SPRD
92
SFDR
91
SRDR
90
FS4
89
KRDR
88
FFDR
87
DVDD
86
TFDR
85
TRDR
84
LDDR
83
APCREF
82
DTRF
81
CKRF
80
XLRF
79
F0CNT
78
ADFG
77
APC
76
DCHG
75 AUX2
74 TE
73 SE
72 AVSS
71 ADRB
70 ADRT
69 AVDD
68 ADIO
61 CLTV
60 FILO
59 FILI
58 PCO
57 PDO
55 RFI
56 AVSS
54 BIAS
53 AVDD
52 ASYI
51 ASYO
67 VC
66 AUX1
65 FE
64 ABCD
63 BOTM
62 PEAK
50
MVCI
49
D3
48
D2
47
D0
46
D1
45
XWE
44
XRAS
43
A09
42
XCAS
41
XOE
40
DVSS
39
A11
38
A08
37
A07
36
A06
35
A05
34
A04
33
A10
32
A00
31
A01
30
A02
29
A03
28
DVDD
26
XBCK
27
FS256
25
LRCK
24
DADT
23
ADDT
22
DOUT
21
DIN
20
RVSS
19
RVDD
18
XTSL
17
OSCO
16
OSCI
15
TX
14
XINT
13
RECP
12
DQSY
11
SQSY
10
XRST
9
SENS
8
SRDT
7
XLAT
6
SCLK
5
SWDT
4
MNT3
3
MNT2
2
MNT1
1
MNT0
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
SPINDLE
SERVO
EACH
BLOCK
EACH
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
A/D
CONVERTER
ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
APC
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
DRAM
ADIP
DEMODULATOR/
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3
IC152 BH6511FS-E2
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA– CAPA+ IN2R IN2F VM2 OUT2F PGND2 OUT2R VM12 OUT1R PGND1 OUT1F VM1 IN1F IN1R VDD
CHARGE
PUMP.
OSC
INTERFACE AMP
INTERFACE AMP
AMP INTERFACE
PREDRIVEPREDRIVE
PREDRIVEPREDRIVE
AMP
INTERFACE
AMPAMPAMP
VDD
PSB
AMP

– 86 –
– MAIN Section –
IC570 LA5620 IC603 M62016L
12 3 45
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND INT RESET CD VCC
COM
COM
IC801 LB1641
12 3 45 6 7 8 9 10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1 VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D O.C.P
FWD/REV/STOP
CONTROL LOGIC
1–
+
12
VREF
DELAY
CIRCUIT
3.3V
PH5
STBY
VCC
ANA5
SYS3.3
BACK
AC
CD1
P. DOWN
GND
CD2
S. RESET
–
+
–
+
–
+
–
+
–
+
2
3
4
5
6
7
8
9
10
11 DELAY
CIRCUIT