Spectrum Monaco Quad 'C6x VME64 Use and care manual

Monaco
Quad 'C6x VME64 Board
Technical Reference
Document Number 500-00191
Revision 2.00
September 1999

ii Part Number 500-00191
Revision 2.00
Copyright © 1999 Spectrum Signal Processing Inc.
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Spectrum Signal Processing reserves the right to change any of the information contained herein without notice.

Spectrum Signal Processing Monaco Technical Reference
Preface
Part Number 500-00191 iii
Revision 2.00
Preface
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Monaco Technical Reference Spectrum Signal Processing
Preface
iv Part Number 500-00191
Revision 2.00
Rev. Date Changes Section
2.00 Sept 1999 Updated for TMS320C6201B and TMS320C6701
DSPs n.a.
Document
Change
History

Spectrum Signal Processing Monaco Technical Reference
Table of Contents
Part Number 500-00191 v
Revision 2.00
Table of Contents
1 Introduction..............................................................................................................................1
1.1. Features....................................................................................................................................1
1.2. Interfaces ..................................................................................................................................2
1.2.1. VME.............................................................................................................................2
1.2.2. PMC ............................................................................................................................2
1.2.3. PEM.............................................................................................................................2
1.2.4. Serial Ports..................................................................................................................2
1.2.5. JTAG...........................................................................................................................2
1.3. Reference Documents..............................................................................................................3
1.4. General Bus Architecture..........................................................................................................4
1.5. On-Board Power Supply ...........................................................................................................4
1.6. Reset Conditions.......................................................................................................................5
1.6.1. VME SYSRESET ........................................................................................................5
1.6.2. VME A24 Slave Interface Reset..................................................................................5
1.6.3. JTAG Reset.................................................................................................................5
1.7. Board Layout.............................................................................................................................6
1.8. Jumper settings.........................................................................................................................7
2 Processor Nodes.....................................................................................................................9
2.1. Processor Memory Configuration ...........................................................................................11
2.1.1. Internal Memory ........................................................................................................11
2.1.2. External Memory.......................................................................................................11
2.2. Synchronous Burst SRAM......................................................................................................15
2.3. Synchronous DRAM ...............................................................................................................15
2.4. Processor Expansion Module.................................................................................................15
2.5. Host Port.................................................................................................................................15
2.6. Interrupt Lines.........................................................................................................................15
2.7. Processor Booting...................................................................................................................16
2.8. Serial Port Routing..................................................................................................................17
3 Global Shared Bus................................................................................................................19
3.1. Memory...................................................................................................................................19
3.2. Arbitration................................................................................................................................19
3.2.1. Single Cycle Bus Access ..........................................................................................20
3.2.2. Burst Cycle Bus Access............................................................................................20

Monaco Technical Reference Spectrum Signal Processing
Table of Contents
vi Part Number 500-00191
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3.2.3. Locked Cycles...........................................................................................................21
4 VME64 Bus Interface............................................................................................................23
4.1. VME Operation........................................................................................................................23
4.2. SCV64 Primary Slave A32/A24 Interface................................................................................23
4.3. A24 Secondary Slave Interface...............................................................................................24
4.4. Master A32/A24/A16 SCV64 Interface....................................................................................27
5 DSP~LINK3 Interface............................................................................................................29
5.1. DSP~LINK3 Data Transfer Operating Modes.........................................................................29
5.2. Address Strobe Control Mode.................................................................................................30
5.3. Interface Signals .....................................................................................................................31
5.4. DSP~LINK3 Reset ..................................................................................................................31
6 PCI Interface.........................................................................................................................33
6.1. Hurricane Configuration..........................................................................................................33
6.2. Hurricane Implementation.......................................................................................................36
7 JTAG Debugging...................................................................................................................37
8 Interrupt Handling..................................................................................................................39
8.1. Overview.................................................................................................................................39
8.2. DSP~LINK3 Interrupts to Node A ...........................................................................................40
8.3. PEM Interrupts........................................................................................................................41
8.4. PCI Bus Interrupts...................................................................................................................41
8.5. Hurricane Interrupt..................................................................................................................41
8.6. SCV64 Interrupt ......................................................................................................................41
8.7. Bus Error Interrupts.................................................................................................................43
8.8. Inter-processor Interrupts........................................................................................................44
8.9. VME Host Interrupts To Any Node..........................................................................................44
9 Registers...............................................................................................................................45
VPAGE Register..................................................................................................................46
VSTATUS Register .............................................................................................................47
VINTA Register ...................................................................................................................49
VINTB Register ...................................................................................................................50
VINTC Register...................................................................................................................51
VINTD Register...................................................................................................................52
KIPL Enable Register.........................................................................................................53

Spectrum Signal Processing Monaco Technical Reference
Table of Contents
Part Number 500-00191 vii
Revision 2.00
DSP~LINK3 Register ..........................................................................................................54
ID Register ..........................................................................................................................55
VME A24 Status Register....................................................................................................56
VME A24 Control Register..................................................................................................57
10 Specifications......................................................................................................................59
10.1. Board Identification ...............................................................................................................59
10.2. General .................................................................................................................................60
10.3. Performance and Data Throughput ......................................................................................61
11 Connector Pinouts...............................................................................................................63
11.1. VME Connectors...................................................................................................................64
11.2. PMC Connectors...................................................................................................................67
11.3. PEM Connectors...................................................................................................................71
11.4. JTAG Connectors .................................................................................................................73

Monaco Technical Reference Spectrum Signal Processing
Table of Contents
viii Part Number 500-00191
Revision 2.00

Spectrum Signal Processing Monaco Technical Reference
Table of Contents
Part Number 500-00191 ix
Revision 2.00
List of Figures
Figure 1 Block Diagram...................................................................................................................4
Figure 2 Board Layout.....................................................................................................................6
Figure 3 Processor Node Block Diagram......................................................................................10
Figure 4 DSP Memory Map...........................................................................................................13
Figure 5 DSP Memory Map for External-Memory Space CE1......................................................14
Figure 6 Serial Port Routing ..........................................................................................................17
Figure 7 Global Bus Arbitration .....................................................................................................20
Figure 8 Primary VME A24/A32 Memory Map ..............................................................................24
Figure 9 A24 Secondary Interface Memory Map...........................................................................25
Figure 10 PCI Memory Map ..........................................................................................................33
Figure 11 JTAG Chain...................................................................................................................37
Figure 12 Interrupt Routing............................................................................................................40
Figure 13 Connector Layout..........................................................................................................63

Monaco Technical Reference Spectrum Signal Processing
Table of Contents
xPart Number 500-00191
Revision 2.00