ST STM32 Nucleo Installation and operating instructions

March 2022 AN4899 Rev 3 1/31
1
AN4899
Application note
STM32 microcontroller GPIO hardware settings
and low-power consumption
Introduction
The STM32 microcontroller general-purpose input/output pin (GPIO) provides many ways to
interface with external circuits within an application framework. This application note
provides basic information about GPIO configurations as well as guidelines for hardware
and software developers to optimize the power performance of their STM32 32-bit Arm®
Cortex®MCUs using the GPIO pin.
This application note must be used in conjunction with the related STM32 reference manual
and datasheet available at www.st.com.
www.st.com

Contents AN4899
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Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Register abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 GPIO abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 GPIO equivalent schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 GPIO modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1 Input mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.2 Output mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.4 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 GPIO electrical characteristics and definitions . . . . . . . . . . . . . . . . . . 13
5.1 GPIO general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Pad leakage current (Ilkg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Injected current (IINJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 GPIO current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.4 Voltage output and current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.5 Pull-up calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Three-volt tolerant and five-volt tolerant . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 Three-volt tolerant GPIO (TT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.2 Five-volt tolerant GPIO (FT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Five-volt tolerant application examples . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.1 White LED drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.2 Triac drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.3 I2C application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.4 UART application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3.5 USB VBUS example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3.6 I/O usage for the five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . 21

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6 GPIO hardware guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Avoid floating unused pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Cross-voltage domains leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 Voltage protection when no VDD is supplied . . . . . . . . . . . . . . . . . . . . . . 24
6.4 Open-drain output with no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Using the MCO clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.6 Debug pins have PU or PD by default . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7 NRST pin cannot be used as enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.8 VBAT GPIO has limited current strength . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9 BOOT0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 GPIO software guidelines for power optimization . . . . . . . . . . . . . . . . 27
7.1 Configure unused GPIO input as analog input . . . . . . . . . . . . . . . . . . . . . 27
7.2 Adapt GPIO speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3 Disable GPIO register clock when not in use . . . . . . . . . . . . . . . . . . . . . . 27
7.4 Configure GPIO when entering low-power modes . . . . . . . . . . . . . . . . . . 27
7.5 Shutdown exit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 GPIO selection guide and configuration . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

List of tables AN4899
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List of tables
Table 1. List of GPIO structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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AN4899 List of figures
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List of figures
Figure 1. Three-volt compliant GPIO structure (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. Three-volt or five-volt tolerant GPIO structure (TT or FT). . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Output buffer and current flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Logical level compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. STM32 current flow according to output voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Example of white LED drive connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Example of triac drive connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Example of I2C connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Example of 5 V to 3.3 V power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Example of UART connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Example of USB VBUS connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Example of VBUS to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Example of five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Workaround example for five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Multi voltage leakage example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Voltage protection when VDD is not supplied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Open-drain output with no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. GPIO configuration flowchart (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. GPIO configuration flowchart (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

General information AN4899
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1 General information
STM32 microcontrollers are based on the Arm®(a) Cortex® processor.
2 Documentation conventions
2.1 Glossary
This section defines the main acronyms and abbreviations used in this document.
AMR: absolute maximum rating
GPIO: general-purpose input output
GP: general-purpose
PP: push-pull
PU: pull-up
PD: pull-down
OD: open-drain
AF: alternate function
VIH: the minimum voltage level that is interpreted as a logical 1 by a digital input
VIL: the maximum voltage level that is interpreted as a logical 0 by a digital input
VOH: the guaranteed minimum voltage level that is provided by a digital output set to
the logical 1 value
VOL: the guaranteed maximum voltage level that is provided by a digital output set to
the logical 0 value
VDD: external power supply for the I/Os
VDDIO2: external power supply for the I/Os, independent from the VDD voltage
VDDA: external power supply for analog
VSS: ground
IIH: input current when input is 1
IIL: input current when input is 0
IOH: output current when output is 1
IOL: output current when output is 0
Ilkg: leakage current
IINJ: injected current
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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2.2 Register abbreviations
The following abbreviations are used in register descriptions (x = A to H):
GPIOx_MODER: GPIO port mode register
GPIOx_OTYPER: GPIO output type register
GPIOx_OSPEEDR: GPIO output speed register
GPIOx_PUPDR: GPIO port pull-up / pull-down register
GPIOx_IDR: GPIO port input data register
GPIOx_ODR: GPIO port output data register
GPIOx_BSRR: GPIO port bit set / reset register
GPIOx_LCKR: GPIO port configuration lock register
GPIOx_AFRL: GPIO alternate function low register
GPIOx_AFRH: GPIO alternate function high register
GPIOx_ASCR: GPIO port analog switch control register
3 GPIO main features
STM32 GPIO exhibits the following features:
•Output states: push-pull, or open drain + pull-up / pull-down according to
GPIOx_MODER, GPIOx_OTYPER, and GPIOx_PUPDR registers settings
•Output data from output data register GPIOx_ODR or peripheral (alternate function
output)
•Speed selection for each I/O (GPIOx_OSPEEDR)
•Input states: floating, pull-up / pull-down, analog according to GPIOx_MODER,
GPIOx_PUPDR and GPIOx_ASCR registers settings
•Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
•Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
•Analog function selection registers (GPIOx_MODER and GPIOx_ASCR)
•Alternate function selection registers (GPIOx_MODER, GPIOx_AFRL, and
GPIOx_AFRH)
•Fast toggle capable of changing every two clock cycles
•Highly flexible pin multiplexing allowing the use of I/O pins as GPIO or as one of
several peripheral functions

GPIO functional description AN4899
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4 GPIO functional description
STM32 GPIO can be used in a variety of configurations. Each GPIO pin can be individually
configured by software in any of the following modes:
•Input floating
•Input pull-up
•Input-pull-down
•Analog
•Output open-drain with pull-up or pull-down capability
•Output push-pull with pull-up or pull-down capability
•Alternate function push-pull with pull-up or pull-down capability
•Alternate function open-drain with pull-up or pull-down capability
4.1 GPIO abbreviations
Several GPIO structures are available across the range of STM32 devices. Each structure
is associated with a list of options.
Table 1 summarizes the GPIO definitions and abbreviations applicable to STM32 products
As an example, the following description refers to a GPIO in a STM32 datasheet:
PB1 I/O FT means:
– pin PB1 I/O: port B bit 1 input / output
– FT: five-volt tolerant
Before starting a board design, it is important to refer to the datasheet of the STM32 product
or to the STM32CubeMX tool to check for GPIO availability in coherence with the target
application.
Refer to the section about software development tools at www.st.com/stm32.
Table 1. List of GPIO structures
Name Abbreviation Definition
Pin Type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT(1) Five-volt tolerant I/O pin
TT(1) Three-volt tolerant I/O pin
TC Three-volt capable I/O pin (Standard 3.3 V I/O)
B Dedicated boot pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Pin functions
Alternate functions Functions selected through GPIOx_AFR registers
Additional functions Functions directly selected and enabled through peripheral registers
1. FT and TT I/Os have options depending on the device. The user must refer to the datasheet for their definitions.

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4.2 GPIO equivalent schematics
STM32 products integrate three main GPIO basic structures:
•Three-volt compliant (abbreviated as TC).
The equivalent GPIO diagram structure is given in Figure 1.
•Three-volt tolerant (abbreviated as TT).
•Five-volt tolerant (abbreviated as FT)
The equivalent GPIO diagram structure for TT or FT is given in Figure 2.
Note: In Figure 1 and Figure 2, the analog switch in the dotted square is optional. Its presence
depends on the STM32 product considered. The analog switch is controlled by enabling
analog peripheral on the given pin (not by setting the GPIO in the analog mode). Refer to
the product datasheet for details.
In Figure 1 and Figure 2, the VDD supply may refer to VDD or VDDIO2 according to the
STM32 product considered. Refer to the product datasheet for details.
Figure 1. Three-volt compliant GPIO structure (TC)
Note: The parasitic diode in the analog domain is connected to VDDA and cannot be used as a
protection diode.
The voltage level called VDD_FT in some datasheets and reference manuals is inside the
ESD protection block.
MSv46872V1
ESD
protection
Output data
register
VDD
I/O pin
VSS
VDD
Output
control
PMOS
NMOS
Analog
option
Input buffer
Ouput buffer
on/off
on/off
VSS
Alternate function output
Input data
register
Alternate function input
VSS
Analog switch
Analog IP
Analog
VSS
VDD
Digital
VDDA
Parasitic diode
and resistor
RPU
RPD

GPIO functional description AN4899
10/31 AN4899 Rev 3
Figure 2. Three-volt or five-volt tolerant GPIO structure (TT or FT)
Note: The parasitic diode in the analog domain is connected to VDDA and cannot be used as a
protection diode.
The voltage level called VDD_FT in some datasheets and reference manuals is inside the
ESD protection block.
When the analog option is selected (by enabling analog peripheral on the given pin), the
FT I/O is not five-volt tolerant anymore since the pin is supplied with VDDA.
Caution: A TT or FT GPIO pin has no internal protection diode connected to supply (VDD). There is
no physical limitation against over-voltage. Therefore, for applications requiring a limited
voltage threshold, it is recommended to connect an external diode to VDD.
4.3 GPIO modes description
This section describes the possible GPIO pin configurations available in STM32 devices.
4.3.1 Input mode configuration
When a STM32 device I/O pin is configured as input, one of three options must be selected:
•Input with internal pull-up. Pull-up resistors are used in STM32 devices to ensure a
well-defined logical level in case of floating input signal. Depending on application
requirements, an external pull-up can be used instead.
•Input with internal pull-down. Pull-down resistors are used in STM32 devices to ensure
a well-defined logical level in case of floating input signal. Depending on application
requirements, an external pull-down can be used instead.
•Floating input. Signal level follows the external signal. When no external signal is
present, the Schmitt trigger randomly toggles between the logical levels induced by the
external noise. This increases the overall consumption.
MSv46873V1
ESD
protection
Output data
register
I/O pin
VSS
VDD
Output
control
PMOS
NMOS
Analog
option
Input buffer
Ouput buffer
on/off
on/off
VSS
Alternate function output
Input data
register
Alternate function input
VSS
Analog switch
Analog IP
Analog
VSS
VDD
Digital
VDDA
Parasitic diode
and resistor
RPU
RPD

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Programmed as input, an I/O port exhibits the following characteristics:
•The output buffer is disabled
•The Schmitt trigger input is activated
•The pull-up or pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•The data present on the I/O pin is sampled into the input data register at each AHB
clock cycle
•The I/O state is obtained by reading the GPIOx_IDR input data register
4.3.2 Output mode configuration
When a STM32 device I/O pin is configured as output, one of two options must be selected:
•Push-pull output mode:
The push-pull output actually uses two transistors: one PMOS and one NMOS. Each
transistor is ON to drive the output to the appropriate level:
– The top transistor (PMOS) is ON when the output has to drive HIGH state
– The bottom transistor (NMOS) is ON when the output has to drive a LOW state
The control of the two transistors is done through the GPIO port output type
register (GPIOx_OTYPER).
Writing the related bit of the output register (GPIOx_ODR) to 0 activates the
NMOS transistor to force the I/O pin to ground.
Writing the related bit of the output register (GPIOx_ODR) to 1 activates the
PMOS transistor to force the I/O pin to VDD.
•Open-drain output mode:
Open-drain output mode does not use the PMOS transistor and a pull-up resistor is
required.
When the output has to go high, the NMOS transistor must be turned off, pulling the
line high only by the pull-up resistor. This pull-up resistor could be internal with a typical
value of 40 kOhm and activated through GPIO port pull-up / pull-down register
(GPIOx_PUPDR).
Note: It is important to note that it is not possible to activate pull-up and pull-down at the same
time on the same I/O pin.
It is also possible to use an external pull-up or pull-down resistor instead of the internal
resistor. In this case, the value must be adapted to be compliant with the GPIO output
voltage and current characteristics.
Programmed as output, an I/O port exhibits the following characteristics:
•The output buffer can be configured in open-drain or push-pull mode
•The Schmitt trigger input is activated
•Theinternalpull-upandpull-downresistorsareactivateddependingonthevalue inthe
GPIOx_PUPDR register.
•The written value into the output data register GPIOx_ODR sets the I/O pin state
•The written data on GPIOx_ODR can be read from GPIOx_IDR register that is updated
every AHB clock cycle
Open-drain output is often used to control devices which operate at a different voltage
supply than the STM32. Open-drain mode is also used to drive one or several I2C devices
when specific pull-up resistors are required.

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4.3.3 Alternate functions
On some STM32 GPIO pins, the user has the possibility to select alternate functions
inputs / outputs. Each pin is multiplexed with up to sixteen peripheral functions such as
communication interfaces (SPI, UART, I2C, USB, CAN, LCD and others), timers, debug
interface, and others.
The alternate function of the selected pin is configured through two registers:
•GPIOx_AFRL (for pin 0 to 7)
•GPIOx_AFRH (for pin 8 to 15)
To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.
When the I/O port is programmed as alternate function mode:
•The output buffer can be configured in open-drain or push-pull mode
•The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
•The Schmitt trigger input is activated
•The pull-up and pull-down resistors activations depend on the value in the register
GPIOx_PUPDR
The data present on the I/O pin are sampled into the input data register at each AHB clock
cycle.
A read access to the input data register provides the I/O state.
Alternate functions details are provided in the datasheet and the reference manual of the
product.
4.3.4 Analog configuration
Few STM32 GPIO pins can be configured in analog mode which allows the use of ADC,
DAC, OPAMP, and COMP internal peripherals. To use a GPIO pin in analog mode, the
following register are considered:
•- GPIOx_MODER to select the mode (Input, Output, Alternate, Analog)
•- GPIOx_ASCR to select the required function ADC, DAC, OPAMP, or COMP
When the I/O port is programmed in an analog configuration:
•The output buffer is disabled
•The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin.The output of the Schmitt trigger is forced to a constant value (0).
•The pull-up and pull-down resistors are disabled by hardware
Read access to the input data register gets the value 0.
For details concerning ADC, DAC, OPAMP and COMP function and programming, refer to
the datasheet and reference manual of the product.
The analog switch itself is not closed. The analog switch is closed only when analog
peripheral is selected (or enabled) on the given pin.

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5 GPIO electrical characteristics and definitions
This chapter defines and explains some of the electrical parameters in STM32 datasheets.
5.1 GPIO general information
The following sections detail some of the electrical parameters in the datasheets as a
function of their use from an application point of view.
AMR (absolute maximum ratings)
The absolute maximum ratings represent the values of voltages, current, temperatures,
power dissipations, and others which must never be exceeded. Exceeding these values can
lead to the deterioration or the destruction of the IC.
Operating conditions
The operating conditions represent the range of guaranteed values within which the IC
operates in proper conditions.
5.1.1 Pad leakage current (Ilkg)
The pad leakage current is the current which is sourced from the input signal by the I/O pin
when it is configured in input mode. The value of the leakage current depends on the I/O
structure and on the voltage range of the VIN signal applied to the I/O pin.
Leakage currents are product dependent. Refer to the datasheets for their values.
5.1.2 Injected current (IINJ)
Injection current is the current that is being forced into a pin by an input voltage (VIN) higher than the
positive supply (VDD + ∆V) or lower than ground (VSS).
Injection current above the given specifications causes a current flow inside the device and
affects its reliability. Even a very small current exceeding the specified limit is not allowed.
STM32 datasheets specify injected current and VIN.
Negative-injection current is the current induced when VIN < VSS. The maximum negative
injected current is -5 mA and the minimum VIN voltage level acceptable on the GPIO is
-0.3 V for TT and FT GPIO.
Positive-injection current is the current induced when VIN > VDD. For STM32 devices, the
maximum positive-injection current on TT and FT GPIO is defined as N/A or 0 mA.
•N/A means that, as long as the input voltage is within the AMR range, and due to the
internal design of the GPIO, no current injection occurs. As a result, no corruption of
the GPIO and STM32 device operation is observed in such a case.
•0 mA means that current injection can damage the GPIO and induce STM32
malfunction.
Warning: positive current injection is prohibited for a TT or FT GPIO
defined as 0 mA

GPIO electrical characteristics and definitions AN4899
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The maximum VIN voltage is equal to VDD + 0.3 V for TT GPIO. For FT GPIO, the VIN
maximum voltage is the minimum value among VDD, VDDA, VDDIO2, VDDUSB, and VLCD)
augmented of 3.6 V with a maximum VIN value limited to 5.5 V.
Note: There is no injected current while -0.3 V < VIN < VINmax.
The total injected current is limited, typically to 25 mA per device. Refer to the device
datasheet for the value of the exact limitation. This restricts the number of pins on which
current can be injected.
5.1.3 GPIO current consumption
There are two types of I/O pin current consumption in STM32 devices:
1. The static current consumption which is mainly due to pull-up resistors when I/O pin is
used as input and held low or when I/O pin is used as output with external pull-down or
external load.
2. The dynamic current consumption which is the current from the I/O supply voltage used
by the I/O pin circuitry and capacitive load when the I/O pin switches.
The dynamic current consumption is given by Equation 1.
Equation 1 ISW = CLx VDD x FSW
–I
SW is the current sunk by a switching I/O to charge / discharge the capacitive load
–C
Lis the total load capacitance seen by the I/O pin
CLis the sum of internal, external, PCB, and package capacitances
–V
DD is the I/O supply voltage
–F
SW is the I/O switching frequency
Note: The GPIO speed has no impact on the dynamic current consumption.
5.1.4 Voltage output and current drive
All STM32 GPIOs are CMOS and TTL compliant and are able to source or sink current from
external pin. Figure 3 shows the current flow according to the output level selected. IOH is
sourced current when GPIO output is in High state. IOL is sunk current when GPIO output is
in Low state. The maximum output current which can be sunk or sourced by one GPIO or
from the power supplies is limited to preserve the GPIO from as well as that the sum of the
current sourced or sunk by all GPIO and cannot exceed the AMR values fixed inside the
product datasheet. Following the current drive limitations, the number of GPIO which can
drive current has to be limited consequently.
For more details, see the values of IVDD, IVSS, IIO and ∑IVDD, ∑IVSS, and ∑IIO parameters
allowed into the AMR current characteristics table available in the datasheet.

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AN4899 GPIO electrical characteristics and definitions
30
Figure 3. Output buffer and current flow
In case of communication exchange, STM32 output signals must be compatible with the
VIL / VIH of the receptor device and STM32 inputs must be compliant with the VOL / VOH of
the transmitter device as shown in Figure 4.
Figure 4. Logical level compatibility
For the CMOS technology, the input threshold voltages are relative to VDD as follows:
VIHmin ~ 2 / 3 VDD and VILmax ~ 1 / 3 VDD.
For the TTL technology, the levels are fixed and equal to VIHmin = 2V and VILmax = 0.8 V.
The VOH ,VOL, VIH, VIL levels and the values of output-driving currents are part of the
general input/output characteristics given in the STM32 datasheet.
MSv46874V2
Ouput
control
ON
OFF
ON
OFF
VDD
GND
DATA FROM
CORE
EXTERNAL
PAD
‘1’
‘0’
IOL
IOH
MSv46875V2
High level = 1
Intermediate region
Low level = 0
Noise margin
Noise margin
Output Input
0 V 0 V
Low level = 0
Intermediate region
High level = 1
VOHmin
VOLmax
VIHmin
VILmax
VDDIO VDDIO

GPIO electrical characteristics and definitions AN4899
16/31 AN4899 Rev 3
5.1.5 Pull-up calculation
Each STM32 GPIO offers the possibility to select internal pull-up and pull-down (typical
value = 40 kOhm). Some STM32 applications may require to use an external pull-up
resistor. This section presents output and input levels compatibility and the way to calculate
the appropriate pull-up resistor when the STM32 GPIO open-drain output is connected to an
external device.
Figure 5. STM32 current flow according to output voltage level
The schematics in Figure 5 shows the current flows (gray arrows) and the associated
voltages needed to calculate the RPU pull-up resistor.
The value of RPU is maximum when GPIO output equals 1. This means that the NMOS
transistor is OFF; the VOHmin voltage is used for the calculation.
The value of RPU is minimum when GPIO output equals 0. This means that the NMOS
transistor is ON; the VOLmax voltage is used for the calculation.
(VDDmax - VOLmax) / (IOL + Ilkg ) < RPU < (VDDmin - VOHmin) / (IIH + Ilkg)
Pull-up calculation for the I2C bus:
Pull-up calculation in case of I2C bus is different because the I2C mode must be taken into
account. This calculation depends on the I2C mode (Standard Mode, Fast Mode, Fast mode
Plus), on the VDD of the device, and on the bus capacitance.
A low pull-up resistor value prevents the dedicated STM32 GPIO I2C pins to generate a low
level on the bus. The minimum value RPUmin is defined as a function of VDD, VOL, and IOL
according to Equation 2.
Equation 2 RPUmin = (VDD - VOLmax) / IOL
The maximum pull-up resistance RPUmax is limited by the total capacitance of the bus
including the capacitance of the wire, connections and pins (Cb), and the maximum rise time
(trmax) of the SDA and SCL signals. Refer to the datasheet and to the I2C bus specification
for more details.
MSv46876V1
STM32
VDD
RPU
Ip
Ilkg IOL
VOLmax
VILmax
GPIO = 0
(ON)
input
External
device
GPIO output = 0
STM32
VDD
RPU
Ip
IIHmax Ilkg
VOHmin
VIHmin
GPIO = 1
(OFF)
input
External
device
GPIO output = 1

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AN4899 GPIO electrical characteristics and definitions
30
If the pull-up resistor is too high, the I2C line does not rise to a logical high before being
pulled low. The maximum value RPUmax is calculated according to Equation 3.
Equation 3 RPUmax = trmax / (0.8473 x Cb)
The rationale for Equation 3 is described in the following steps:
1. Voltage amplitude over time is RC time-constant dependent according to
V(t) = VDD x (1 - e(-t / RC))
2. With VIH = 0.3 x VDD, the time t1at which VIH is reached satisfies to
V(t1) = 0.3 x VDD = VDD x (1 – e(-t1/ RPUCb))
leading to t1= 0.3566749 x RPU x Cb
3. With VOH = 0.7 x VDD, the time t2at which VOH is reached satisfies to
V(t2) = 0.7 x VDD = VDD x (1 – e(-t2/ RPUCb))
leading to t2= 1.2039729 x RPU x Cb
4. With tr= t2- t1, it comes
tr= 0.8473 x RPU x Cb
5.2 Three-volt tolerant and five-volt tolerant
Electrical characteristics defines GPIO as three-volt tolerant, five-volt tolerant, and also
three-volt capable. Tolerance represents the voltage value which can be accepted by the
GPIO. Capability represents the voltage value which can be output by the GPIO.
5.2.1 Three-volt tolerant GPIO (TT)
For some STM32, electrical specifications define GPIO as three-volt tolerant or three-volt
compliant. From the user point of view, there is no difference between these two kinds of
GPIO.
Input voltage on three-volt tolerant cannot exceed VDD + 0.3 V.
If some analog input function is enabled on the GPIO (I/O structure TT_a with ADC input
active, COMP input, OPAMP input), then the maximum operating voltage on pin cannot
exceed min(VDDA, VREF+) + 0.3 V.
5.2.2 Five-volt tolerant GPIO (FT)
STM32 devices embed five-volt tolerant GPIOs. These GPIOs are actually tolerant to
VDD + 3.6 V. It means that the I/O pins can accept such voltages without causing leakage
current and damages on the GPIOs.
Regardless of the supply voltage, VIN cannot exceed 5.5 V.
When VDD = 0 V, the input voltage on the GPIO cannot exceed 3.6 V.
In case of a multi-supplied and multiplexed GPIO (VDD, VDDUSB, VLCD, VDDA), the GPIO is
tolerant to 3.6 V augmented of the minimum supply voltage among VDD, VDDUSB, VLCD, and
VDDA.
However, a GPIO is five-volt tolerant only in input mode. When the output mode is enabled,
the GPIO is no more five-volt tolerant. For more details about I/O input voltage, refer to VIN
parameters in the general operating conditions table of the datasheet.

GPIO electrical characteristics and definitions AN4899
18/31 AN4899 Rev 3
A GPIO is five-volt tolerant only if there is no analog function enabled on pin (for I/O
structure FT_a, FT_fa, TT_a). If some analog input function is enabled on the GPIO (ADC
input active, COMP input, OPAMP input), then the maximum operating voltage on pin
cannot exceed min(VDDA, VREF+) + 0.3 V.
5.3 Five-volt tolerant application examples
The following figures give examples of applications only using five-volt tolerant GPIO.
5.3.1 White LED drive
A white LED needs a typical ~20 mA current under typical 3.5 V supply (4 V max.).
As STM32 devices maximum sink current is 25 mA, there is not enough margin to directly
drive a LED. Two options, using an external MOSFET (or BJT) or driving by means of two
GPIOs, are presented in Figure 6.
Figure 6. Example of white LED drive connections
For the GPIO parallel drive option, open-drain mode must be used and internal pull-up must
be disabled. Since the ground current is huge compared to the MCU consumption, the
ground layout needs to be designed with care.
MSv46877V1
STM32
GPIO
VDD = 1.8 V or 3.3 V VDD = 5 V
STM32
GPIO2
VDD = 1.8 V or 3.3 V VDD = 5 V
GPIO1
or

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AN4899 GPIO electrical characteristics and definitions
30
5.3.2 Triac drive
A triac drive example is shown in Figure 7 for the -5 V supply system.
Figure 7. Example of triac drive connections
In this set up, the STM32 current flow depends on the output voltage level. The STM32
GPIO must be set up in open-drain mode. If the I/O drive current is not sufficient, coupled
GPIOs can be used in parallel.
5.3.3 I2C application
The STM32 device supplied by 1.8 V or 3.3 V can directly communicate with a 5 V I2C bus
as illustrated in Figure 8.
Figure 8. Example of I2C connections
If it occurs that VDD = 0 V while VDDX = 5 V (even transient), it is recommended to place a
Zenner diode (for instance 3.3 V) between VDD and VDDX.
MSv46878V1
LDO STM32
LOAD
0 V (phase)
Neutral
-5 V
5.6
-1.7 V
3.3 V
MSv46879V1
STM32
VDD = 1.8 V or 3.3 V
5 V external device
SDA
SDL
VDDX = 5.0 V VDDX = 5.0 V
5.4 V max when VDD = 1.8 V

GPIO electrical characteristics and definitions AN4899
20/31 AN4899 Rev 3
In the example shown in Figure 9, VDD is the output of the LDO supplied by VDDX.
Figure 9. Example of 5 V to 3.3 V power supply
5.3.4 UART application
If the UART transceiver to communicate with is supplied with TTL-compatible 5 V, the
STM32 device can directly communicate as shown in Figure 10.
Figure 10. Example of UART connections
If the 5 V UART interface input is TTL compatible, VOL < 0.8 V and VOH > 2.0 V. This implies
that a 3.3 V CMOS output can drive without any problem. An STM32 FT pad can accept 0 V
to 5 V CMOS level input when VDD = 3.3 V.
MSv46880V1
LDO
VDDX = 5 V VDD = 3.3 V To STM32 VDD
3.3 V
(example)
MSv46881V1
STM32
UART RX
VDD = 3.3 V
UART TX
GND GND
UART TRX
with
charge pump
TTL / CMOS compatible
+/-12 V
+/-12 V
VDD = 5 V