ST STM32 Nucleo Installation and operating instructions

March 2022 AN4899 Rev 3 1/31
1
AN4899
Application note
STM32 microcontroller GPIO hardware settings
and low-power consumption
Introduction
The STM32 microcontroller general-purpose input/output pin (GPIO) provides many ways to
interface with external circuits within an application framework. This application note
provides basic information about GPIO configurations as well as guidelines for hardware
and software developers to optimize the power performance of their STM32 32-bit Arm®
Cortex®MCUs using the GPIO pin.
This application note must be used in conjunction with the related STM32 reference manual
and datasheet available at www.st.com.
www.st.com

Contents AN4899
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Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Register abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 GPIO abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 GPIO equivalent schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 GPIO modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1 Input mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.2 Output mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.4 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 GPIO electrical characteristics and definitions . . . . . . . . . . . . . . . . . . 13
5.1 GPIO general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Pad leakage current (Ilkg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Injected current (IINJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 GPIO current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.4 Voltage output and current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.5 Pull-up calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Three-volt tolerant and five-volt tolerant . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 Three-volt tolerant GPIO (TT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.2 Five-volt tolerant GPIO (FT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Five-volt tolerant application examples . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.1 White LED drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.2 Triac drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.3 I2C application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.4 UART application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3.5 USB VBUS example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3.6 I/O usage for the five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . 21

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AN4899 Contents
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6 GPIO hardware guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Avoid floating unused pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Cross-voltage domains leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 Voltage protection when no VDD is supplied . . . . . . . . . . . . . . . . . . . . . . 24
6.4 Open-drain output with no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Using the MCO clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.6 Debug pins have PU or PD by default . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7 NRST pin cannot be used as enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.8 VBAT GPIO has limited current strength . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9 BOOT0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 GPIO software guidelines for power optimization . . . . . . . . . . . . . . . . 27
7.1 Configure unused GPIO input as analog input . . . . . . . . . . . . . . . . . . . . . 27
7.2 Adapt GPIO speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3 Disable GPIO register clock when not in use . . . . . . . . . . . . . . . . . . . . . . 27
7.4 Configure GPIO when entering low-power modes . . . . . . . . . . . . . . . . . . 27
7.5 Shutdown exit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 GPIO selection guide and configuration . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

List of tables AN4899
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List of tables
Table 1. List of GPIO structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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AN4899 List of figures
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List of figures
Figure 1. Three-volt compliant GPIO structure (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. Three-volt or five-volt tolerant GPIO structure (TT or FT). . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Output buffer and current flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Logical level compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. STM32 current flow according to output voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Example of white LED drive connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Example of triac drive connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Example of I2C connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Example of 5 V to 3.3 V power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Example of UART connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Example of USB VBUS connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Example of VBUS to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Example of five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Workaround example for five-volt ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Multi voltage leakage example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Voltage protection when VDD is not supplied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Open-drain output with no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. GPIO configuration flowchart (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. GPIO configuration flowchart (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

General information AN4899
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1 General information
STM32 microcontrollers are based on the Arm®(a) Cortex® processor.
2 Documentation conventions
2.1 Glossary
This section defines the main acronyms and abbreviations used in this document.
AMR: absolute maximum rating
GPIO: general-purpose input output
GP: general-purpose
PP: push-pull
PU: pull-up
PD: pull-down
OD: open-drain
AF: alternate function
VIH: the minimum voltage level that is interpreted as a logical 1 by a digital input
VIL: the maximum voltage level that is interpreted as a logical 0 by a digital input
VOH: the guaranteed minimum voltage level that is provided by a digital output set to
the logical 1 value
VOL: the guaranteed maximum voltage level that is provided by a digital output set to
the logical 0 value
VDD: external power supply for the I/Os
VDDIO2: external power supply for the I/Os, independent from the VDD voltage
VDDA: external power supply for analog
VSS: ground
IIH: input current when input is 1
IIL: input current when input is 0
IOH: output current when output is 1
IOL: output current when output is 0
Ilkg: leakage current
IINJ: injected current
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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2.2 Register abbreviations
The following abbreviations are used in register descriptions (x = A to H):
GPIOx_MODER: GPIO port mode register
GPIOx_OTYPER: GPIO output type register
GPIOx_OSPEEDR: GPIO output speed register
GPIOx_PUPDR: GPIO port pull-up / pull-down register
GPIOx_IDR: GPIO port input data register
GPIOx_ODR: GPIO port output data register
GPIOx_BSRR: GPIO port bit set / reset register
GPIOx_LCKR: GPIO port configuration lock register
GPIOx_AFRL: GPIO alternate function low register
GPIOx_AFRH: GPIO alternate function high register
GPIOx_ASCR: GPIO port analog switch control register
3 GPIO main features
STM32 GPIO exhibits the following features:
•Output states: push-pull, or open drain + pull-up / pull-down according to
GPIOx_MODER, GPIOx_OTYPER, and GPIOx_PUPDR registers settings
•Output data from output data register GPIOx_ODR or peripheral (alternate function
output)
•Speed selection for each I/O (GPIOx_OSPEEDR)
•Input states: floating, pull-up / pull-down, analog according to GPIOx_MODER,
GPIOx_PUPDR and GPIOx_ASCR registers settings
•Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
•Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
•Analog function selection registers (GPIOx_MODER and GPIOx_ASCR)
•Alternate function selection registers (GPIOx_MODER, GPIOx_AFRL, and
GPIOx_AFRH)
•Fast toggle capable of changing every two clock cycles
•Highly flexible pin multiplexing allowing the use of I/O pins as GPIO or as one of
several peripheral functions

GPIO functional description AN4899
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4 GPIO functional description
STM32 GPIO can be used in a variety of configurations. Each GPIO pin can be individually
configured by software in any of the following modes:
•Input floating
•Input pull-up
•Input-pull-down
•Analog
•Output open-drain with pull-up or pull-down capability
•Output push-pull with pull-up or pull-down capability
•Alternate function push-pull with pull-up or pull-down capability
•Alternate function open-drain with pull-up or pull-down capability
4.1 GPIO abbreviations
Several GPIO structures are available across the range of STM32 devices. Each structure
is associated with a list of options.
Table 1 summarizes the GPIO definitions and abbreviations applicable to STM32 products
As an example, the following description refers to a GPIO in a STM32 datasheet:
PB1 I/O FT means:
– pin PB1 I/O: port B bit 1 input / output
– FT: five-volt tolerant
Before starting a board design, it is important to refer to the datasheet of the STM32 product
or to the STM32CubeMX tool to check for GPIO availability in coherence with the target
application.
Refer to the section about software development tools at www.st.com/stm32.
Table 1. List of GPIO structures
Name Abbreviation Definition
Pin Type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT(1) Five-volt tolerant I/O pin
TT(1) Three-volt tolerant I/O pin
TC Three-volt capable I/O pin (Standard 3.3 V I/O)
B Dedicated boot pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Pin functions
Alternate functions Functions selected through GPIOx_AFR registers
Additional functions Functions directly selected and enabled through peripheral registers
1. FT and TT I/Os have options depending on the device. The user must refer to the datasheet for their definitions.

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4.2 GPIO equivalent schematics
STM32 products integrate three main GPIO basic structures:
•Three-volt compliant (abbreviated as TC).
The equivalent GPIO diagram structure is given in Figure 1.
•Three-volt tolerant (abbreviated as TT).
•Five-volt tolerant (abbreviated as FT)
The equivalent GPIO diagram structure for TT or FT is given in Figure 2.
Note: In Figure 1 and Figure 2, the analog switch in the dotted square is optional. Its presence
depends on the STM32 product considered. The analog switch is controlled by enabling
analog peripheral on the given pin (not by setting the GPIO in the analog mode). Refer to
the product datasheet for details.
In Figure 1 and Figure 2, the VDD supply may refer to VDD or VDDIO2 according to the
STM32 product considered. Refer to the product datasheet for details.
Figure 1. Three-volt compliant GPIO structure (TC)
Note: The parasitic diode in the analog domain is connected to VDDA and cannot be used as a
protection diode.
The voltage level called VDD_FT in some datasheets and reference manuals is inside the
ESD protection block.
MSv46872V1
ESD
protection
Output data
register
VDD
I/O pin
VSS
VDD
Output
control
PMOS
NMOS
Analog
option
Input buffer
Ouput buffer
on/off
on/off
VSS
Alternate function output
Input data
register
Alternate function input
VSS
Analog switch
Analog IP
Analog
VSS
VDD
Digital
VDDA
Parasitic diode
and resistor
RPU
RPD

GPIO functional description AN4899
10/31 AN4899 Rev 3
Figure 2. Three-volt or five-volt tolerant GPIO structure (TT or FT)
Note: The parasitic diode in the analog domain is connected to VDDA and cannot be used as a
protection diode.
The voltage level called VDD_FT in some datasheets and reference manuals is inside the
ESD protection block.
When the analog option is selected (by enabling analog peripheral on the given pin), the
FT I/O is not five-volt tolerant anymore since the pin is supplied with VDDA.
Caution: A TT or FT GPIO pin has no internal protection diode connected to supply (VDD). There is
no physical limitation against over-voltage. Therefore, for applications requiring a limited
voltage threshold, it is recommended to connect an external diode to VDD.
4.3 GPIO modes description
This section describes the possible GPIO pin configurations available in STM32 devices.
4.3.1 Input mode configuration
When a STM32 device I/O pin is configured as input, one of three options must be selected:
•Input with internal pull-up. Pull-up resistors are used in STM32 devices to ensure a
well-defined logical level in case of floating input signal. Depending on application
requirements, an external pull-up can be used instead.
•Input with internal pull-down. Pull-down resistors are used in STM32 devices to ensure
a well-defined logical level in case of floating input signal. Depending on application
requirements, an external pull-down can be used instead.
•Floating input. Signal level follows the external signal. When no external signal is
present, the Schmitt trigger randomly toggles between the logical levels induced by the
external noise. This increases the overall consumption.
MSv46873V1
ESD
protection
Output data
register
I/O pin
VSS
VDD
Output
control
PMOS
NMOS
Analog
option
Input buffer
Ouput buffer
on/off
on/off
VSS
Alternate function output
Input data
register
Alternate function input
VSS
Analog switch
Analog IP
Analog
VSS
VDD
Digital
VDDA
Parasitic diode
and resistor
RPU
RPD