NXP Semiconductors P89LPC980 User manual

UM10346
LPC980/982 User manual
Rev. 01 — 2 November 2009 User manual
Document information
Info Content
Keywords P89LPC980/982
Abstract Technical information for the P89LPC980/982 device

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10346
LPC980/982 User manual
Revision history
Rev Date Description
01 20091102 Initial version.

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LPC980/982 User manual
1. Introduction
The P89LPC980/982 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC980/982 in order to reduce component count,
board space, and system cost.
1.1 Pin configuration
Fig 1. P89LPC980/982 TSSOP28 pin configuration
P89LPC980
P89LPC982
002aae536
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
P2.0/TXD
P2.1/RXD
P0.0/CMP2/KBI0/SPICLK
P1.7/T3EX/MOSI
P1.6/MISO
P1.5/RST
VSS
P3.1/XTAL1
P3.0/XTAL2/CLKOUT
P1.4/INT1/T4EX/SS
P1.3/INT0/SDA/T4
P1.2/T0/SCL
P2.2/MOSI
P2.3/MISO
P2.7/SDA
P2.6/SCL
P0.1/CIN2B/KBI1
P0.2/CIN2A/KBI2
P0.3/CIN1B/KBI3/T2
P0.4/CIN1A/KBI4
P0.5/CMPREF/KBI5/T3
VDD
P0.6/CMP1/KBI6
P0.7/T1/KBI7
P1.0/TXD
P1.1/RXD/T2EX
P2.5/SPICLK
P2.4/SS

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LPC980/982 User manual
1.2 Pin description
Fig 2. P89LPC982 PLCC28 pin configuration
P89LPC982
002aae538
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12 13 14 15
16 17 18
4 3
2
1
28
27
26
P1.6/MISO
P1.5/RST
VSS
P3.1/XTAL1
P3.0/XTAL2/CLKOUT
P1.4/INT1/T4EX/SS
P1.3/INT0/SDA/T4
P1.7/T3EX/MOSI P0.0/CMP2/KBI0/SPICLK P2.1/RXD P2.0/TXD P2.7/SDA P2.6/SCL P0.1/CIN2B/KBI1
P0.2/CIN2A/KBI2
P0.3/CIN1B/KBI3/T2
P0.4/CIN1A/KBI4
P0.5/CMPREF/KBI5/T3
VDD
P0.6/CMP1/KBI6
P0.7/T1/KBI7
P1.2/T0/SCL
P2.2/MOSI P2.3/MISO
P2.4/SS
P2.5/SPICLK
P1.1/RXD/T2EX
P1.0/TXD
Table 1. Pin description
Symbol Pin Type Description
PLCC28,
TSSOP28
P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
4.1 “Port configurations”for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt trigger inputs.
Port 0 also provides various special functions as described below:
P0.0/CMP2/KBI0/
SPICLK 3I/OP0.0 — Port 0 bit 0.
OCMP2 — Comparator 2 output
IKBI0 — Keyboard input 0.
I/O SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input. (Pin Remap)

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P0.1/CIN2B/
KBI1 26 I/O P0.1 — Port 0 bit 1.
ICIN2B — Comparator 2 positive input B.
IKBI1 — Keyboard input 1.
P0.2/CIN2A/
KBI2 25 I/O P0.2 — Port 0 bit 2.
ICIN2A — Comparator 2 positive input A.
IKBI2 — Keyboard input 2.
P0.3/CIN1B/
KBI3/T2 24 I/O P0.3 — Port 0 bit 3. High current source.
ICIN1B — Comparator 1 positive input B.
IKBI3 — Keyboard input 3.
I/O T2 — Timer/counter 2 external count input or overflow output.
P0.4/CIN1A/
KBI4 23 I/O P0.4 — Port 0 bit 4. High current source.
ICIN1A — Comparator 1 positive input A.
IKBI4 — Keyboard input 4.
P0.5/CMPREF/
KBI5/T3 22 I/O P0.5 — Port 0 bit 5. High current source.
ICMPREF — Comparator reference (negative) input.
IKBI5 — Keyboard input 5.
I/O T3 — Timer/counter 3 external count input or overflow output.
Table 1. Pin description …continued
Symbol Pin Type Description
PLCC28,
TSSOP28

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P0.6/CMP1/KBI6 20 I/O P0.6 — Port 0 bit 6. High current source.
OCMP1 — Comparator 1 output.
IKBI6 — Keyboard input 6.
P0.7/KBI7/T1 19 I/O P0.7 — Port 0 bit 7. High current source.
I/O T1 — Timer/counter 1 external count input or overflow output.
IKBI7 — Keyboard input 7.
P1.0 to P1.7 I/O, I
[1] Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for
three pins as noted below. During reset Port 1 latches are configured in the input
only mode with the internal pull-up disabled. The operation of the configurable
Port 1 pins as inputs and outputs depends upon the port configuration selected.
Each of the configurable port pins are programmed independently. Refer to Section
4.1 “Port configurations”for details. P1.2 to P1.3 are open drain when used as
outputs. P1.5 is input only.
All pins have Schmitt trigger inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 18 I/O P1.0 — Port 1 bit 0.
OTXD — Transmitter output for serial port.
P1.1/RXD/T2EX 17 I/O P1.1 — Port 1 bit 1.
IRXD — Receiver input for serial port.
IT2EX — Timer/counter 2 external capture input.
P1.2/SCL/T0 12 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overflow output. (open-drain when
used as output.)
I/O SCL — I2C-bus serial clock input/output.
P1.3/INT0/SDA/
T4 11 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).
IINT0 — External interrupt 0 input.
I/O SDA — I2C-bus serial data input/output.
I/O T4 — Timer/counter 4 external count input or overflow output.
P1.4/INT1/T4EX/
SS 10 I/O P1.4 — Port 1 bit 4. High current source.
IINT1 — External interrupt 1 input.
IT4EX — Timer/counter 4 external capture input.
ISS — SPI Slave select . (Pin Remap)
P1.5/RST 6IP1.5 — Port 1 bit 5 (input only).
IRST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
P1.6/MISO 5 I/O P1.6 — Port 1 bit 6. High current source.
I/O MISO — SPI master in slave out. When configured as master, this pin is input,
when configured as slave, this pin is output. (Pin Remap)
Table 1. Pin description …continued
Symbol Pin Type Description
PLCC28,
TSSOP28

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P1.7/T3EX/MOSI 4 I/O P1.7 — Port 1 bit 7. High current source.
IT3EX — Timer/counter 3 external capture input.
I/O MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input. (Pin Remap)
P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
4.1 “Port configurations”for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/TXD 1 I/O P2.0 — Port 2 bit 0.
OTXD — Transmitter output for serial port. (Pin Remap)
P2.1/RXD 2 I/O P2.1 — Port 2 bit 1.
IRXD — Receiver input for serial port. (Pin Remap)
P2.2/MOSI 13 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input.
P2.3/MISO 14 I/O P2.3 — Port 2 bit 3.
I/O MISO — SPI master in slave out.When configured as master, this pin is input,
when configured as slave, this pin is output.
P2.4/SS 15 I/O P2.4 — Port 2 bit 4.
ISS — SPI Slave select.
P2.5/SPICLK 16 I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6/SCL 27 I/O P2.6 — Port 2 bit 6.
I/O SCL — I2C-bus serial clock input/output. (Pin Remap)
P2.7/SDA 28 I/O P2.7 — Port 2 bit 7.
I/O SDA — I2C-bus serial data input/output. (Pin Remap)
P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
4.1 “Port configurations”for details.
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT 9I/OP3.0 — Port 3 bit 0.
OXTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration.
OCLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the RTC/system timer.
Table 1. Pin description …continued
Symbol Pin Type Description
PLCC28,
TSSOP28

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[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P3.1/XTAL1 8 I/O P3.1 — Port 3 bit 1.
IXTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the flash configuration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the RTC/system timer.
VSS 7IGround: 0 V reference.
VDD 21 I Power supply: This is the power supply voltage for normal operation as well as
Idle and Power-down modes.
Table 1. Pin description …continued
Symbol Pin Type Description
PLCC28,
TSSOP28

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LPC980/982 User manual
1.3 Logic symbols
(1) For Pin Remap.
Fig 3. P89LPC980/982 logic symbol
VDD VSS
PORT 0
PORT 3
TXD
RXD
T0
INT0
INT1
RST
SCL
SDA
002aae534
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
XTAL1
KBI0SPICLK(1)
T2
T3
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
MOSI
MISO
SS
SPICLK
PORT 1
T2EX
SCL(1)
SDA(1)
T4
T4EX SS(1)
MOSI(1)
MISO(1)
T3EX
PORT 2
P89LPC980/982
TXD(1)
RXD(1)
CLKOUT

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1.4 Block diagram
Fig 4. P89LPC980/982 Block diagram
ACCELERATED 2-CLOCK 80C51 CPU
8 kB/4 kB
CODE FLASH
256-BYTE
DATA RAM
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
clock
CONFIGURABLE
OSCILLATOR
ON-CHIP RC
OSCILLATOR
WITH CLOCK
DOUBLER
internal bus
POWER MANAGEMENT
(POWER-ON RESET,
BROWNOUT RESET,
REGULATORS)
002aae532
UART
ANALOG
COMPARATORS
256-BYTE
AUXILIARY RAM
(P89LPC982)
I2C-BUS
PORT 3
CONFIGURABLE I/Os
P89LPC980/982
WATCHDOG TIMER
AND OSCILLATOR
TIMER 0
TIMER 1
REAL-TIME CLOCK/
SYSTEM TIMER
SPI
P3[1:0]
P2[7:0]
P1[7:0]
P0[7:0]
TXD
RXD
SCL
SDA
T0
T1
CMP2
CIN2B
CIN2A
CMP1
CIN1A
CIN1B
TIMER 2
TIMER 3
TIMER 4
T2
T2EX
T3
T3EX
T4
T4EX
SPICLK
MOSI
MISO
SS
CRYSTAL
OR
RESONATOR XTAL2
XTAL1

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1.5 Special function registers
Remark: SFR accesses are restricted in the following ways:
•User must not attempt to access any SFR locations not defined.
•Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
•SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
–‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
–‘0’ must be written with ‘0’, and will return a ‘0’ when read.
–‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Table 2. Special function registers - P89LPC980/982
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary
Bit address E7 E6 E5 E4 E3 E2 E1 E0
ACC* Accumulator E0H 00 0000 0000
AUXR1 Auxiliary
function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0
Bit address F7 F6 F5 F4 F3 F2 F1 F0
B* B register F0H 00 0000 0000
BRGR0[2] Baud rate
generator 0 rate
low
BEH 00 0000 0000
BRGR1[2] Baud rate
generator 0 rate
high
BFH 00 0000 0000
BRGCON Baud rate
generator 0
control
BDH------SBRGSBRGEN00
[2] xxxx xx00
CMP1 Comparator 1
control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00[1] xx00 0000
CMP2 Comparator 2
control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00[1] xx00 0000
DIVM CPU clock
divide-by-M
control
95H 00 0000 0000
DPTR Data pointer
(2 bytes)
DPH Data pointer
high 83H 00 0000 0000
DPL Data pointer low 82H 00 0000 0000
FMADRH Program flash
address high E7H 00 0000 0000
FMADRL Program flash
address low E6H 00 0000 0000

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FMCON Program flash
control (Read) E4H BUSY - - - HVA HVE SV OI 70 0111 0000
Program flash
control (Write) E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0
FMDATA Program flash
data E5H 00 0000 0000
I2ADR I2C-bus slave
address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000
Bit address DF DE DD DC DB DA D9 D8
I2CON* I2C-bus control
register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0
I2DAT I2C-bus data
register DAH
I2SCLH Serial clock
generator/SCL
duty cycle
register high
DDH 00 0000 0000
I2SCLL Serial clock
generator/SCL
duty cycle
register low
DCH 00 0000 0000
I2STAT I2C-bus status
register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000
Bit address AF AE AD AC AB AA A9 A8
IEN0* Interrupt enable
0A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000
Bit address EF EE ED EC EB EA E9 E8
IEN1* Interrupt enable
1E8H - EST - EXTIM ESPI EC EKBI EI2C 00[1] 00x0 0000
Bit address BF BE BD BC BB BA B9 B8
IP0* Interrupt priority
0B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[1] x000 0000
IP0H Interrupt priority
0 high B7H - PWDRTH PBOH PSH/ PSRH PT1H PX1H PT0H PX0H 00[1] x000 0000
Table 2. Special function registers - P89LPC980/982
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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Bit address FF FE FD FC FB FA F9 F8
IP1* Interrupt priority
1F8H - PST - PXTIM PSPI PC PKBI PI2C 00[1] 00x0 0000
IP1H Interrupt priority
1 high F7H - PSTH - PXTIMH PSPIH PCH PKBIH PI2CH 00[1] 00x0 0000
KBCON Keypad control
register 94H------PATN _SEL KBIF 00[1] xxxx xx00
KBMASK Keypad
interrupt mask
register
86H 00 0000 0000
KBPATN Keypad pattern
register 93H FF 1111 1111
Bit address 87 86 85 84 83 82 81 80
P0* Port 0 80H T1/KB7 CMP1
/KB6 CMPREF /KB5/T3 CIN1A /KB4 CIN1B /KB3/T2 CIN2A /KB2 CIN2B /KB1 CMP2 /KB0 [1]
Bit address 97 96 95 94 93 92 91 90
P1* Port 1 90H T3EX - RST INT1/T4E
XINT0/SDA/ T4 T0/SCL RXD/T2EX TXD [1]
Bit address A7 A6 A5 A4 A3 A2 A1 A0
P2* Port 2 A0H - - SPICLK SS MISO MOSI - - [1]
Bit address B7 B6 B5 B4 B3 B2 B1 B0
P3*Port3 B0H------XTAL1XTAL2
[1]
P0M1 Port 0 output
mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111
P0M2 Port 0 output
mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] 0000 0000
P1M1 Port 1 output
mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1 xx11
P1M2 Port 1 output
mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1] 00x0 xx00
Table 2. Special function registers - P89LPC980/982
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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P2M1 Port 2 output
mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF[1] 1111 1111
P2M2 Port 2 output
mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00[1] 0000 0000
P3M1 Port 3 output
mode 1 B1H------(P3M1.1)(P3M1.0)03
[1] xxxx xx11
P3M2 Port 3 output
mode 2 B2H------(P3M2.1)(P3M2.0)00
[1] xxxx xx00
PCON Power control
register 87H SMOD1 SMOD0 - BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000
PCONA Power control
register A B5H RTCPD - VCPD - I2PD SPPD SPD - 00[1] 0000 0000
PINCON Pin Remap
control register CFH - - - - - UART SPI I2C 00[1] 0000 0000
PMUCON Power
Management
Unit control
register
FAHLPMOD------HCOK0xxx xxx1
Bit address D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status
word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000
PT0AD Port 0 digital
input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x
PWMD2H PWM Free
Cycle Register
2 High Byte
AEH 00 0000 0000
PWMD2L PWM Free
Cycle Register
2 Low Byte
AFH 00 0000 0000
PWMD3H PWM Free
Cycle Register
3 High Byte
E9H 00 0000 0000
Table 2. Special function registers - P89LPC980/982
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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PWMD3L PWM Free
Cycle Register
3 Low Byte
EAH 00 0000 0000
PWMD4H PWM Free
Cycle Register
4 High Byte
AAH 00 0000 0000
PWMD4L PWM Free
Cycle Register
4 Low Byte
ABH 00 0000 0000
RCAP2H Capture
Register 2 High
Byte
FCH 00 0000 0000
RCAP2L Capture
Register 2 Low
Byte
FBH 00 0000 0000
RCAP3H Capture
Register 3 High
Byte
ECH 00 0000 0000
RCAP3L Capture
Register 3 Low
Byte
EBH 00 0000 0000
RCAP4H Capture
Register 4 High
Byte
CAH 00 0000 0000
RCAP4L Capture
Register 4 Low
Byte
C9H 00 0000 0000
RSTSRC Reset source
register DFH - BOIF BORF POF R_KB R_WD R_SF R_EX [3]
RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60[1][6] 011x xx00
RTCH RTC register
high D2H 00[6] 0000 0000
RTCL RTC register
low D3H 00[6] 0000 0000
Table 2. Special function registers - P89LPC980/982
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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SADDR Serial port
address register A9H 00 0000 0000
SADEN Serial port
address enable B9H 00 0000 0000
SBUF Serial Port data
buffer register 99H xx xxxx xxxx
Bit address 9F 9E 9D 9C 9B 9A 99 98
SCON* Serial port
control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000
SSTAT Serial port
extended status
register
BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000
SP Stack pointer 81H 07 0000 0111
SPCTL SPI control
register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100
SPSTAT SPI status
register E1HSPIFWCOL------0000xxxxxx
SPDAT SPI data
register E3H 00 0000 0000
TAMOD Timer 0 and 1
auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0
Bit address 8F 8E 8D 8C 8B 8A 89 88
TCON* Timer 0 and 1
control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000
TH0 Timer 0 high 8CH 00 0000 0000
TH1 Timer 1 high 8DH 00 0000 0000
TL0 Timer 0 low 8AH 00 0000 0000
TL1 Timer 1 low 8BH 00 0000 0000
TMOD Timer 0 and 1
mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0000 0000
T2CON Timer/Counter2
Control FFH PSEL2 ENT2 TIEN2 PWM2 EXEN2 TR2 C/NT2 CP/NRL2 00 0000 0000
Table 2. Special function registers - P89LPC980/982
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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[1] All ports are in input only (high-impedance) state after power-up.
[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3] The RSTSRC register reflects the cause of the UM10346 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on
reset value is x011 0000.
TH2 Timer/Counter2
High Byte FEH 00 0000 0000
TL2 Timer/Counter2
Low Byte FDH 00 0000 0000
T3CON Timer/Counter3
Control EFH PSEL3 ENT3 TIEN3 PWM3 EXEN3 TR3 C/NT3 CP/NRL3 00 0000 0000
TH3 Timer/Counter3
High Byte EEH 00 0000 0000
TL3 Timer/Counter3
Low Byte EDH 00 0000 0000
T4CON Timer/Counter2
Control CDH PSEL4 ENT4 TIEN4 PWM4 EXEN4 TR4 C/NT4 CP/NRL4 00 0000 0000
TH4 Timer/Counter4
High Byte CCH 00 0000 0000
TL4 Timer/Counter4
Low Byte CBH 00 0000 0000
TINTF Timer/Counters
2/3/4 Overflow
and External
Flags
CEH - - TF4 EXF4 TF3 EXF3 TF2 EXF2 00 0000 0000
TRIM Internal
oscillator trim
register
96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 [5][6]
WDCON Watchdog
control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4][6]
WDL Watchdog load C1H FF 1111 1111
WFEED1 Watchdog
feed 1 C2H
WFEED2 Watchdog
feed 2 C3H
Table 2. Special function registers - P89LPC980/982
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.
[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are
used to access these extended SFRs.
[2] The BOICFG2/1/0 will be copied from UCFG1.5 to UCFG1.3 when power-on reset.
[3] CLKCON register reset value comes from UCFG1. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from
UCFG1.7.
Table 3. Extended special function registers - P89LPC980/982[1]
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary
BODCFG BOD
configuration
register
FFC8H - - - - - BOICFG2 BOICFG1 BOICFG0 [2]
CLKCON CLOCK Control
register FFDEH CLKOK - WDMOD XTALWD CLKDBL FOSC2 FOSC1 FOSC0 [3] 1000 xxxx
CMPREF Comparator
referencre
register
FFCBH - REFS5 REFS4 REFS3 - REFS2 REFS1 REFS0 00 0000 0000
RTCDATH Real-time clock
data register
high
FFBFH 00 0000 0000
RTCDATL Real-time clock
data register low FFBEH 00 0000 0000

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1.6 Memory organization
The various P89LPC980/982 memory spaces are as follows:
DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction
other than MOVX and MOVC. All or part of the Stack may be in this area.
IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using
instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and
the 128 bytes immediately above it.
SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via
direct addressing.
(1) ISP code is located at the end of sector 3 on the P89LPC980 and at the endof sector 7 on P89LPC982.
Fig 5. P89LPC980/982 memory map
002aae986
0000h
03FFh
0400h
07FFh
0800h
0BFFh
0C00h
0FFFh
SECTOR 0
SECTOR 1
SECTOR 2
SECTOR 3
1000h
13FFh
1400h
17FFh
1800h
1BFFh
1C00h
1E00h
1FFFh
SECTOR 4
SECTOR 5
SECTOR 6
FFEFh
FF00h IAP entry-
points
SECTOR 7
ISP CODE
(512B)
(1)
SPECIAL FUNCTION
REGISTERS
(DIRECTLY ADDRESSABLE)
128 BYTES ON-CHIP
DATA MEMORY (STACK,
DIRECT AND INDIR. ADDR.)
4 REG. BANKS R[7:0]
data memory
(DATA, IDATA)
DATA
128 BYTES ON-CHIP
DATA MEMORY (STACK
AND INDIR. ADDR.)
IDATA (incl. DATA)
FFEFh FFh
80h
7Fh
00h
FF1Fh
FF00h
entry points for:
-51 ASM. code
-C code
IDATA routines
1FFFh
1E00h
entry points for:
-UART (auto-baud)
-I2C, SPI, etc.(1)
ISP serial loader
entry
points
read-protected
IAP calls only
EXTENDED SFRs
FFFFh
FFB0h
RESERVED
00FFh
XDATA
(256 BYTES)
(P89LPC982) 0000h