ST STM32F74 Series User manual

June 2015 DocID027559 Rev 2 1/45
1
AN4661
Application note
Getting started with STM32F74xxx/STM32F75xxx MCU hardware
development
Introduction
This application note is intended for system designers who require an hardware
implementation overview of the development board, with focus on features:
•Power supply,
•Package selection,
•Clock management,
•Reset control,
•Boot mode settings,
•Debug management.
This document describes the minimum hardware resources required to develop an
application based on the STM32F74xxx/STM32F75xxx devices.
Table 1. Applicable products
Type Part number
Microcontrollers
STM32F745IE, STM32F745VE, STM32F745IG, STM32F745VG,
STM32F745ZE, STM32F745ZG
STM32F746VG, STM32F746ZG, STM32F746IG, STM32F746BG,
STM32F746NG, STM32F746IE, STM32F746VE, STM32F746ZE,
STM32F746BE, STM32F746NE
STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG
www.st.com

Contents AN4661
2/45 DocID027559 Rev 2
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7
1.1.2 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.4 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 11
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.4 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.5 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.6 Regulator OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.7 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 16
2 Alternate function mapping to pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 External user clock (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 19
3.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 External clock (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 20
3.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 System bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DocID027559 Rev 2 3/45
AN4661 Contents
4
5.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 25
5.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 25
6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 Ground and power supply (VSS,VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 Recommended PCB routing guidelines for
STM32F745xx/STM32F756xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 PCB stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3 Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.4 High speed signal layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.4.1 SDMMC bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.4.2 Flexible memory controller (FMC) interface . . . . . . . . . . . . . . . . . . . . . . 37
8.4.3 Quadrature serial parallel interface (Quad SPI) . . . . . . . . . . . . . . . . . . . 38
8.4.4 Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.5 Package layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.5.1 BGA 216 0.8 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . . . 39

Contents AN4661
4/45 DocID027559 Rev 2
8.5.2 WLCSP143 0.4 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . 41
9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DocID027559 Rev 2 5/45
AN4661 List of tables
5
List of tables
Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. STM32F74xxx/STM32F75xxx bootloader communication peripherals. . . . . . . . . . . . . . . . 22
Table 5. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Flexible SWJ-DP assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. BGA 216 0.8 mm pitch package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. Wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

List of figures AN4661
6/45 DocID027559 Rev 2
List of figures
Figure 1. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. VDDUSB connected to external power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. PVD threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 13
Figure 8. NRST circuitry timing example for STM32F74xxx/STM32F75xxx . . . . . . . . . . . . . . . . . . . 14
Figure 9. BYPASS_REG supervisor reset connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. STM32CubeMX example screen-shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Host to board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. Typical layout for VDD/VSS pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 19. STM32F756NGH6 reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. Four layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21. Six layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. Example of bypass cap placed underneath the STM32F74xxx/STM32F75xxx . . . . . . . . . 36
Figure 23. BGA 0.8mm pitch example of fan-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. Via fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. FMC signal fan-out routing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 26. 143-bumps WLCSP, 0.40 mm pitch routing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DocID027559 Rev 2 7/45
AN4661 Power supplies
44
1 Power supplies
1.1 Introduction
The device requires a 1.8 to 3.6 V operating voltage supply (VDD), which can be reduced
down to 1.7 V with PDR OFF, as detailed in the product datasheets. The embedded linear
voltage regulator is used to supply the internal 1.2 V digital power.
The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM)
can be powered from the VBAT voltage when the main VDD supply is powered off.
1.1.1 Independent A/D converter supply and reference voltage
To improve the conversion accuracy, the ADC has an independent power supply which can
be separately filtered and shielded from noise on the PCB.
•The ADC voltage supply input is available on a separate VDDA pin.
•An isolated supply ground connection is provided on pin VSSA.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF
. The voltage on VREF ranges from 1.8 V to VDDA.
When available (depending on package), VREF– must be externally tied to VSSA.
1.1.2 Independent USB transceivers supply
The USB transceivers are supplied from a separated VDDUSB power supply pin.
VDDUSB can be connected either to VDD or an external independent power supply (3.0 to
3.6V) for USB transceivers (refer to Figure 1 and Figure 2). For example, when device is
powered at 1.8V, an independent power supply 3.3V can be connected to VDDUSB. When
the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA
but it must be the last supply to be provided and the first to disappear. The following
conditions VDDUSB must be respected:
•During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD
•During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD
•VDDSUB rising and falling time rate specifications must be respected (refer to operating
conditions at power-up / power-down (regulator ON) table and operating conditions at
power-up / power-down (regulator OFF) table of STM32F74xxx/STM32F75xxx
datasheet).
•In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
–TheV
DDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If
only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.

Power supplies AN4661
8/45 DocID027559 Rev 2
Figure 1. VDDUSB connected to VDD power supply
Figure 2. VDDUSB connected to external power supply.
1.1.3 Battery backup domain
Backup domain description
To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when
VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a
battery or by another source.
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DocID027559 Rev 2 9/45
AN4661 Power supplies
44
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
•PC14 and PC15 can be used as LSE pins only.
•PC13 can be used as tamper pin (TAMP1).
•PI8 can be used as tamper pin (TAMP2).
1.1.4 Voltage regulator
The voltage regulator is always enabled after reset. It works in three different modes
depending on the application modes.
•In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals).
•In Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the
contents of the registers and SRAM.
•In Standby mode, the regulator is powered down. The contents of the registers and
SRAM are lost except for those concerned with the standby circuitry and the backup
domain.
Note: Depending on the selected package, there are specific pins that should be connected either
to VSS or VDD to activate or deactivate the voltage regulator. Refer to the voltage regulator
section in the datasheet for more details.
1.2 Power supply scheme
•VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins. The VDD pins must be connected to
VDD with external decoupling capacitors: one single tantalum or ceramic capacitor
(min. 4.7 μF) for the package + one 100 nF ceramic capacitor for each VDD pin.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
The VDDA pin must be connected to two external decoupling capacitors (100 nF
ceramic + 1 μF tantalum or ceramic).
•VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers. For example, when the device is powered at 1.8V, an
independent power supply 3.3V can be connected to VDDUSB.
The VDDUSB pin must be connected to two external decoupling capacitors (100 nF
ceramic + 1 μF tantalum or ceramic).
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
The VBAT pin can be connected to the external battery (1.65 V < VBAT < 3.6 V). If no
external battery is used, it is recommended to connect this pin to VDD with a 100 nF
external ceramic decoupling capacitor.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 1.3.5: Internal reset OFF).
•The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, a 100 nF and a 1 μF capacitors must be

Power supplies AN4661
10/45 DocID027559 Rev 2
connected on this pin. In all cases, VREF+ must be kept between (VDDA-1.2 V) and
VDDA with minimum of 1.7 V.
•Additional precautions can be taken to filter analog noise:
–V
DDA can be connected to VDD through a ferrite bead.
–TheV
REF+ pin can be connected to VDDA through a resistor (typ. 47 Ω).
•For the voltage regulator configuration, there is specific BYPASS_REG pin (not
available on all packages) that should be connected either to VSS or VDD to activate or
deactivate the voltage regulator specific.
Note: Refer to the voltage regulator section of the related device datasheet for more details.
•When the voltage regulator is enabled, VCAP1 and VCAP2 pins must be connected to
2*2.2 μF low ESR < 2Ωceramic capacitor.
Figure 3. Power supply scheme
1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and 1
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