GigaDevice Semiconductor GD32F10 Series User manual

GigaDevice Semiconductor Inc.
GD32F10x
Arm® Cortex®-M3 32-bit MCU
User Manual
Revision 2.6
( Jun. 2022 )

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................18
List of Tables ................................................................................................................25
1. System and memory architecture ........................................................................29
1.1. Arm®Cortex®-M3 processor ..................................................................................... 29
1.2. System architecture .................................................................................................. 30
1.3. Memory map .............................................................................................................. 35
1.3.1. Bit-banding............................................................................................................................ 39
1.3.2. On-chip SRAM memory........................................................................................................ 40
1.3.3. On-chip flash memory overview ........................................................................................... 40
1.4. Boot configuration..................................................................................................... 40
1.5. Device electronic signature...................................................................................... 41
1.5.1. Memory density information.................................................................................................. 42
1.5.2. Unique device ID (96 bits) .................................................................................................... 42
1.6. System configuration registers................................................................................ 43
2. Flash memory controller (FMC)............................................................................44
2.1. Overview .................................................................................................................... 44
2.2. Characteristics........................................................................................................... 44
2.3. Function overview..................................................................................................... 44
2.3.1. Flash memory architecture ................................................................................................... 44
2.3.2. Read operations ................................................................................................................... 45
2.3.3. Unlock the FMC_CTLx registers........................................................................................... 46
2.3.4. Page erase............................................................................................................................ 46
2.3.5. Mass erase ........................................................................................................................... 47
2.3.6. Main flash programming ....................................................................................................... 49
2.3.7. Option bytes Erase ............................................................................................................... 50
2.3.8. Option bytes modify .............................................................................................................. 51
2.3.9. Option bytes description ....................................................................................................... 51
2.3.10. Page erase/program protection ............................................................................................ 53
2.3.11. Security protection ................................................................................................................ 53
2.4. Register definition..................................................................................................... 54
2.4.1. Wait state register (FMC_WS).............................................................................................. 54
2.4.2. Unlock key register 0 (FMC_KEY0)...................................................................................... 54
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 55

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2.4.4. Status register 0 (FMC_STAT0)............................................................................................ 55
2.4.5. Control register 0 (FMC_CTL0) ............................................................................................ 56
2.4.6. Address register 0 (FMC_ADDR0) ....................................................................................... 57
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 58
2.4.8. Erase/Program Protection register (FMC_WP) .................................................................... 58
2.4.9. Unlock key register 1(FMC_KEY1)....................................................................................... 59
2.4.10. Status register 1 (FMC_STAT1)............................................................................................ 59
2.4.11. Control register 1 (FMC_CTL1) ............................................................................................ 60
2.4.12. Address register 1 (FMC_ADDR1) ....................................................................................... 61
2.4.13. Wait state enable register (FMC_WSEN) ............................................................................. 62
2.4.14. Product ID register (FMC_PID)............................................................................................. 62
3. Power management unit (PMU) ............................................................................64
3.1. Overview .................................................................................................................... 64
3.2. Characteristics........................................................................................................... 64
3.3. Function overview..................................................................................................... 64
3.3.1. Backup domain ..................................................................................................................... 65
3.3.2. VDD / VDDA power domain ...................................................................................................... 66
3.3.3. 1.2V power domain............................................................................................................... 68
3.3.4. Power saving modes ............................................................................................................ 68
3.4. Register definition..................................................................................................... 71
3.4.1. Control register (PMU_CTL) ................................................................................................. 71
3.4.2. Control and status register (PMU_CS) ................................................................................. 72
4. Backup registers (BKP).........................................................................................74
4.1. Overview .................................................................................................................... 74
4.2. Characteristics........................................................................................................... 74
4.3. Function overview..................................................................................................... 74
4.3.1. RTC clock calibration ............................................................................................................ 74
4.3.2. Tamper detection .................................................................................................................. 75
4.4. Register definition..................................................................................................... 76
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) .................................................................. 76
4.4.2. RTC signal output control register (BKP_OCTL).................................................................. 76
4.4.3. Tamper pin control register (BKP_TPCTL) ........................................................................... 77
4.4.4. Tamper control and status register (BKP_TPCS) ................................................................. 77
5. Reset and clock unit (RCU)...................................................................................79
Medium-, High- and extra-density reset and clock control unit (RCU)............................. 79
5.1. Reset control unit (RCTL) ......................................................................................... 79
5.1.1. Overview ............................................................................................................................... 79
5.1.2. Function overview ................................................................................................................. 79

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5.2. Clock control unit (CCTL) ......................................................................................... 80
5.2.1. Overview ............................................................................................................................... 80
5.2.2. Characteristics ...................................................................................................................... 82
5.2.3. Function overview ................................................................................................................. 82
5.3. Register definition..................................................................................................... 86
5.3.1. Control register (RCU_CTL) ................................................................................................. 86
5.3.2. Clock configuration register 0 (RCU_CFG0) ........................................................................ 87
5.3.3. Clock interrupt register (RCU_INT) ...................................................................................... 91
5.3.4. APB2 reset register (RCU_APB2RST) ................................................................................. 93
5.3.5. APB1 reset register (RCU_APB1RST) ................................................................................. 96
5.3.6. AHB enable register (RCU_AHBEN) .................................................................................... 99
5.3.7. APB2 enable register (RCU_APB2EN) .............................................................................. 100
5.3.8. APB1 enable register (RCU_APB1EN) .............................................................................. 102
5.3.9. Backup domain control register (RCU_BDCTL) ................................................................. 105
5.3.10. Reset source/clock register (RCU_RSTSCK) .................................................................... 107
5.3.11. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 108
Connectivity line devices: Reset and clock control unit (RCU).......................................110
5.4. Reset control unit (RCTL) ........................................................................................110
5.4.1. Overview ..............................................................................................................................110
5.4.2. Function overview ................................................................................................................110
5.5. Clock control unit (CCTL) ........................................................................................111
5.5.1. Overview ..............................................................................................................................111
5.5.2. Characteristics .....................................................................................................................113
5.5.3. Function overview ................................................................................................................113
5.6. Register definition....................................................................................................118
5.6.1. Control register (RCU_CTL) ................................................................................................118
5.6.2. Clock configuration register 0 (RCU_CFG0) ...................................................................... 120
5.6.3. Clock interrupt register (RCU_INT) .................................................................................... 123
5.6.4. APB2 reset register (RCU_APB2RST) ............................................................................... 126
5.6.5. APB1 reset register (RCU_APB1RST) ............................................................................... 128
5.6.6. AHB enable register (RCU_AHBEN) .................................................................................. 131
5.6.7. APB2 enable register (RCU_APB2EN) .............................................................................. 133
5.6.8. APB1 enable register (RCU_APB1EN) .............................................................................. 135
5.6.9. Backup domain control register (RCU_BDCTL) ................................................................. 137
5.6.10. Reset source/clock register (RCU_RSTSCK) .................................................................... 138
5.6.11. AHB reset register (RCU_AHBRST)................................................................................... 140
5.6.12. Clock configuration register 1 (RCU_CFG1) ...................................................................... 141
5.6.13. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 143
6. Interrupt/event controller (EXTI).........................................................................144
6.1. Overview .................................................................................................................. 144

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6.2. Characteristics......................................................................................................... 144
6.3. Function overview ................................................................................................... 144
6.4. External interrupt and event (EXTI) block diagram ............................................... 148
6.5. External Interrupt and Event function overview.................................................... 149
6.6. Register definition ................................................................................................... 150
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 150
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 150
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 151
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 151
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 152
6.6.6. Pending register (EXTI_PD) ............................................................................................... 152
7. General-purpose and alternate-function I/Os (GPIO and AFIO).......................153
7.1. Overview .................................................................................................................. 153
7.2. Characteristics......................................................................................................... 153
7.3. Function overview ................................................................................................... 153
7.3.1. GPIO pin configuration ....................................................................................................... 154
7.3.2. External interrupt/event lines .............................................................................................. 155
7.3.3. Alternate functions (AF) ...................................................................................................... 155
7.3.4. Input configuration .............................................................................................................. 155
7.3.5. Output configuration ........................................................................................................... 155
7.3.6. Analog configuration ........................................................................................................... 156
7.3.7. Alternate function (AF) configuration .................................................................................. 156
7.3.8. IO pin function selection ..................................................................................................... 157
7.3.9. GPIO locking function ......................................................................................................... 158
7.4. Remapping function I/O and debug configuration ................................................ 158
7.4.1. Introduction ......................................................................................................................... 158
7.4.2. Main features ...................................................................................................................... 158
7.4.3. JTAG/SWD alternate function remapping........................................................................... 158
7.4.4. ADC AF remapping............................................................................................................. 159
7.4.5. TIMER AF remapping ......................................................................................................... 160
7.4.6. USART AF remapping ........................................................................................................ 161
7.4.7. I2C0 AF remapping ............................................................................................................. 162
7.4.8. SPI0/SPI2/I2S AF remapping ............................................................................................. 162
7.4.9. CAN0/1 AF remapping........................................................................................................ 163
7.4.10. Ethernet AF remapping....................................................................................................... 164
7.4.11. CLK pins AF remapping ...................................................................................................... 164
7.5. Register definition ................................................................................................... 165
7.5.1. Port control register 0 (GPIOx_CTL0, x=A..G) ................................................................... 165
7.5.2. Port control register 1 (GPIOx_CTL1, x=A..G) ................................................................... 167

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7.5.3. Port input status register (GPIOx_ISTAT, x=A..G) .............................................................. 169
7.5.4. Port output control register (GPIOx_OCTL, x=A..G) .......................................................... 169
7.5.5. Port bit operate register (GPIOx_BOP, x=A..G).................................................................. 170
7.5.6. Port bit clear register (GPIOx_BC, x=A..G) ........................................................................ 170
7.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G).................................................... 171
7.5.8. Event control register (AFIO_EC) ....................................................................................... 171
7.5.9. AFIO port configuration register 0 (AFIO_PCF0) ............................................................... 172
7.5.10. EXTI sources selection register 0 (AFIO_EXTISS0) .......................................................... 178
7.5.11. EXTI sources selection register 1 (AFIO_EXTISS1) .......................................................... 180
7.5.12. EXTI sources selection register 2 (AFIO_EXTISS2) .......................................................... 181
7.5.13. EXTI sources selection register 3 (AFIO_EXTISS3) .......................................................... 182
7.5.14. AFIO port configuration register 1 (AFIO_PCF1) ............................................................... 183
8. Cyclic redundancy checks management unit (CRC) ........................................185
8.1. Overview .................................................................................................................. 185
8.2. Characteristics......................................................................................................... 185
8.3. Function overview ................................................................................................... 186
8.4. Register definition ................................................................................................... 187
8.4.1. Data register (CRC_DATA) ................................................................................................. 187
8.4.2. Free data register (CRC_FDATA) ....................................................................................... 187
8.4.3. Control register (CRC_CTL) ............................................................................................... 188
9. Direct memory access controller (DMA)............................................................189
9.1. Overview .................................................................................................................. 189
9.2. Characteristics......................................................................................................... 189
9.3. Block diagram.......................................................................................................... 190
9.4. Function overview ................................................................................................... 190
9.4.1. DMA operation .................................................................................................................... 190
9.4.2. Peripheral handshake......................................................................................................... 192
9.4.3. Arbitration............................................................................................................................ 192
9.4.4. Address generation............................................................................................................. 193
9.4.5. Circular mode...................................................................................................................... 193
9.4.6. Memory to memory mode................................................................................................... 193
9.4.7. Channel configuration......................................................................................................... 193
9.4.8. Interrupt............................................................................................................................... 194
9.4.9. DMA request mapping ........................................................................................................ 194
9.5. Register definition ................................................................................................... 198
9.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 198
9.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 199
9.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 199
9.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 201

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9.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 202
9.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 202
10. Debug (DBG) .....................................................................................................204
10.1. Overview............................................................................................................... 204
10.2. JTAG/SW function overview................................................................................ 204
10.2.1. Switch JTAG or SW interface ............................................................................................. 204
10.2.2. Pin assignment ................................................................................................................... 204
10.2.3. JTAG daisy chained structure............................................................................................. 205
10.2.4. Debug reset ........................................................................................................................ 205
10.2.5. JEDEC-106 ID code ........................................................................................................... 205
10.3. Debug hold function overview ............................................................................ 205
10.3.1. Debug support for power saving mode............................................................................... 205
10.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN ............................................ 206
10.4. Register definition................................................................................................ 207
10.4.1. ID code register (DBG_ID).................................................................................................. 207
10.4.2. Control register (DBG_CTL) ............................................................................................... 207
11. Analog-to-digital converter (ADC)................................................................... 211
11.1. Overview................................................................................................................211
11.2. Characteristics......................................................................................................211
11.3. Pins and internal signals..................................................................................... 212
11.4. Function overview................................................................................................ 213
11.4.1. Foreground calibration function.......................................................................................... 213
11.4.2. ADC clock ........................................................................................................................... 214
11.4.3. ADC enable......................................................................................................................... 214
11.4.4. Routine sequence............................................................................................................... 214
11.4.5. Operation modes ................................................................................................................ 214
11.4.6. Conversion result threshold monitor function ..................................................................... 217
11.4.7. Data storage mode ............................................................................................................. 217
11.4.8. Sample time configuration.................................................................................................. 218
11.4.9. External trigger configuration.............................................................................................. 218
11.4.10. DMA request ................................................................................................................... 219
11.4.11. ADC internal channels .................................................................................................... 219
11.5. ADC sync mode.................................................................................................... 220
11.5.1. Free mode........................................................................................................................... 221
11.5.2. Routine parallel mode ......................................................................................................... 221
11.5.3. Routine follow-up fast mode ............................................................................................... 221
11.5.4. Routine follow-up slow mode.............................................................................................. 222
11.6. ADC interrupts...................................................................................................... 223

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11.7. Register definition................................................................................................ 224
11.7.1. Status register (ADC_STAT) ............................................................................................... 224
11.7.2. Control register 0 (ADC_CTL0) .......................................................................................... 225
11.7.3. Control register 1 (ADC_CTL1) .......................................................................................... 226
11.7.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 228
11.7.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 229
11.7.6. Watchdog high threshold register (ADC_WDHT) ............................................................... 230
11.7.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 231
11.7.8. Routine sequence register 0 (ADC_RSQ0)........................................................................ 231
11.7.9. Routine sequence register 1 (ADC_RSQ1)........................................................................ 232
11.7.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 232
11.7.11. Routine data register (ADC_RDATA).............................................................................. 233
12. Digital-to-analog converter (DAC) ...................................................................234
12.1. Overview............................................................................................................... 234
12.2. Characteristics..................................................................................................... 234
12.3. Function overview................................................................................................ 235
12.3.1. DAC enable......................................................................................................................... 235
12.3.2. DAC output buffer ............................................................................................................... 236
12.3.3. DAC data configuration....................................................................................................... 236
12.3.4. DAC trigger ......................................................................................................................... 236
12.3.5. DAC workflow ..................................................................................................................... 236
12.3.6. DAC noise wave ................................................................................................................. 237
12.3.7. DAC output calculate .......................................................................................................... 238
12.3.8. DMA function....................................................................................................................... 238
12.3.9. DAC concurrent conversion................................................................................................ 238
12.4. Register definition................................................................................................ 239
12.4.1. Control register (DAC_CTL) ............................................................................................... 239
12.4.2. Software trigger register (DAC_SWT) ................................................................................ 241
12.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)....................................... 242
12.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ......................................... 242
12.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)........................................... 243
12.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)....................................... 243
12.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) ......................................... 244
12.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)........................................... 244
12.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH)............ 245
12.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) ........... 245
12.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ............ 246
12.4.12. DAC0 data output register (DAC0_DO) .......................................................................... 246
12.4.13. DAC1 data output register (DAC1_DO) .......................................................................... 247
13. Watchdog timer (WDGT) ..................................................................................248

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13.1. Free watchdog timer (FWDGT)............................................................................ 248
13.1.1. Overview ............................................................................................................................. 248
13.1.2. Characteristics .................................................................................................................... 248
13.1.3. Function overview ............................................................................................................... 248
13.1.4. Register definition ............................................................................................................... 251
13.2. Window watchdog timer (WWDGT)..................................................................... 254
13.2.1. Overview ............................................................................................................................. 254
13.2.2. Characteristics .................................................................................................................... 254
13.2.3. Function overview ............................................................................................................... 254
13.2.4. Register definition ............................................................................................................... 257
14. Real-time Clock (RTC) ......................................................................................259
14.1. Overview ............................................................................................................... 259
14.2. Characteristics..................................................................................................... 259
14.3. Function overview................................................................................................ 259
14.3.1. RTC reset............................................................................................................................ 260
14.3.2. RTC reading........................................................................................................................ 260
14.3.3. RTC configuration ............................................................................................................... 260
14.3.4. RTC flag assertion .............................................................................................................. 261
14.4. Register definition................................................................................................ 263
14.4.1. RTC interrupt enable register (RTC_INTEN)...................................................................... 263
14.4.2. RTC control register (RTC_CTL) ........................................................................................ 263
14.4.3. RTC prescaler high register (RTC_PSCH) ......................................................................... 264
14.4.4. RTC prescaler low register (RTC_PSCL) ........................................................................... 265
14.4.5. RTC divider high register (RTC_DIVH)............................................................................... 265
14.4.6. RTC divider low register (RTC_DIVL)................................................................................. 265
14.4.7. RTC counter high register (RTC_CNTH)............................................................................ 266
14.4.8. RTC counter low register (RTC_CNTL).............................................................................. 266
14.4.9. RTC alarm high register (RTC_ALRMH) ............................................................................ 267
14.4.10. RTC alarm low register (RTC_ALRML) .......................................................................... 267
15. TIMER ................................................................................................................268
15.1. Advanced timer (TIMERx, x=0, 7)........................................................................ 269
15.1.1. Overview ............................................................................................................................. 269
15.1.2. Characteristics .................................................................................................................... 269
15.1.3. Block diagram ..................................................................................................................... 269
15.1.4. Function overview ............................................................................................................... 270
15.1.5. Register definition ............................................................................................................... 298
15.2. General level0 timer (TIMERx, x=1, 2, 3, 4)......................................................... 325
15.2.1. Overview ............................................................................................................................. 325
15.2.2. Characteristics .................................................................................................................... 325
15.2.3. Block diagram ..................................................................................................................... 325

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15.2.4. Function overview ............................................................................................................... 326
15.2.5. Register definition ............................................................................................................... 342
15.3. General level1 timer (TIMERx, x=8, 11)............................................................... 364
15.3.1. Overview ............................................................................................................................. 364
15.3.2. Characteristics .................................................................................................................... 364
15.3.3. Block diagram ..................................................................................................................... 365
15.3.4. Function overview ............................................................................................................... 365
15.3.5. Register definition ............................................................................................................... 381
15.4. General level2 timer (TIMERx, x=9, 10, 12, 13) ................................................... 394
15.4.1. Overview ............................................................................................................................. 394
15.4.2. Characteristics .................................................................................................................... 394
15.4.3. Block diagram ..................................................................................................................... 394
15.4.4. Function overview ............................................................................................................... 395
15.4.5. Register definition ............................................................................................................... 406
15.5. Basic timer (TIMERx, x=5, 6)................................................................................ 417
15.5.1. Overview ............................................................................................................................. 417
15.5.2. Characteristics .................................................................................................................... 417
15.5.3. Block diagram ..................................................................................................................... 417
15.5.4. Function overview ............................................................................................................... 417
15.5.5. Register definition ............................................................................................................... 422
16. Universal synchronous/asynchronous receiver /transmitter (USART)........428
16.1. Overview ............................................................................................................... 428
16.2. Characteristics..................................................................................................... 428
16.3. Function overview................................................................................................ 429
16.3.1. USART frame format .......................................................................................................... 430
16.3.2. Baud rate generation .......................................................................................................... 431
16.3.3. USART transmitter.............................................................................................................. 431
16.3.4. USART receiver .................................................................................................................. 432
16.3.5. Use DMA for data buffer access ......................................................................................... 434
16.3.6. Hardware flow control ......................................................................................................... 435
16.3.7. Multi-processor communication .......................................................................................... 437
16.3.8. LIN mode ............................................................................................................................ 437
16.3.9. Synchronous mode............................................................................................................. 438
16.3.10. IrDA SIR ENDEC mode .................................................................................................. 439
16.3.11. Half-duplex communication mode .................................................................................. 441
16.3.12. Smartcard (ISO7816-3) mode......................................................................................... 441
16.3.13. USART interrupts ............................................................................................................ 442
16.4. Register definition................................................................................................ 444
16.4.1. Status register (USART_STAT) .......................................................................................... 444
16.4.2. Data register (USART_DATA)............................................................................................. 446

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16.4.3. Baud rate register (USART_BAUD).................................................................................... 446
16.4.4. Control register 0 (USART_CTL0)...................................................................................... 447
16.4.5. Control register 1 (USART_CTL1)...................................................................................... 449
16.4.6. Control register 2 (USART_CTL2)...................................................................................... 450
16.4.7. Guard time and prescaler register (USART_GP) ............................................................... 452
17. Inter-integrated circuit interface (I2C).............................................................454
17.1. Overview............................................................................................................... 454
17.2. Characteristics..................................................................................................... 454
17.3. Function overview................................................................................................ 454
17.3.1. SDA and SCL lines ............................................................................................................. 455
17.3.2. Data validation .................................................................................................................... 456
17.3.3. START and STOP signal .................................................................................................... 456
17.3.4. Clock synchronization......................................................................................................... 457
17.3.5. Arbitration............................................................................................................................ 457
17.3.6. I2C communication flow...................................................................................................... 458
17.3.7. Programming model ........................................................................................................... 459
17.3.8. SCL line stretching.............................................................................................................. 468
17.3.9. Use DMA for data transfer .................................................................................................. 469
17.3.10. Packet error checking ..................................................................................................... 469
17.3.11. SMBus support ............................................................................................................... 470
17.3.12. Status, errors and interrupts ........................................................................................... 471
17.4. Register definition................................................................................................ 473
17.4.1. Control register 0 (I2C_CTL0) ............................................................................................ 473
17.4.2. Control register 1 (I2C_CTL1) ............................................................................................ 475
17.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 476
17.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 476
17.4.5. Transfer buffer register (I2C_DATA) ................................................................................... 477
17.4.6. Transfer status register 0 (I2C_STAT0) .............................................................................. 477
17.4.7. Transfer status register 1 (I2C_STAT1) .............................................................................. 480
17.4.8. Clock configure register (I2C_CKCFG) .............................................................................. 481
17.4.9. Rise time register (I2C_RT) ................................................................................................ 482
18. Serial peripheral interface / Inter-IC sound (SPI / I2S) ...................................483
18.1. Overview............................................................................................................... 483
18.2. Characteristics..................................................................................................... 483
18.2.1. SPI characteristics .............................................................................................................. 483
18.2.2. I2S characteristics .............................................................................................................. 483
18.3. SPI function overview.......................................................................................... 484
18.3.1. SPI block diagram............................................................................................................... 484
18.3.2. SPI signal description ......................................................................................................... 484
18.3.3. SPI clock timing and data format ........................................................................................ 485

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18.3.4. NSS function ....................................................................................................................... 485
18.3.5. SPI operation modes .......................................................................................................... 487
18.3.6. DMA function....................................................................................................................... 491
18.3.7. CRC function....................................................................................................................... 491
18.3.8. SPI interrupts ...................................................................................................................... 492
18.4. I2S function overview .......................................................................................... 493
18.4.1. I2S block diagram ............................................................................................................... 493
18.4.2. I2S signal description.......................................................................................................... 494
18.4.3. I2S audio standards ............................................................................................................ 494
18.4.4. I2S clock ............................................................................................................................. 502
18.4.5. Operation ............................................................................................................................ 503
18.4.6. DMA function....................................................................................................................... 507
18.4.7. I2S interrupts....................................................................................................................... 507
18.5. Register definition................................................................................................ 509
18.5.1. Control register 0 (SPI_CTL0) ............................................................................................ 509
18.5.2. Control register 1 (SPI_CTL1) .............................................................................................511
18.5.3. Status register (SPI_STAT)................................................................................................. 512
18.5.4. Data register (SPI_DATA) ................................................................................................... 513
18.5.5. CRC polynomial register (SPI_CRCPOLY) ........................................................................ 514
18.5.6. RX CRC register (SPI_RCRC) ........................................................................................... 514
18.5.7. TX CRC register (SPI_TCRC) ............................................................................................ 515
18.5.8. I2S control register (SPI_I2SCTL) ...................................................................................... 515
18.5.9. I2S clock prescaler register (SPI_I2SPSC) ........................................................................ 517
19. Secure digital input/output interface (SDIO) ..................................................519
19.1. Overview............................................................................................................... 519
19.2. Characteristics..................................................................................................... 519
19.3. SDIO bus topology............................................................................................... 519
19.4. SDIO functional description ................................................................................ 522
19.4.1. SDIO adapter ...................................................................................................................... 522
19.4.2. AHB interface...................................................................................................................... 526
19.5. Card functional description................................................................................. 528
19.5.1. Card registers ..................................................................................................................... 528
19.5.2. Commands.......................................................................................................................... 529
19.5.3. Responses .......................................................................................................................... 540
19.5.4. Data packets format............................................................................................................ 544
19.5.5. Two status fields of the card ............................................................................................... 545
19.6. Programming sequence....................................................................................... 553
19.6.1. Card identification ............................................................................................................... 553
19.6.2. No data commands............................................................................................................. 555
19.6.3. Single block or multiple block write..................................................................................... 555

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19.6.4. Single block or multiple block read ..................................................................................... 556
19.6.5. Stream write and stream read (MMC only)......................................................................... 557
19.6.6. Erase................................................................................................................................... 559
19.6.7. Bus width selection ............................................................................................................. 560
19.6.8. Protection management...................................................................................................... 560
19.6.9. Card Lock/Unlock operation ............................................................................................... 560
19.7. Specific operations.............................................................................................. 563
19.7.1. SD I/O specific operations .................................................................................................. 563
19.7.2. CE-ATA specific operations................................................................................................. 566
19.8. Register definition................................................................................................ 568
19.8.1. Power control register (SDIO_PWRCTL) ........................................................................... 568
19.8.2. Clock control register (SDIO_CLKCTL) .............................................................................. 568
19.8.3. Command argument register (SDIO_CMDAGMT) ............................................................. 569
19.8.4. Command control register (SDIO_CMDCTL) ..................................................................... 570
19.8.5. Command index response register (SDIO_RSPCMDIDX)................................................. 571
19.8.6. Response register (SDIO_RESPx x=0..3).......................................................................... 572
19.8.7. Data timeout register (SDIO_DATATO) .............................................................................. 573
19.8.8. Data length register (SDIO_DATALEN) .............................................................................. 573
19.8.9. Data control register (SDIO_DATACTL) ............................................................................. 574
19.8.10. Data counter register (SDIO_DATACNT)........................................................................ 575
19.8.11. Status register (SDIO_STAT).......................................................................................... 576
19.8.12. Interrupt clear register (SDIO_INTC) .............................................................................. 577
19.8.13. Interrupt enable register (SDIO_INTEN)......................................................................... 578
19.8.14. FIFO counter register (SDIO_FIFOCNT)........................................................................ 580
19.8.15. FIFO data register (SDIO_FIFO) .................................................................................... 581
20. External memory controller (EXMC) ...............................................................582
20.1. Overview ............................................................................................................... 582
20.2. Characteristics ..................................................................................................... 582
20.3. Function overview................................................................................................ 582
20.3.1. Block diagram ..................................................................................................................... 582
20.3.2. Basic regulation of EXMC access....................................................................................... 583
20.3.3. External device address mapping....................................................................................... 584
20.3.4. NOR/PSRAM controller ...................................................................................................... 587
20.3.5. NAND Flash or PC Card controller ..................................................................................... 606
20.4. Register definition................................................................................................ 612
20.4.1. NOR/PSRAM controller registers ....................................................................................... 612
20.4.2. NAND Flash/PC Card controller registers .......................................................................... 616
21. Controller area network (CAN) ........................................................................623
21.1. Overview ............................................................................................................... 623

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21.2. Characteristics ..................................................................................................... 623
21.3. Function overview................................................................................................ 624
21.3.1. Working mode..................................................................................................................... 624
21.3.2. Communication modes ....................................................................................................... 625
21.3.3. Data transmission ............................................................................................................... 626
21.3.4. Data reception..................................................................................................................... 628
21.3.5. Filtering function.................................................................................................................. 630
21.3.6. Time-triggered communication ........................................................................................... 633
21.3.7. Communication parameters................................................................................................ 633
21.3.8. Error flags ........................................................................................................................... 635
21.3.9. CAN interrupts .................................................................................................................... 635
21.4. Register definition................................................................................................ 637
21.4.1. Control register (CAN_CTL) ............................................................................................... 637
21.4.2. Status register (CAN_STAT) ............................................................................................... 638
21.4.3. Transmit status register (CAN_TSTAT) .............................................................................. 640
21.4.4. Receive message FIFO0 register (CAN_RFIFO0) ............................................................. 643
21.4.5. Receive message FIFO1 register (CAN_RFIFO1) ............................................................. 644
21.4.6. Interrupt enable register (CAN_INTEN).............................................................................. 644
21.4.7. Error register (CAN_ERR) .................................................................................................. 646
21.4.8. Bit timing register (CAN_BT) .............................................................................................. 647
21.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) .................................................. 648
21.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2) ............................................. 649
21.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2) ......................................... 649
21.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) ......................................... 650
21.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1) .............................. 650
21.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) ............................. 651
21.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) ......................... 652
21.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) ......................... 652
21.4.17. Filter control register (CAN_FCTL) (Just for CAN0) ....................................................... 653
21.4.18. Filter mode configuration register (CAN_FMCFG) (Just for CAN0) ............................... 654
21.4.19. Filter scale configuration register (CAN_FSCFG) (Just for CAN0)................................. 654
21.4.20. Filter associated FIFO register (CAN_FAFIFO) (Just for CAN0).................................... 655
21.4.21. Filter working register (CAN_FW) (Just for CAN0) ......................................................... 655
21.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) (Just for CAN0) ..................... 656
22. Ethernet (ENET) ................................................................................................657
22.1. Overview ............................................................................................................... 657
22.2. Characteristics ..................................................................................................... 657
22.2.1. Block diagram ..................................................................................................................... 658
22.2.2. MAC 802.3 Ethernet packet description ............................................................................. 659
22.2.3. Ethernet signal description ................................................................................................. 660
22.3. Function overview................................................................................................ 661

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22.3.1. Interface configuration ........................................................................................................ 661
22.3.2. MAC function overview ....................................................................................................... 666
22.3.3. MAC statistics counters: MSC ............................................................................................ 677
22.3.4. Wake up management: WUM............................................................................................. 678
22.3.5. Precision time protocol: PTP .............................................................................................. 681
22.3.6. DMA controller description.................................................................................................. 685
22.3.7. Example for a typical configuration flow of Ethernet........................................................... 705
22.3.8. Ethernet interrupts .............................................................................................................. 707
22.4. Register definition................................................................................................ 709
22.4.1. MAC configuration register (ENET_MAC_CFG) ................................................................ 709
22.4.2. MAC frame filter register (ENET_MAC_FRMF)...................................................................711
22.4.3. MAC hash list high register (ENET_MAC_HLH) ................................................................ 713
22.4.4. MAC hash list low register (ENET_MAC_HLL) .................................................................. 713
22.4.5. MAC PHY control register (ENET_MAC_PHY_CTL) ......................................................... 714
22.4.6. MAC PHY data register (ENET_MAC_PHY_DATA)........................................................... 715
22.4.7. MAC flow control register (ENET_MAC_FCTL) ................................................................. 715
22.4.8. MAC flow control threshold register (ENET_MAC_FCTH) ................................................. 717
22.4.9. MAC VLAN tag register (ENET_MAC_VLT) ....................................................................... 718
22.4.10. MAC remote wakeup frame filter register (ENET_MAC_RWFF).................................... 718
22.4.11. MAC wakeup management register (ENET_MAC_WUM) ............................................. 719
22.4.12. MAC interrupt flag register (ENET_MAC_INTF)............................................................. 720
22.4.13. MAC interrupt mask register (ENET_MAC_INTMSK) .................................................... 721
22.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) .................................................. 722
22.4.15. MAC address 0 low register (ENET_MAC_ADDR0L) .................................................... 722
22.4.16. MAC address 1 high register (ENET_MAC_ADDR1H) .................................................. 723
22.4.17. MAC address 1 low register (ENET_MAC_ADDR1L) .................................................... 724
22.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) .................................................. 724
22.4.19. MAC address 2 low register (ENET_MAC_ADDR2L) .................................................... 725
22.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) .................................................. 725
22.4.21. MAC address 3 low register (ENET_MAC_ADDR3L) .................................................... 726
22.4.22. MSC control register (ENET_MSC_CTL) ....................................................................... 726
22.4.23. MSC receive interrupt flag register (ENET_MSC_RINTF) ............................................. 727
22.4.24. MSC transmit interrupt flag register (ENET_MSC_TINTF)............................................. 728
22.4.25. MSC receive interrupt mask register (ENET_MSC_RINTMSK) ..................................... 729
22.4.26. MSC transmit interrupt mask register (ENET_MSC_TINTMSK) .................................... 729
22.4.27. MSC transmitted good frames after a single collision counter register
(ENET_MSC_SCCNT)....................................................................................................................... 730
22.4.28. MSC transmitted good frames after more than a single collision counter register
(ENET_MSC_MSCCNT).................................................................................................................... 731
22.4.29. MSC transmitted good frames counter register (ENET_MSC_TGFCNT) ...................... 731
22.4.30. MSC received frames with CRC error counter register (ENET_MSC_RFCECNT) ........ 732
22.4.31. MSC received frames with alignment error counter register (ENET_MSC_RFAECNT) 732
22.4.32. MSC received good unicast frames counter register (ENET_MSC_RGUFCNT) ........... 733

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22.4.33. PTP time stamp control register (ENET_PTP_TSCTL) .................................................. 733
22.4.34. PTP subsecond increment register (ENET_PTP_SSINC).............................................. 734
22.4.35. PTP time stamp high register (ENET_PTP_TSH) .......................................................... 735
22.4.36. PTP time stamp low register (ENET_PTP_TSL) ............................................................ 735
22.4.37. PTP time stamp update high register (ENET_PTP_TSUH) ........................................... 736
22.4.38. PTP time stamp update low register (ENET_PTP_TSUL) ............................................. 736
22.4.39. PTP time stamp addend register (ENET_PTP_TSADDEND) ........................................ 737
22.4.40. PTP expected time high register (ENET_PTP_ETH) ..................................................... 737
22.4.41. PTP expected time low register (ENET_PTP_ETL) ....................................................... 737
22.4.42. DMA bus control register (ENET_DMA_BCTL) .............................................................. 738
22.4.43. DMA transmit poll enable register (ENET_DMA_TPEN) ................................................ 740
22.4.44. DMA receive poll enable register (ENET_DMA_RPEN) ................................................. 740
22.4.45. DMA receive descriptor table address register (ENET_DMA_RDTADDR) .................... 741
22.4.46. DMA transmit descriptor table address register (ENET_DMA_TDTADDR).................... 742
22.4.47. DMA status register (ENET_DMA_STAT)....................................................................... 742
22.4.48. DMA control register (ENET_DMA_CTL) ....................................................................... 746
22.4.49. DMA interrupt enable register (ENET_DMA_INTEN) ..................................................... 749
22.4.50. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT)..... 751
22.4.51. DMA current transmit descriptor address register (ENET_DMA_CTDADDR) ............... 751
22.4.52. DMA current receive descriptor address register (ENET_DMA_CRDADDR) ................ 752
22.4.53. DMA current transmit buffer address register (ENET_DMA_CTBADDR) ...................... 752
22.4.54. DMA current receive buffer address register (ENET_DMA_CRBADDR) ....................... 753
23. Universal Serial Bus full-speed device interface (USBD)..............................754
23.1. Overview ............................................................................................................... 754
23.2. Characteristics..................................................................................................... 754
23.3. Block diagram ...................................................................................................... 754
23.4. Signal description ................................................................................................ 755
23.5. Clock configuration.............................................................................................. 755
23.6. Function overview................................................................................................ 756
23.6.1. USB endpoints .................................................................................................................... 756
23.6.2. Operation procedure ........................................................................................................... 758
23.6.3. USB events and interrupts.................................................................................................. 761
23.6.4. Operation guide .................................................................................................................. 762
23.7. Register definition................................................................................................ 765
23.7.1. USBD control register (USBD_CTL)................................................................................... 765
23.7.2. USBD interrupt flag register (USBD_INTF) ........................................................................ 766
23.7.3. USBD status register (USBD_STAT) .................................................................................. 767
23.7.4. USBD device address register (USBD_DADDR) ............................................................... 768
23.7.5. USBD buffer address register (USBD_BADDR)................................................................. 768
23.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7] ............................ 769

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23.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in
[0..7] 771
23.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in
[0..7] 771
23.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in [0..7]
771
23.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x can be in
[0..7] 772
24. Universal serial bus full-speed interface (USBFS).........................................773
24.1. Overview............................................................................................................... 773
24.2. Characteristics..................................................................................................... 773
24.3. Block diagram ...................................................................................................... 774
24.4. Signal description................................................................................................ 774
24.5. Function overview................................................................................................ 774
24.5.1. USBFS clocks and working modes..................................................................................... 774
24.5.2. USB host function ............................................................................................................... 776
24.5.3. USB device function ........................................................................................................... 778
24.5.4. OTG function overview ....................................................................................................... 779
24.5.5. Data FIFO ........................................................................................................................... 780
24.5.6. Operation guide .................................................................................................................. 783
24.6. Interrupts.............................................................................................................. 787
24.7. Register definition................................................................................................ 789
24.7.1. Global control and status registers ..................................................................................... 789
24.7.2. Host control and status registers ........................................................................................ 810
24.7.3. Device control and status registers .................................................................................... 822
24.7.4. Power and clock control register (USBFS_PWRCLKCTL)................................................. 846
25. Appendix ...........................................................................................................848
25.1. List of abbreviations used in register................................................................. 848
25.2. List of terms.......................................................................................................... 848
25.3. Available peripherals........................................................................................... 849
26. Revision history................................................................................................850

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List of Figures
Figure 1-1. The structure of the Cortex®-M3 processor......................................................................... 30
Figure 1-2. GD32F10x Medium-density series system architecture..................................................... 32
Figure 1-3. GD32F10x High-density series system architecture .......................................................... 33
Figure 1-4. GD32F10x Extra-density series system architecture ......................................................... 34
Figure 1-5. GD32F10x Connectivity line series system architecture ................................................... 35
Figure 2-1. Process of page erase operation.......................................................................................... 47
Figure 2-2. Process of mass erase operation......................................................................................... 49
Figure 2-3. Process of word program operation .................................................................................... 50
Figure 3-1. Power supply overview ......................................................................................................... 65
Figure 3-2. Waveform of the POR / PDR.................................................................................................. 67
Figure 3-3. Waveform of the LVD threshold ........................................................................................... 67
Figure 5-1. The system reset circuit ........................................................................................................ 80
Figure 5-2. Clock tree ................................................................................................................................ 81
Figure 5-3. HXTAL clock source............................................................................................................... 82
Figure 5-4. HXTAL clock source in bypass mode .................................................................................. 83
Figure 5-5. The system reset circuit.......................................................................................................111
Figure 5-6. Clock tree ...............................................................................................................................112
Figure 5-7. HXTAL clock source..............................................................................................................113
Figure 5-8. HXTAL clock source in bypass mode .................................................................................114
Figure 6-1. Block diagram of EXTI......................................................................................................... 148
Figure 7-1. Basic structure of of a general-pupose I/O........................................................................ 154
Figure 7-2. Basic structure of Input configuration............................................................................... 155
Figure 7-3. Basic structure of Output configuration............................................................................ 156
Figure 7-4. Basic structure of Analog configuration ........................................................................... 156
Figure 7-5. Basic structure of Alternate function configuration......................................................... 157
Figure 8-1. Block diagram of CRC management unit .......................................................................... 185
Figure 9-1. Block diagram of DMA......................................................................................................... 190
Figure 9-2. Handshake mechanism ....................................................................................................... 192
Figure 9-3. DMA interrupt logic.............................................................................................................. 194
Figure 9-4. DMA0 request mapping ....................................................................................................... 195
Figure 9-5. DMA1 request mapping ....................................................................................................... 196
Figure 11-1. ADC module block diagram .............................................................................................. 213
Figure 11-2. Single operation mode....................................................................................................... 214
Figure 11-3. Continuous operation mode ............................................................................................. 215
Figure 11-4. Scan operation mode, continuous disable...................................................................... 216
Figure 11-5. Scan operation mode, continuous enable....................................................................... 216
Figure 11-6. Discontinuous operation mode ........................................................................................ 217
Figure 11-7. 12-bit Data storage mode .................................................................................................. 218
Figure 11-8. ADC sync block diagram................................................................................................... 220
Figure 11-9. Routine parallel mode on 10 channels............................................................................. 221

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Figure 11-10. Routine follow-up fast mode (the CTN bit of ADCs are set)........................................ 222
Figure 11-11. Routine follow-up slow mode ......................................................................................... 222
Figure 12-1. DAC block diagram ............................................................................................................ 235
Figure 12-2. DAC LFSR algorithm.......................................................................................................... 237
Figure 12-3. DAC triangle noise wave ................................................................................................... 237
Figure 13-1. Free watchdog block diagram .......................................................................................... 249
Figure 13-2. Window watchdog timer block diagram .......................................................................... 255
Figure 13-3. Window watchdog timing diagram................................................................................... 256
Figure 14-1. Block diagram of RTC........................................................................................................ 260
Figure 15-1. Advanced timer block diagram......................................................................................... 270
Figure 15-2. Timing chart of internal clock divided by 1 ..................................................................... 271
Figure 15-3. Timing chart of PSC value change from 0 to 2 ............................................................... 272
Figure 15-4. Timing chart of up counting mode, PSC=0/2 .................................................................. 273
Figure 15-5. Timing chart of up counting mode, change TIMERx_CAR ongoing............................. 273
Figure 15-6. Timing chart of down counting mode, PSC=0/2 ............................................................. 274
Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR ongoing........................ 275
Figure 15-8. Timing chart of center-aligned counting mode............................................................... 276
Figure 15-9. Repetition counter timing chart of center-aligned counting mode............................... 277
Figure 15-10. Repetition counter timing chart of up counting mode ................................................. 277
Figure 15-11. Repetition counter timing chart of down counting mode ............................................ 278
Figure 15-12. Channel input capture principle ..................................................................................... 279
Figure 15-13. channel output compare principle (with complementary output, x=0,1,2) ................ 280
Figure 15-14. channel output compare principle (CH3_O) .................................................................. 280
Figure 15-15. Output-compare in three modes..................................................................................... 282
Figure 15-16. Timing chart of EAPWM................................................................................................... 283
Figure 15-17. Timing chart of CAPWM .................................................................................................. 283
Figure 15-18. Channel output complementary PWM with dead-time insertion................................. 286
Figure 15-19. Output behavior in response to a break (The break high active)................................ 287
Figure 15-20. Counter behavior with CI0FE0 polarity non-inverted in mode 2 ................................. 288
Figure 15-21. Counter behavior with CI0FE0 polarity inverted in mode 2 ......................................... 288
Figure 15-22. Hall sensor is used to BLDC motor................................................................................ 289
Figure 15-23. Hall sensor timing between two timers.......................................................................... 290
Figure 15-24. Restart mode .................................................................................................................... 291
Figure 15-25. Pause mode ...................................................................................................................... 292
Figure 15-26. Event mode ....................................................................................................................... 292
Figure 15-27. Single pulse mode, TIMERx_CHxCV = 4, TIMERx_CAR=99 ........................................ 293
Figure 15-28. Timer0 master/slave mode timer example..................................................................... 294
Figure 15-29. Triggering TIMER0 with enable signal of TIMER2......................................................... 295
Figure 15-30. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input............................................ 296
Figure 15-31. General Level 0 timer block diagram ............................................................................. 326
Figure 15-32. Timing chart of internal clock divided by 1................................................................... 327
Figure 15-33. Timing chart of PSC value change from 0 to 2 ............................................................. 328
Figure 15-34. Timing chart of up counting mode, PSC=0/2 ................................................................ 329

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Figure 15-35. Timing chart of up counting mode, change TIMERx_CAR ongoing........................... 329
Figure 15-36. Timing chart of down counting mode, PSC=0/2 ........................................................... 330
Figure 15-37. Timing chart of down counting mode, change TIMERx_CAR ongoing...................... 331
Figure 15-38. Timing chart of center-aligned counting mode............................................................. 332
Figure 15-39. Channel input capture principle ..................................................................................... 333
Figure 15-40. channel output compare principle (x=0,1,2,3)............................................................... 334
Figure 15-41. Output-compare in three modes..................................................................................... 335
Figure 15-42. EAPWM timechart ............................................................................................................ 336
Figure 15-43. CAPWM timechart ............................................................................................................ 337
Figure 15-44. Restart mode .................................................................................................................... 339
Figure 15-45. Pause mode ...................................................................................................................... 339
Figure 15-46. Event mode ....................................................................................................................... 340
Figure 15-47. General level1 timer block diagram................................................................................ 365
Figure 15-48. Timing chart of internal clock divided by 1................................................................... 366
Figure 15-49. Timing chart of PSC value change from 0 to 2 ............................................................. 367
Figure 15-50. Timing chart of up counting mode, PSC=0/2 ................................................................ 368
Figure 15-51. Timing chart of up counting mode, change TIMERx_CAR ongoing........................... 368
Figure 15-52. Timing chart of down counting mode, PSC=0/2 ........................................................... 369
Figure 15-53. Timing chart of down counting mode, change TIMERx_CAR ongoing...................... 370
Figure 15-54. Timing chart of center-aligned counting mode............................................................. 371
Figure 15-55. Channel input capture principle ..................................................................................... 372
Figure 15-56. channel output compare principle (x=0,1)..................................................................... 373
Figure 15-57. Output-compare under three modes.............................................................................. 374
Figure 15-58. EAPWM timechart ............................................................................................................ 375
Figure 15-59. CAPWM timechart ............................................................................................................ 376
Figure 15-60. Restart mode .................................................................................................................... 377
Figure 15-61. Pause mode ...................................................................................................................... 378
Figure 15-62. Event mode ....................................................................................................................... 378
Figure 15-63. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 .......................................... 379
Figure 15-64. General level2 timer block diagram................................................................................ 395
Figure 15-65. Timing chart of internal clock divided by 1................................................................... 396
Figure 15-66. Timing chart of PSC value change from 0 to 2 ............................................................. 396
Figure 15-67. Up-counter timechart, PSC=0/2 ...................................................................................... 397
Figure 15-68. Up-counter timechart, change TIMERx_CAR on the go............................................... 398
Figure 15-69. Down-counter timechart, PSC=0/2 ................................................................................. 399
Figure 15-70. Down-counter timechart, change TIMERx_CAR on the go.......................................... 400
Figure 15-71. Center-aligned counter timechart................................................................................... 401
Figure 15-72. Channels input capture principle ................................................................................... 402
Figure 15-73. Channel output compare principle (x=0) ....................................................................... 403
Figure 15-74. Output-compare under three modes.............................................................................. 404
Figure 15-75. Basic timer block diagram .............................................................................................. 417
Figure 15-76. Timing chart of internal clock divided by 1................................................................... 418
Figure 15-77. Timing chart of PSC value change from 0 to 2 ............................................................. 419