GigaDevice Semiconductor GD32F10 Series User manual

GigaDevice Semiconductor Inc.
GD32F10x
Arm® Cortex®-M3 32-bit MCU
User Manual
Revision 2.6
( Jun. 2022 )

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................18
List of Tables ................................................................................................................25
1. System and memory architecture ........................................................................29
1.1. Arm®Cortex®-M3 processor ..................................................................................... 29
1.2. System architecture .................................................................................................. 30
1.3. Memory map .............................................................................................................. 35
1.3.1. Bit-banding............................................................................................................................ 39
1.3.2. On-chip SRAM memory........................................................................................................ 40
1.3.3. On-chip flash memory overview ........................................................................................... 40
1.4. Boot configuration..................................................................................................... 40
1.5. Device electronic signature...................................................................................... 41
1.5.1. Memory density information.................................................................................................. 42
1.5.2. Unique device ID (96 bits) .................................................................................................... 42
1.6. System configuration registers................................................................................ 43
2. Flash memory controller (FMC)............................................................................44
2.1. Overview .................................................................................................................... 44
2.2. Characteristics........................................................................................................... 44
2.3. Function overview..................................................................................................... 44
2.3.1. Flash memory architecture ................................................................................................... 44
2.3.2. Read operations ................................................................................................................... 45
2.3.3. Unlock the FMC_CTLx registers........................................................................................... 46
2.3.4. Page erase............................................................................................................................ 46
2.3.5. Mass erase ........................................................................................................................... 47
2.3.6. Main flash programming ....................................................................................................... 49
2.3.7. Option bytes Erase ............................................................................................................... 50
2.3.8. Option bytes modify .............................................................................................................. 51
2.3.9. Option bytes description ....................................................................................................... 51
2.3.10. Page erase/program protection ............................................................................................ 53
2.3.11. Security protection ................................................................................................................ 53
2.4. Register definition..................................................................................................... 54
2.4.1. Wait state register (FMC_WS).............................................................................................. 54
2.4.2. Unlock key register 0 (FMC_KEY0)...................................................................................... 54
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 55

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2.4.4. Status register 0 (FMC_STAT0)............................................................................................ 55
2.4.5. Control register 0 (FMC_CTL0) ............................................................................................ 56
2.4.6. Address register 0 (FMC_ADDR0) ....................................................................................... 57
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 58
2.4.8. Erase/Program Protection register (FMC_WP) .................................................................... 58
2.4.9. Unlock key register 1(FMC_KEY1)....................................................................................... 59
2.4.10. Status register 1 (FMC_STAT1)............................................................................................ 59
2.4.11. Control register 1 (FMC_CTL1) ............................................................................................ 60
2.4.12. Address register 1 (FMC_ADDR1) ....................................................................................... 61
2.4.13. Wait state enable register (FMC_WSEN) ............................................................................. 62
2.4.14. Product ID register (FMC_PID)............................................................................................. 62
3. Power management unit (PMU) ............................................................................64
3.1. Overview .................................................................................................................... 64
3.2. Characteristics........................................................................................................... 64
3.3. Function overview..................................................................................................... 64
3.3.1. Backup domain ..................................................................................................................... 65
3.3.2. VDD / VDDA power domain ...................................................................................................... 66
3.3.3. 1.2V power domain............................................................................................................... 68
3.3.4. Power saving modes ............................................................................................................ 68
3.4. Register definition..................................................................................................... 71
3.4.1. Control register (PMU_CTL) ................................................................................................. 71
3.4.2. Control and status register (PMU_CS) ................................................................................. 72
4. Backup registers (BKP).........................................................................................74
4.1. Overview .................................................................................................................... 74
4.2. Characteristics........................................................................................................... 74
4.3. Function overview..................................................................................................... 74
4.3.1. RTC clock calibration ............................................................................................................ 74
4.3.2. Tamper detection .................................................................................................................. 75
4.4. Register definition..................................................................................................... 76
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) .................................................................. 76
4.4.2. RTC signal output control register (BKP_OCTL).................................................................. 76
4.4.3. Tamper pin control register (BKP_TPCTL) ........................................................................... 77
4.4.4. Tamper control and status register (BKP_TPCS) ................................................................. 77
5. Reset and clock unit (RCU)...................................................................................79
Medium-, High- and extra-density reset and clock control unit (RCU)............................. 79
5.1. Reset control unit (RCTL) ......................................................................................... 79
5.1.1. Overview ............................................................................................................................... 79
5.1.2. Function overview ................................................................................................................. 79

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5.2. Clock control unit (CCTL) ......................................................................................... 80
5.2.1. Overview ............................................................................................................................... 80
5.2.2. Characteristics ...................................................................................................................... 82
5.2.3. Function overview ................................................................................................................. 82
5.3. Register definition..................................................................................................... 86
5.3.1. Control register (RCU_CTL) ................................................................................................. 86
5.3.2. Clock configuration register 0 (RCU_CFG0) ........................................................................ 87
5.3.3. Clock interrupt register (RCU_INT) ...................................................................................... 91
5.3.4. APB2 reset register (RCU_APB2RST) ................................................................................. 93
5.3.5. APB1 reset register (RCU_APB1RST) ................................................................................. 96
5.3.6. AHB enable register (RCU_AHBEN) .................................................................................... 99
5.3.7. APB2 enable register (RCU_APB2EN) .............................................................................. 100
5.3.8. APB1 enable register (RCU_APB1EN) .............................................................................. 102
5.3.9. Backup domain control register (RCU_BDCTL) ................................................................. 105
5.3.10. Reset source/clock register (RCU_RSTSCK) .................................................................... 107
5.3.11. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 108
Connectivity line devices: Reset and clock control unit (RCU).......................................110
5.4. Reset control unit (RCTL) ........................................................................................110
5.4.1. Overview ..............................................................................................................................110
5.4.2. Function overview ................................................................................................................110
5.5. Clock control unit (CCTL) ........................................................................................111
5.5.1. Overview ..............................................................................................................................111
5.5.2. Characteristics .....................................................................................................................113
5.5.3. Function overview ................................................................................................................113
5.6. Register definition....................................................................................................118
5.6.1. Control register (RCU_CTL) ................................................................................................118
5.6.2. Clock configuration register 0 (RCU_CFG0) ...................................................................... 120
5.6.3. Clock interrupt register (RCU_INT) .................................................................................... 123
5.6.4. APB2 reset register (RCU_APB2RST) ............................................................................... 126
5.6.5. APB1 reset register (RCU_APB1RST) ............................................................................... 128
5.6.6. AHB enable register (RCU_AHBEN) .................................................................................. 131
5.6.7. APB2 enable register (RCU_APB2EN) .............................................................................. 133
5.6.8. APB1 enable register (RCU_APB1EN) .............................................................................. 135
5.6.9. Backup domain control register (RCU_BDCTL) ................................................................. 137
5.6.10. Reset source/clock register (RCU_RSTSCK) .................................................................... 138
5.6.11. AHB reset register (RCU_AHBRST)................................................................................... 140
5.6.12. Clock configuration register 1 (RCU_CFG1) ...................................................................... 141
5.6.13. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 143
6. Interrupt/event controller (EXTI).........................................................................144
6.1. Overview .................................................................................................................. 144

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6.2. Characteristics......................................................................................................... 144
6.3. Function overview ................................................................................................... 144
6.4. External interrupt and event (EXTI) block diagram ............................................... 148
6.5. External Interrupt and Event function overview.................................................... 149
6.6. Register definition ................................................................................................... 150
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 150
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 150
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 151
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 151
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 152
6.6.6. Pending register (EXTI_PD) ............................................................................................... 152
7. General-purpose and alternate-function I/Os (GPIO and AFIO).......................153
7.1. Overview .................................................................................................................. 153
7.2. Characteristics......................................................................................................... 153
7.3. Function overview ................................................................................................... 153
7.3.1. GPIO pin configuration ....................................................................................................... 154
7.3.2. External interrupt/event lines .............................................................................................. 155
7.3.3. Alternate functions (AF) ...................................................................................................... 155
7.3.4. Input configuration .............................................................................................................. 155
7.3.5. Output configuration ........................................................................................................... 155
7.3.6. Analog configuration ........................................................................................................... 156
7.3.7. Alternate function (AF) configuration .................................................................................. 156
7.3.8. IO pin function selection ..................................................................................................... 157
7.3.9. GPIO locking function ......................................................................................................... 158
7.4. Remapping function I/O and debug configuration ................................................ 158
7.4.1. Introduction ......................................................................................................................... 158
7.4.2. Main features ...................................................................................................................... 158
7.4.3. JTAG/SWD alternate function remapping........................................................................... 158
7.4.4. ADC AF remapping............................................................................................................. 159
7.4.5. TIMER AF remapping ......................................................................................................... 160
7.4.6. USART AF remapping ........................................................................................................ 161
7.4.7. I2C0 AF remapping ............................................................................................................. 162
7.4.8. SPI0/SPI2/I2S AF remapping ............................................................................................. 162
7.4.9. CAN0/1 AF remapping........................................................................................................ 163
7.4.10. Ethernet AF remapping....................................................................................................... 164
7.4.11. CLK pins AF remapping ...................................................................................................... 164
7.5. Register definition ................................................................................................... 165
7.5.1. Port control register 0 (GPIOx_CTL0, x=A..G) ................................................................... 165
7.5.2. Port control register 1 (GPIOx_CTL1, x=A..G) ................................................................... 167

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7.5.3. Port input status register (GPIOx_ISTAT, x=A..G) .............................................................. 169
7.5.4. Port output control register (GPIOx_OCTL, x=A..G) .......................................................... 169
7.5.5. Port bit operate register (GPIOx_BOP, x=A..G).................................................................. 170
7.5.6. Port bit clear register (GPIOx_BC, x=A..G) ........................................................................ 170
7.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G).................................................... 171
7.5.8. Event control register (AFIO_EC) ....................................................................................... 171
7.5.9. AFIO port configuration register 0 (AFIO_PCF0) ............................................................... 172
7.5.10. EXTI sources selection register 0 (AFIO_EXTISS0) .......................................................... 178
7.5.11. EXTI sources selection register 1 (AFIO_EXTISS1) .......................................................... 180
7.5.12. EXTI sources selection register 2 (AFIO_EXTISS2) .......................................................... 181
7.5.13. EXTI sources selection register 3 (AFIO_EXTISS3) .......................................................... 182
7.5.14. AFIO port configuration register 1 (AFIO_PCF1) ............................................................... 183
8. Cyclic redundancy checks management unit (CRC) ........................................185
8.1. Overview .................................................................................................................. 185
8.2. Characteristics......................................................................................................... 185
8.3. Function overview ................................................................................................... 186
8.4. Register definition ................................................................................................... 187
8.4.1. Data register (CRC_DATA) ................................................................................................. 187
8.4.2. Free data register (CRC_FDATA) ....................................................................................... 187
8.4.3. Control register (CRC_CTL) ............................................................................................... 188
9. Direct memory access controller (DMA)............................................................189
9.1. Overview .................................................................................................................. 189
9.2. Characteristics......................................................................................................... 189
9.3. Block diagram.......................................................................................................... 190
9.4. Function overview ................................................................................................... 190
9.4.1. DMA operation .................................................................................................................... 190
9.4.2. Peripheral handshake......................................................................................................... 192
9.4.3. Arbitration............................................................................................................................ 192
9.4.4. Address generation............................................................................................................. 193
9.4.5. Circular mode...................................................................................................................... 193
9.4.6. Memory to memory mode................................................................................................... 193
9.4.7. Channel configuration......................................................................................................... 193
9.4.8. Interrupt............................................................................................................................... 194
9.4.9. DMA request mapping ........................................................................................................ 194
9.5. Register definition ................................................................................................... 198
9.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 198
9.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 199
9.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 199
9.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 201

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9.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 202
9.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 202
10. Debug (DBG) .....................................................................................................204
10.1. Overview............................................................................................................... 204
10.2. JTAG/SW function overview................................................................................ 204
10.2.1. Switch JTAG or SW interface ............................................................................................. 204
10.2.2. Pin assignment ................................................................................................................... 204
10.2.3. JTAG daisy chained structure............................................................................................. 205
10.2.4. Debug reset ........................................................................................................................ 205
10.2.5. JEDEC-106 ID code ........................................................................................................... 205
10.3. Debug hold function overview ............................................................................ 205
10.3.1. Debug support for power saving mode............................................................................... 205
10.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN ............................................ 206
10.4. Register definition................................................................................................ 207
10.4.1. ID code register (DBG_ID).................................................................................................. 207
10.4.2. Control register (DBG_CTL) ............................................................................................... 207
11. Analog-to-digital converter (ADC)................................................................... 211
11.1. Overview................................................................................................................211
11.2. Characteristics......................................................................................................211
11.3. Pins and internal signals..................................................................................... 212
11.4. Function overview................................................................................................ 213
11.4.1. Foreground calibration function.......................................................................................... 213
11.4.2. ADC clock ........................................................................................................................... 214
11.4.3. ADC enable......................................................................................................................... 214
11.4.4. Routine sequence............................................................................................................... 214
11.4.5. Operation modes ................................................................................................................ 214
11.4.6. Conversion result threshold monitor function ..................................................................... 217
11.4.7. Data storage mode ............................................................................................................. 217
11.4.8. Sample time configuration.................................................................................................. 218
11.4.9. External trigger configuration.............................................................................................. 218
11.4.10. DMA request ................................................................................................................... 219
11.4.11. ADC internal channels .................................................................................................... 219
11.5. ADC sync mode.................................................................................................... 220
11.5.1. Free mode........................................................................................................................... 221
11.5.2. Routine parallel mode ......................................................................................................... 221
11.5.3. Routine follow-up fast mode ............................................................................................... 221
11.5.4. Routine follow-up slow mode.............................................................................................. 222
11.6. ADC interrupts...................................................................................................... 223

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11.7. Register definition................................................................................................ 224
11.7.1. Status register (ADC_STAT) ............................................................................................... 224
11.7.2. Control register 0 (ADC_CTL0) .......................................................................................... 225
11.7.3. Control register 1 (ADC_CTL1) .......................................................................................... 226
11.7.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 228
11.7.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 229
11.7.6. Watchdog high threshold register (ADC_WDHT) ............................................................... 230
11.7.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 231
11.7.8. Routine sequence register 0 (ADC_RSQ0)........................................................................ 231
11.7.9. Routine sequence register 1 (ADC_RSQ1)........................................................................ 232
11.7.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 232
11.7.11. Routine data register (ADC_RDATA).............................................................................. 233
12. Digital-to-analog converter (DAC) ...................................................................234
12.1. Overview............................................................................................................... 234
12.2. Characteristics..................................................................................................... 234
12.3. Function overview................................................................................................ 235
12.3.1. DAC enable......................................................................................................................... 235
12.3.2. DAC output buffer ............................................................................................................... 236
12.3.3. DAC data configuration....................................................................................................... 236
12.3.4. DAC trigger ......................................................................................................................... 236
12.3.5. DAC workflow ..................................................................................................................... 236
12.3.6. DAC noise wave ................................................................................................................. 237
12.3.7. DAC output calculate .......................................................................................................... 238
12.3.8. DMA function....................................................................................................................... 238
12.3.9. DAC concurrent conversion................................................................................................ 238
12.4. Register definition................................................................................................ 239
12.4.1. Control register (DAC_CTL) ............................................................................................... 239
12.4.2. Software trigger register (DAC_SWT) ................................................................................ 241
12.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)....................................... 242
12.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ......................................... 242
12.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)........................................... 243
12.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)....................................... 243
12.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) ......................................... 244
12.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)........................................... 244
12.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH)............ 245
12.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) ........... 245
12.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ............ 246
12.4.12. DAC0 data output register (DAC0_DO) .......................................................................... 246
12.4.13. DAC1 data output register (DAC1_DO) .......................................................................... 247
13. Watchdog timer (WDGT) ..................................................................................248

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13.1. Free watchdog timer (FWDGT)............................................................................ 248
13.1.1. Overview ............................................................................................................................. 248
13.1.2. Characteristics .................................................................................................................... 248
13.1.3. Function overview ............................................................................................................... 248
13.1.4. Register definition ............................................................................................................... 251
13.2. Window watchdog timer (WWDGT)..................................................................... 254
13.2.1. Overview ............................................................................................................................. 254
13.2.2. Characteristics .................................................................................................................... 254
13.2.3. Function overview ............................................................................................................... 254
13.2.4. Register definition ............................................................................................................... 257
14. Real-time Clock (RTC) ......................................................................................259
14.1. Overview ............................................................................................................... 259
14.2. Characteristics..................................................................................................... 259
14.3. Function overview................................................................................................ 259
14.3.1. RTC reset............................................................................................................................ 260
14.3.2. RTC reading........................................................................................................................ 260
14.3.3. RTC configuration ............................................................................................................... 260
14.3.4. RTC flag assertion .............................................................................................................. 261
14.4. Register definition................................................................................................ 263
14.4.1. RTC interrupt enable register (RTC_INTEN)...................................................................... 263
14.4.2. RTC control register (RTC_CTL) ........................................................................................ 263
14.4.3. RTC prescaler high register (RTC_PSCH) ......................................................................... 264
14.4.4. RTC prescaler low register (RTC_PSCL) ........................................................................... 265
14.4.5. RTC divider high register (RTC_DIVH)............................................................................... 265
14.4.6. RTC divider low register (RTC_DIVL)................................................................................. 265
14.4.7. RTC counter high register (RTC_CNTH)............................................................................ 266
14.4.8. RTC counter low register (RTC_CNTL).............................................................................. 266
14.4.9. RTC alarm high register (RTC_ALRMH) ............................................................................ 267
14.4.10. RTC alarm low register (RTC_ALRML) .......................................................................... 267
15. TIMER ................................................................................................................268
15.1. Advanced timer (TIMERx, x=0, 7)........................................................................ 269
15.1.1. Overview ............................................................................................................................. 269
15.1.2. Characteristics .................................................................................................................... 269
15.1.3. Block diagram ..................................................................................................................... 269
15.1.4. Function overview ............................................................................................................... 270
15.1.5. Register definition ............................................................................................................... 298
15.2. General level0 timer (TIMERx, x=1, 2, 3, 4)......................................................... 325
15.2.1. Overview ............................................................................................................................. 325
15.2.2. Characteristics .................................................................................................................... 325
15.2.3. Block diagram ..................................................................................................................... 325

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15.2.4. Function overview ............................................................................................................... 326
15.2.5. Register definition ............................................................................................................... 342
15.3. General level1 timer (TIMERx, x=8, 11)............................................................... 364
15.3.1. Overview ............................................................................................................................. 364
15.3.2. Characteristics .................................................................................................................... 364
15.3.3. Block diagram ..................................................................................................................... 365
15.3.4. Function overview ............................................................................................................... 365
15.3.5. Register definition ............................................................................................................... 381
15.4. General level2 timer (TIMERx, x=9, 10, 12, 13) ................................................... 394
15.4.1. Overview ............................................................................................................................. 394
15.4.2. Characteristics .................................................................................................................... 394
15.4.3. Block diagram ..................................................................................................................... 394
15.4.4. Function overview ............................................................................................................... 395
15.4.5. Register definition ............................................................................................................... 406
15.5. Basic timer (TIMERx, x=5, 6)................................................................................ 417
15.5.1. Overview ............................................................................................................................. 417
15.5.2. Characteristics .................................................................................................................... 417
15.5.3. Block diagram ..................................................................................................................... 417
15.5.4. Function overview ............................................................................................................... 417
15.5.5. Register definition ............................................................................................................... 422
16. Universal synchronous/asynchronous receiver /transmitter (USART)........428
16.1. Overview ............................................................................................................... 428
16.2. Characteristics..................................................................................................... 428
16.3. Function overview................................................................................................ 429
16.3.1. USART frame format .......................................................................................................... 430
16.3.2. Baud rate generation .......................................................................................................... 431
16.3.3. USART transmitter.............................................................................................................. 431
16.3.4. USART receiver .................................................................................................................. 432
16.3.5. Use DMA for data buffer access ......................................................................................... 434
16.3.6. Hardware flow control ......................................................................................................... 435
16.3.7. Multi-processor communication .......................................................................................... 437
16.3.8. LIN mode ............................................................................................................................ 437
16.3.9. Synchronous mode............................................................................................................. 438
16.3.10. IrDA SIR ENDEC mode .................................................................................................. 439
16.3.11. Half-duplex communication mode .................................................................................. 441
16.3.12. Smartcard (ISO7816-3) mode......................................................................................... 441
16.3.13. USART interrupts ............................................................................................................ 442
16.4. Register definition................................................................................................ 444
16.4.1. Status register (USART_STAT) .......................................................................................... 444
16.4.2. Data register (USART_DATA)............................................................................................. 446