Efinix Titanium User manual

Titanium Interfaces
User Guide
UG-TiINTF-v2.0
February 2022
www.efinixinc.com
Copyright © 2022. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other
trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.

Titanium Interfaces User Guide
Contents
About the Interface Designer.........................................................................................................iv
Chapter1:Get Oriented.................................................................................................................. 5
Interface Blocks..........................................................................................................................................7
Package/Interface Support Matrix...........................................................................................................8
Interface Block Connectivity.................................................................................................................... 8
Designing an Interface............................................................................................................................. 9
Create or Delete a Block....................................................................................................................... 10
Using the Resource Assigner................................................................................................................ 11
Resource View..............................................................................................................................12
Importing and Exporting Assignments.....................................................................................13
Interface Designer Output Files............................................................................................................15
Scripting an Interface Design................................................................................................................15
Chapter2:Device Settings............................................................................................................17
Configuration Interface...........................................................................................................................17
Enable Internal Configuration....................................................................................................17
About SEU Detection.................................................................................................................. 17
Enable SEU Detection.................................................................................................................18
SEU Detection Circuitry.............................................................................................................. 19
Design Check: Configuration Messages............................................................................................. 20
I/O Banks Interface................................................................................................................................. 21
Titanium I/O Banks................................................................................................................................. 21
Dynamic Voltage Support......................................................................................................................22
Design Check: I/O Bank Messages......................................................................................................23
Chapter3:Clock and Control Networks....................................................................................... 24
Clock Sources that Drive the Global and Regional Networks.......................................................... 26
Configuring the Dynamic Clock Multiplexers..................................................................................... 27
Driving both the Global and Regional Networks............................................................................... 27
Design Check: Clock Control Messages............................................................................................. 28
Chapter4:DDR Interface.............................................................................................................. 31
About the DDR DRAM Interface............................................................................................................ 31
DDR Interface Designer Settings.......................................................................................................... 37
Chapter5:GPIO Interface............................................................................................................. 39
Types of GPIO...........................................................................................................................................39
Features for HVIO and HSIO Configured as GPIO.............................................................................41
Double-Data I/O.......................................................................................................................... 42
Programmable Delay Chains..................................................................................................... 43
About the HVIO Interface....................................................................................................................... 44
About the HSIO Interface....................................................................................................................... 46
HSIO Configured as GPIO.....................................................................................................................47
Using the GPIO Block.............................................................................................................................50
Using the GPIO Bus Block..................................................................................................................... 53
Create a TX Serializer Interface............................................................................................................ 54
Create a RX Deserializer Interface........................................................................................................55
Design Check: GPIO Messages............................................................................................................ 56
Chapter6:LVDS Interface............................................................................................................. 67
HSIO Configured as LVDS..................................................................................................................... 67
Using the LVDS Block.............................................................................................................................73
Create an LVDS TX Interface................................................................................................................. 75
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Titanium Interfaces User Guide
Create an LVDS RX Interface.................................................................................................................77
Design Check: LVDS Errors and Warnings..........................................................................................78
Chapter7:HyperRAM Interface.................................................................................................... 86
About the HyperRAM..............................................................................................................................86
Using the HyperRAM Interface............................................................................................................. 87
Chapter8:JTAG User TAP Interface............................................................................................. 89
JTAG Mode.............................................................................................................................................. 89
Using the JTAG User TAP Block........................................................................................................... 92
Design Check: JTAG User Tap Errors and Warnings.........................................................................93
Chapter9:MIPI RX/TX Lane Interface.......................................................................................... 94
HSIO Configured as MIPI Lane...............................................................................................................94
MIPI Groups by Package........................................................................................................................99
Using the MIPI TX Lane or MIPI RX Lane Block................................................................................103
Create a MIPI TX Interface...................................................................................................................104
Create a MIPI RX Interface.................................................................................................................. 106
Design Check: MIPI Lane Messages.................................................................................................. 107
Chapter10:MIPI D-PHY Interface...............................................................................................110
MIPI RX D-PHY.......................................................................................................................................110
MIPI TX D-PHY.......................................................................................................................................113
MIPI DPHY TX Interface Designer Settings....................................................................................... 117
MIPI DPHY RX Interface Designer Settings.......................................................................................119
Chapter11:PLL........................................................................................................................... 121
About the PLL Interface........................................................................................................................ 121
Using the PLL V3 Block........................................................................................................................123
Using the PLL Clock Calculator...............................................................................................123
Understanding PLL Phase Shifting..........................................................................................124
Manually Configuring the PLL................................................................................................. 124
Implementing a Zero-Delay Buffer.....................................................................................................125
Design Check: PLL Errors.................................................................................................................... 126
Chapter12:Oscillator................................................................................................................. 131
Using the Oscillator Block................................................................................................................... 131
Design Check: Oscillator Errors......................................................................................................... 131
Chapter13:SPI Flash Interface...................................................................................................133
About the SPI Flash Memory...............................................................................................................133
Using the SPI Flash Interface.............................................................................................................. 134
Chapter14:Interface Floorplans................................................................................................ 135
Icon Reference.............................................................................................................................137
Revision History.......................................................................................................................... 138
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Titanium Interfaces User Guide
About the Interface Designer
Titanium FPGAs wrap a Quantum™-accelerated core with a periphery that sends signals
out to the device pins. The core contains the logic, embedded memory, and multipliers. The
device periphery includes blocks such as GPIO pins, LVDS, MIPI, DDR, and PLLs.
The tools in the Efinity® main window help you design the logic portion of your design. You
use the Efinity Interface Designer to build the peripheral portion of your design.
Figure 1: Conceptual View of Interface Blocks
Embedded Memory
Multiplier
Note: The number and locations of blocks
are shown for illustration purposes only.
The actual number and position depends
on the device.
Interface Blocks:
Use the Efinity Interface Designer to create and
define these blocks and to connect them to
your RTL design via the signal interface.
Programmable Core Fabric:
Create your RTL design for the core fabric
using Efinity design tools.
Signal Interface:
Connects the core fabric to the interface blocks
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Titanium Interfaces User Guide
Chapter 1
Get Oriented
Contents:
•Interface Blocks
•Package/Interface Support Matrix
•Interface Block Connectivity
•Designing an Interface
•Create or Delete a Block
•Using the Resource Assigner
•Interface Designer Output Files
•Scripting an Interface Design
The Interface Designer has four main sections:
•Design Explorer—Provides a list view of the interface blocks you have in your design
organized by block type. It also includes device-wide settings for the I/O banks and
configuration options. Select a block to display it's summary and editor.
•Block Summary—Displays the current settings for the selected block.
•Block Editor—Provides options and settings for the selected block. The editor may have
more than one tab, depending on the block.
•Resource Assigner—Provides an easy, tabular method for assigning resources. View by
instance (default) or resource.
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Titanium Interfaces User Guide
Figure 2: Interface Designer
When you first open the Interface Designer for your project, the Design Explorer shows the
Device Settings folder (with default settings) and empty folders for the interface blocks your
chosen device supports. You need to add blocks as required for your design.
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Titanium Interfaces User Guide
Interface Blocks
Titanium FPGAs support a variety of interface blocks. The available blocks differ depending
on which FPGA you target. You need to assign a resource for every block you use.
The following table describes the interface blocks supported in the Efinity® software version
2021.2.
Table 1: Titanium Interface Blocks
Interface Ti35 Ti60 Ti90 Ti120 Ti180
DDR
GPIO
GPIO bus
I/O bank
JTAG User TAP
LVDS TX
LVDS RX
Bidirectional
LVDS
MIPI DPHY
MIPI TX Lane
MIPI RX Lane
PLL (V3)
Oscillator
All interface blocks have an instance name that must be a unique identifier. When you add
a new block, the Interface Designer gives the block a unique default name, which you can
change.
Note: Many fields in the Block Editor allow arbitrary names. After you type a new name, press Enter or
click Save to save the name.
Pin names are the top-level ports of the design implemented in the core that connect to the
interface block. These names must be legal Verilog HDL or VHDL identifiers.
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Titanium Interfaces User Guide
Package/Interface Support Matrix
Some interfaces are only available in certain packages. The following table describes which
interfaces are supported in specific FPGA/package combinations for the Efinity® software
v2021.2.
Table 2: Titanium Interface/Package Combinations Supported in Efinity® Software
v2021.2
Package Ti35 Ti60 Ti90, Ti120, Ti180
W64
F100
F225
M484
Titanium Family Legend:
Oscillator PLL LVDS MIPI RX or
TX Lane
MIPI D-PHY
Controller
DDR DRAM
Controller
Interface Block Connectivity
The FPGA core fabric connects to the interface blocks through a signal interface. The
interface blocks then connect to the package pins. The core connects to the interface blocks
using three types of signals:
•Input—Input data or clock to the FPGA core
•Output—Output from the FPGA core
•Clock output—Clock signal from the core clock tree
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Titanium Interfaces User Guide
Figure 3: Interface Block and Core Connectivity
FPGA
Signal
Interface
Core
Interface
Block
Input
Output
Clock Output
Interface
Block
GPIO
Input
Output
Clock Output
Interface
Block
Input
Output
Clock Output
Interface
Block
Input
Output
Clock Output
GPIO blocks are a special case because they can operate in several modes. For example, in
alternate mode the GPIO signal can bypass the signal interface and directly feed another
interface block. So a GPIO configured as an alternate input can be used as a PLL reference
clock without going through the signal interface to the core.
When designing for Titanium FPGAs, you create an RTL design for the core and also
configure the interface blocks. From the perspective of the core, outputs from the core are
inputs to the interface block and inputs to the core are outputs from the interface block.
The Efinity netlist always shows signals from the perspective of the core, so some signals do
not appear in the netlist:
•GPIO used as reference clocks are not present in the RTL design, they are only visible in
the interface block configuration of the Efinity® Interface Designer.
•The FPGA clock tree is connected to the interface blocks directly. Therefore, clock
outputs from the core to the interface are not present in the RTL design, they are only
part of the interface configuration (this includes GPIO configured as output clocks).
The following sections describe the different types of interface blocks in the Titanium. Signals
and block diagrams are shown from the perspective of the interface, not the core.
Designing an Interface
Save Check Design Generate Report
Generate Efinity
Constraint Files
Exit
Designing your interface is straightforward: add interface blocks, configure them, and then
generate reports and constraints. The Efinity software uses the constraints during compilation
to connect signals from the core to your interface.
Note: Refer to Create or Delete a Block on page 10 and Interface Blocks on page 7 for instructions on
adding blocks and configuring them.
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Titanium Interfaces User Guide
During the design process, you can generate reports, which are available in the Efinity®
Results tab. When you generate reports, the software also saves your design.
Use the design checker to check the interface for errors and to ensure that your settings are
valid. The Interface designer displays design issues in the message viewer window. You can
also export design issues (Design > Export Design Issues) to generate a comma separated
values (.csv) report to view the issues in a spreadsheet application. When you run the design
checker, the software automatically saves your interface.
When you are done configuring your interface, click the Export Efinity Constraints Files
button to export the interface constraints to your project. The software saves the design,
checks it for errors, generates the interface reports and the interface constraint files.
Click Exit to close the Interface Designer and return to the Efinity® main window.
Note: You can leave the Interface Designer open while running the Efinity® software. However, if you
make changes to the Efinity project, the Interface Designer is not updated until the next time you launch it.
Create or Delete a Block
Create Block Create GPIO Bus Delete Block
To create a block:
1. Select the folder for the block type you want to create.
2. Click the Create Block button.
To create a GPIO bus, click the GPIO folder and then click the Create GPIO Bus button.
To delete a block, select the block name and click the Delete Block button.
Tip: Right-clicking a folder name opens a context-sensitive menu. From there you can choose Create Block (and
Create Bus for GPIO).
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Titanium Interfaces User Guide
Using the Resource Assigner
Resource Assigner Switch View Clear Selected
Resource
Clear All Resources
Show/Hide Filter Clear Filter
The Resource Assigner provides a tabular view of all GPIO resources in your chosen FPGA
and information about them, such as whether they are used, the I/O bank, pad, and package
pin, and the instance assigned to the resource.
•The GPIO: Instance View shows all GPIO instances in your project.
•The GPIO: Resource View shows all GPIO, LVDS, and MIPI RX or TX lane resources
and the resources to which you assigned them.
Note: In the Efinity® software v2021.1, you can only view the resources used for LVDS and MIPI lanes in
the Resource Assigner. You cannot change or assign resources in this view.
To assign a resource:
1. Open the Resource Assigner by clicking the Show/Hide Resource Assigner button. The
software opens to the Instance View, which lists all instances in the design.
Note: Click Switch View to toggle between instance view and resource view.
2. In instance view, you can assign pins or resources to the instance. Double-click in the
table cell for the item you want to assign. The software displays a drop-down list of
available selections.
3. Select an unused resource, instance, or pin.
Note: If you select a used resource, instance, or pin, the software makes the new
assignment, which replaces the previous assignment.
4. Press Enter.
Note: Titanium: When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO
pins between any GPIO and HSIO pins in the same bank. This separation reduces noise. The Efinity
software issues an error if you do not leave this separation.
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Titanium Interfaces User Guide
Figure 4: Resource Assigner
Resource View
When assigning GPIO, sometimes you want to know which resource can be used as a global
clock, global control, or other special function. You can look it up in the pin table for the
FPGA and package you are targeting, but an easier way is to use the Resource View in the
Resource Assigner.
1. Click the Switch View button to open the Resource View.
2. Double-click in the filter box above the Alt Conn column and choose the connection
type, for example, GCTRL.
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Titanium Interfaces User Guide
Figure 5: Resource View
Importing and Exporting Assignments
Although it is nice to use a GUI for adding blocks, in some cases it may be easier to use
another format. The Interface Designer lets you import and export assignments using an
Interface Scripting File (.isf) or comma separated values (.csv) file.
When the software reads an imported .isf, it processes the entire imported file and shows any
issues it found. The import only fails for catastrophic errors. The software:
•Creates new instances defined in the file that do not already exist in the GUI
•Overwrites assignments for existing instances with settings from the file
•Does not delete instances that are in the GUI but were not defined in the file
When the software reads an imported .csv file, it compares the imported assignments to the
original assignments and reports any issues. If the software finds warnings, it displays them
but allows you to finish the import. If it finds errors, it will not finish the import. When
importing, the software:
•Deletes instances that you removed
•Creates newly defined instances
•Replaces instances you renamed with the new name
Learn more: For help understanding messages, refer to the "Design Check" topics in the Titanium
Interfaces User Guide. These topics describe the messages the Interface Designer generates and gives
suggestions on how to fix errors and warnings.
Interface Scripting File
The Interface Scripting File (.isf) contains all of the Python API commands to re-create your
interface. You can export your design to an .isf, manipulate the file, and then re-import it
back into the Efinity® software. Additionally, you can write your own .isf if desired.
In addition to using the API, you can export and import an .isf in the Interface Designer
GUI. Click the Import GPIO or Export GPIO buttons and choose Interface Scripting File
(.isf) under Format.
Example: Example Interface Scripting File
# Efinity Interface Configuration
# Version: 2020.M.138
# Date: 2020-06-26 14:22
#
# Copyright (C) 2017 - 2020 Efinix Inc. All rights reserved.
#
# Device: T8F81
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# Package: 81-ball FBGA (final)
# Project: pt_demo
# Configuration mode: active (x1)
# Timing Model: C2 (final)
# Create instance
design.create_output_gpio("Fled",3,0)
design.create_inout_gpio("Sled",3,0)
design.create_output_gpio("Oled",3,0)
design.create_clockout_gpio("Oclk_out")
design.create_pll_input_clock_gpio("pll_clkin")
design.create_global_control_gpio("resetn")
# Set property, non-defaults
design.set_property("Fled","OUT_REG","REG")
design.set_property("Fled","OUT_CLK_PIN","Fclk")
design.set_property("Sled[0]","IN_PIN","")
design.set_property("Sled[0]","OUT_PIN","Sled[0]")
design.set_property("Sled[1]","IN_PIN","")
design.set_property("Sled[1]","OUT_PIN","Sled[1]")
design.set_property("Sled[2]","IN_PIN","")
design.set_property("Sled[2]","OUT_PIN","Sled[2]")
design.set_property("Sled[3]","IN_PIN","")
design.set_property("Sled[3]","OUT_PIN","Sled[3]")
design.set_property("Oclk_out","OUT_CLK_PIN","Oclk")
# Set resource assignment
design.assign_pkg_pin("Fled[0]","J2")
design.assign_pkg_pin("Fled[1]","C2")
design.assign_pkg_pin("Fled[2]","F8")
design.assign_pkg_pin("Fled[3]","D8")
design.assign_pkg_pin("Sled[0]","E6")
design.assign_pkg_pin("Sled[1]","G4")
design.assign_pkg_pin("Sled[2]","E2")
design.assign_pkg_pin("Sled[3]","G9")
design.assign_pkg_pin("Oled[0]","H4")
design.assign_pkg_pin("Oled[1]","J4")
design.assign_pkg_pin("Oled[2]","A5")
design.assign_pkg_pin("Oled[3]","C5")
design.assign_pkg_pin("Oclk_out","D6")
design.assign_pkg_pin("pll_clkin","C3")
design.assign_pkg_pin("resetn","F1")
.csv File for GPIO Blocks
For larger designs with lots of GPIO, it can be simpler to use a spreadsheet application to
make assignments. The Resource Assigner allows you to import and export GPIO block
assignments using a comma separated values (.csv) file. The .csv file includes the package pin
and pad name, the instance name, and the mode. You can use this method for any type of
GPIO, including LVDS pins used as GPIO or HSIO pins used as GPIO.
Table 3: Example GPIO .csv File
Package Pin-Pad Name Instance Name Mode
G5-GPIOL_00
J4-GPIOL_01_SS_N
H4-GPIOL02_CCK
G4-GPIOL_03_CDI4 led[0] output
F4-GPIOL04_CDI0 led[1] output
J3-GPIOL_05_CDI5 rstn input
H3-GPIOL_06_CDI1
...
(1) led[6] inout
(1) Unassigned instances have a blank field for the Package Pin-Pad Name column.
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Titanium Interfaces User Guide
When working with the .csv file:
•Add your assignments to the Instance Name and Mode columns.
•Do not modify the package pin-pad names.
•For the mode, specify: input, output, inout, clkout, or none
Note: You cannot make advanced settings such as alternate connections or
registering. To make these settings, use the Block Editor.
When the software reads an imported .csv file, it performs a comparison between the .csv
assignments and the original GPIO block assignments and reports any issues. If the software
finds warnings, it displays them but allows you to finish the import. If it finds errors, it will
not finish the import. When importing, the software:
•Deletes instances that you removed
•Creates newly defined instances
•Replaces instances you renamed with the new name
Interface Designer Output Files
When you generate constraint files, the Interface Designer creates the following output files.
You can view them in the Interface section of the Result pane.
•<project name>.interface.csv—Constrains the FPGA design pins used in the interface
between the core and the periphery.
•<project name>.pt.rpt—Provides information about the interface.
•<project name>.pinout.csv—Contains the board design pinout in CSV format.
•<project name>.pinout.rpt—Has the board design pinout in a nicely formatted text file
format.
•<project name>.pt_timing.rpt—Timing report for the Titanium interface logic.
•<project name>.pt.sdc—Template SDC file to constrain the FPGA design pins based
on the interface configuration.
•<project name>_template.v—Template Verilog HDL file defining the FPGA design
pins based on the interface configuration.
Scripting an Interface Design
Python is an interpreted, object-oriented, high-level programming language with dynamic
semantics.(2) Efinix distributes a copy of Python 3 with the Efinity® software to support point
tools such as the Debugger and to allow users to write scripts to control compilation.
You use the Efinity® Interface Designer to build the peripheral portion of your design,
including GPIO, LVDS, PLLs, MIPI RX and TX lanes, and other hardened blocks. Efinix
provides a Python 3 API for the Interface Designer to let you write scripts to control the
interface design process. For example, you may want to create a large number of GPIO, or
target your design to another board, or export the interface to perform analysis. This user
guide describes how to use the API and provides a function reference.
Learn more: Refer to the Python web site, www.python.org/doc, for detailed documentation on the
language.
(2) Source: What Is Python? Executive Summary
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Titanium Interfaces User Guide
Learn more: For more information on using the Python API to script an interface, refer to the Efinity
Interface Designer Python API.
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Titanium Interfaces User Guide
Chapter 2
Device Settings
Contents:
•Configuration Interface
•Design Check: Configuration Messages
•I/O Banks Interface
•Titanium I/O Banks
•Dynamic Voltage Support
•Design Check: I/O Bank Messages
The Interface Designer has device-wide settings for I/O banks and configuration.
Configuration Interface
The Configuration device-wide setting lets you control or monitor configuration using the
FPGA design implemented in the FPGA core.
Enable Internal Configuration
Efinix® FPGAs have an internal reconfiguration feature that allows you to control
reconfiguration of the FPGA from within the FPGA design. Leave this feature disabled
unless you want to use internal reconfiguration.
To enable internal reconfiguration:
1. Click Device Setting > Configuration.
2. In the Block Editor Remote Update tab, turn on Enable Internal Reconfiguration
Interface.
3. Indicate the name of the clock pin that will control the internal reconfiguration.
4. Define the FPGA pins that the interface uses.
5. Save.
Note: Refer to AN 010: Using Internal Reconfiguration in Trion and Titanium FPGAs for instructions on
how to use this feature.
About SEU Detection
An SEU happens when an environmental factor, such as background radiation, causes a
digital circuit to malfunction. For FPGAs, the most frequent (and most worrisome) outcome
of an SEU is that a CRAM bit is changed from its programmed value. Designs may not use
every CRAM bit in the FPGA, so an SEU may or may not cause the FPGA to malfunction.
However, in many situations the safest course of action is to assume that the FPGA's
behavior is corrupted until it is reconfigured.
Titanium FPGAs contain built-in circuitry to help detect SEUs. This circuitry periodically
monitors the FPGA's CRAM, detects if a CRAM value has changed from the programmed
state, and sends status signals to user logic. The user logic can optionally trigger the FPGA to
reconfigure using the SEU detection circuitry.
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Titanium Interfaces User Guide
Figure 6: SEU Detection Circuitry
FPGA
SEU
Detection
Circuit
SEU
Event
CRAM
Watch for flipped bits
Error found
Trigger
Reconfiguration
User
Logic
Titanium FPGAs can monitor the CRAM while the FPGA is operating normally in user
mode; When the SEU detection circuitry is triggered, it calculates a 32-bit CRC value based
on CRAM values and compares it to a CRC computed by the Efinity software and stored in
the configuration bitstream. If the values are different, the SEU circuit determines an error
has occurred and sends an error signal to the user logic. You can trigger the SEU detection
circuitry automatically on a set interval, or manually using a signal.
Note: For Ti35 and Ti60 FPGAs, your design should be in an "idle" state before performing an SEU check.
Enable SEU Detection
To enable the SEU feature in the Efinity software:
1. Click Device Setting > Configuration.
2. Click the SEU Detection tab.
3. Turn on Enable SEU Detection.
4. Choose the mode, auto or manual.
•In auto mode, you can specify the amount of time between SEU error checks in
microseconds. Allowable values are 1 to 1650000.0 (default).
•In manual mode, you specify the pin name that controls when the SEU error check
happens.
Tip: For environment that have a higher risk of SEUs, you can set a shorter wait interval. However, the shorter the
wait interval, the more power the system consumes. To use less power, choose a longer wait interval. To save even
more power, you can use manual mode to only trigger the SEU detection circuitry when conditions require it.
5. Save.
Note: The software issues an error if you turn on SEU detection for Ti60ES FPGAs because they do not
support SEU checking.
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Titanium Interfaces User Guide
SEU Detection Circuitry
Your user logic connects to the SEU detection circuitry using the following pins.
Table 4: SEU Detection Pins
GUI Option Default Signal Name Direction Description
SEU Start Detection Pin
Name
seu_START Input Manual mode only. To use this pin to initiate an
SEU check, pulse this signal high for a minimum
pulse of 500 ns.
Error Injection Pin
Name
seu_INJECT_ERROR Input This signal forces an SEU error so you can test
the how the SEU detection circuitry interacts
with your user design during testing and
development. To inject an error, pulse this signal
high for a minimum pulse of 500 ns.
Pull this signal low when you are not using it.
Error Reset Pin Name seu_RST Input This pin sets the Error Status pin to low to clear
the error and restart SEU detection monitoring.
To reset SEU monitoring, pulse this signal high
for a minimum pulse of 500 ns.
Error Status Pin Name seu_ERROR Output If the FPGA detects an SEU, this signal goes high.
It does not go low until you toggle the Error
Reset pin.
Reconfiguration Pin
Name
seu_CONFIG Input If the FPGA is using active configuration mode,
you can use this pin to trigger the FPGA to
reconfigure; the FPGA does not automatically
reconfigure when an error is detected. Pulse this
signal high for a minimum pulse width of 500 ns.
If you are using passive configuration mode
or JTAG configuration, you cannot trigger
reconfiguration with this signal.
SEU Done Detection
Pin Name
seu_DONE Output This signal goes high when the SEU detection
circuitry has completed calculating the CRC
and comparing it to the stored one. If an SEU
occurred, this signal stays high until you reset the
circuitry.
Figure 7: SEU Signal Waveform
seu_START
seu_INJECT_ERROR
seu_RST
seu_ERROR
seu_CONFIG
seu_DONE
500 ns
500 ns
500 ns
500 ns
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Titanium Interfaces User Guide
Design Check: Configuration Messages
When you check your design, the Interface Designer applies design rules to your
configuration settings. The following tables show some of the error messages you may
encounter and explains how to fix them.
configuration_rule_clock (error)
Message Internal Reconfiguration Interface is enabled but clock pin name is invalid
To fix Enter a valid clock name.
seu_rule_start (error)
Message Empty SEU Start Detection pin name found
To fix Enter a valid start pin name.
seu_rule_interval (error)
Message Invalid wait interval <#> microsec
To fix Change the wait interval to one that is in range. Allowable values are 0 - 1677721.
seu_rule_error (error)
Message Empty Error Status pin name found
To fix Enter a valid error pin name.
seu_rule_param (error)
Message Invalid parameters configuration: <feature list>
To fix One of the parameters you set was incorrect. Review any other errors for details.
seu_rule_sample_device (error)
Message SEU Detection is not supported in ES device
To fix You get this error if you try to enable SEU for the Ti60ES. SEU is not supported in this FPGA.
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