ST STM32F20 Series Installation and operating instructions

August 2011 Doc ID 18267 Rev 2 1/29
AN3320
Application note
Getting started with STM32F20xxx/21xxx MCU
hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the high-density performance line STM32F20xxx/21xxx product families
and describes the minimum hardware resources required to develop an
STM32F20xxx/21xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
www.st.com

Contents AN3320
2/29 Doc ID 18267 Rev 2
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7
1.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 9
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 13
2.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 14
2.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.3 Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 19
4.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 20

AN3320 Contents
Doc ID 18267 Rev 2 3/29
5 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

List of tables AN3320
4/29 Doc ID 18267 Rev 2
List of tables
Table 1. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2. Debug port pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AN3320 List of figures
Doc ID 18267 Rev 2 5/29
List of figures
Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. STM32F207IG(H6) microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power supplies AN3320
6/29 Doc ID 18267 Rev 2
1 Power supplies
1.1 Introduction
The device requires a 1.8 V to 3.6 V operating voltage supply (VDD), excepted the WLCSP
package witch requires 1.65 V to 3.6 V. An embedded regulator is used to supply the
internal 1.2 V digital power.
The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when
the main VDD supply is powered off.
Figure 1. Power supply overview
1. VDDA and VSSA must be connected to VDD and VSS, respectively.
2. The voltage on VREF ranges from 1.65 V to VDDA for WLCSP64+2 packages.
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AN3320 Power supplies
Doc ID 18267 Rev 2 7/29
1.1.1 Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply that can be
filtered separately, and shielded from noise on the PCB.
●the ADC voltage supply input is available on a separate VDDA pin
●an isolated supply ground connection is provided on the VSSA pin
When available (depending on package), VREF– must be tied to VSSA.
On 100-pin package and above and on WLCSP64+2
To ensure a better accuracy on low-voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF+. The voltage on VREF+ may range from 1.8 V to
VDDA. On WLCSP64+2, the VREF- pin is not available, it is internally connected to the ADC
ground (VSSA).
On 64-pin packages
The VREF+ and VREF- pins are not available, they are internally connected to the ADC
voltage supply (VDDA) and ground (VSSA).
1.1.2 Battery backup
To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be
connected to an optional standby voltage supplied by a battery or another source.
The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main
digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power
down reset (PDR) circuitry embedded in the Reset block.
If no external battery is used in the application, it is highly recommended to connect VBAT
externally to VDD.
1.1.3 Voltage regulator
The voltage regulator is always enabled after reset. It works in three different modes
depending on the application modes.
●in Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals)
●in Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the
contents of the registers and SRAM
●in Standby mode, the regulator is powered down. The contents of the registers and
SRAM are lost except for those concerned with the Standby circuitry and the Backup
domain.
Note: Depending on the selected package, there are specific pins that should be connected either
to VSS or VDD to activate or deactivate the voltage regulator. Refer to section "Voltage
regulator" in STM32F20xxx/21xxx datasheet for details.

Power supplies AN3320
8/29 Doc ID 18267 Rev 2
1.2 Power supply schemes
The circuit is powered by a stabilized power supply, VDD.
●Caution:
– The VDD voltage range is 1.8 V to 3.6 V (and 1.65 V to 3.6 V for WLCSP64+2
package)
●The VDD pins must be connected to VDD with external decoupling capacitors: one
single Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) for the package + one
100 nF Ceramic capacitor for each VDD pin.
●The VBAT pin can be connected to the external battery (1.65 V < VBAT < 3.6 V). If no
external battery is used, it is recommended to connect this pin to VDD with a 100 nF
external ceramic decoupling capacitor.
●The VDDA pin must be connected to two external decoupling capacitors (100 nF
Ceramic + 1 µF Tantalum or Ceramic).
●The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitors must be
connected on this pin. In all cases, VREF+ must be kept between 1.65 V and VDDA.
●Additional precautions can be taken to filter analog noise:
–V
DDA can be connected to VDD through a ferrite bead.
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REF+ pin can be connected to VDDA through a resistor (typ. 47 Ω).
●For the voltage regulator configuration, there are specific pins (REGOFF and IRROFF
depending on the package) that should be connected either to VSS or VDD to activate
or deactivate the voltage regulator specific. Refer to section "Voltage regulator" in
STM32F20xxx/21xxx datasheet for details.
●When the voltage regulator is enabled, VCAP1 and VCAP2 pins must be connected to
2*2.2 µF Ceramic capacitor.

AN3320 Power supplies
Doc ID 18267 Rev 2 9/29
Figure 2. Power supply scheme
1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and
1 µF) must be connected.
2. VREF+ is either connected to VREF or to VDDA.
3. N is the number of VDD and VSS inputs.
4. Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet to connect REGOFF and IRROFF
pins.
1.3 Reset & power supply supervisor
1.3.1 Power on reset (POR) / power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from
1.8 V.
The device remains in the Reset mode as long as VDD is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power down reset threshold, refer to the electrical characteristics in
STM32F20xxx/21xxx datasheets.
On WLCSP66 package if IRROFF pin is set to VDD (in that case REGOFF pin must not be
activated, refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details ),
the PDR is not functional. Then the VDD can lower below 1.8 V, but the external circuitry
must ensure that reset pin is activated when VDD/VDDA becomes below 1.65 V.
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Power supplies AN3320
10/29 Doc ID 18267 Rev 2
Figure 3. Power-on reset/power-down reset waveform
1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge is
1.70 V (typ.). Refer to STM32F20xxx/21xxx datasheets for actual value.
1.3.2 Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate
whether VDD is higher or lower than the PVD threshold. This event is internally connected to
EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD
output interrupt can be generated when VDD drops below the PVD threshold and/or when
VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge
configuration. As an example the service routine can perform emergency shutdown tasks.
Figure 4. PVD thresholds
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