ST STM32F7 Series Supplement

February 2017 DocID027559 Rev 5 1/54
1
AN4661
Application note
Getting started with STM32F7 Series MCU hardware development
Introduction
This application note is intended for system designers who require an hardware
implementation overview of the development board, with a focus on the features:
•Power supply,
•Package selection,
•Clock management,
•Reset control,
•Boot mode settings,
•Debug management.
This document describes the minimum hardware resources required to develop an
application based on the STM32F7 Series devices.
Reference documents
The following documents are available on www.st.com:
• Oscillator design guide for STM8S, STM8A and STM32 microcontrollers
application note (AN2867),
•STM32 microcontroller system memory boot mode application note (AN2606).
www.st.com

Contents AN4661
2/54 DocID027559 Rev 5
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7
1.1.2 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Independent SDMMC2 supply for STM32F767xx/STM32F777xx
and STM32F72xxx/STM32F73xxx devices . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.4 Independent DSI supply for STM32F769xx/STM32F779xx devices . . . 10
1.1.5 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.6 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 17
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3.4 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.5 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.6 Regulator OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.7 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 22
2 Alternate function mapping to pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.1 External user clock (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 25
3.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1 External clock (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 26
3.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 System bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DocID027559 Rev 5 3/54
AN4661 Contents
4
5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 31
5.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 32
6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 Ground and power supply (VSS,VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.7 Recommendations for the WLCSP180 package in the
STM32F769Ax/STM32F768Ax devices . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 Recommended PCB routing guidelines for
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 PCB stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3 Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4 High speed signal layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4.1 SDMMC bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4.2 Flexible memory controller (FMC) interface . . . . . . . . . . . . . . . . . . . . . . 45

Contents AN4661
4/54 DocID027559 Rev 5
8.4.3 Quadrature serial parallel interface (Quad-SPI) . . . . . . . . . . . . . . . . . . 46
8.4.4 Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.5 Package layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.5.1 BGA 216 0.8 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . . . 47
8.5.2 WLCSP143 0.4 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . 49
9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

DocID027559 Rev 5 5/54
AN4661 List of tables
5
List of tables
Table 1. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 3. STM32F7 Series bootloader communication peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. Flexible SWJ-DP assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. BGA 216 0.8 mm pitch package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 10. Wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of figures AN4661
6/54 DocID027559 Rev 5
List of figures
Figure 1. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. VDDUSB connected to external power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. VDDSDMMC connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Power supply overview (STM32F74xxx/STM32F75xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. STM32F7x2xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. STM32F7x3xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. PVD threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 19
Figure 13. NRST circuitry timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. BYPASS_REG supervisor reset connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. STM32CubeMX example screen-shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 21. Host to board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23. Typical layout for VDD/VSS pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. STM32F756NGH6 reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25. Four layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 26. Six layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 27. Example of bypass cap placed underneath the STM32F7 Series . . . . . . . . . . . . . . . . . . . 44
Figure 28. BGA 0.8mm pitch example of fan-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 29. Via fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 30. FMC signal fan-out routing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 31. 143-bumps WLCSP, 0.40 mm pitch routing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DocID027559 Rev 5 7/54
AN4661 Power supplies
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1 Power supplies
1.1 Introduction
The device requires a 1.8 to 3.6 V operating voltage supply (VDD), which can be reduced
down to 1.7 V with PDR OFF, as detailed in the product datasheets. The embedded linear
voltage regulator is used to supply the internal 1.2 V digital power.
The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM)
can be powered from the VBAT voltage when the main VDD supply is powered off.
1.1.1 Independent A/D converter supply and reference voltage
To improve the conversion accuracy, the ADC has an independent power supply which can
be separately filtered and shielded from noise on the PCB.
•The ADC voltage supply input is available on a separate VDDA pin.
•An isolated supply ground connection is provided on the pin VSSA.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF
. The voltage on VREF ranges from 1.8 V to VDDA.
When available (depending on package), VREF– must be externally tied to VSSA.
1.1.2 Independent USB transceivers supply
The USB transceivers are supplied from a separated VDDUSB power supply pin.
The VDDUSB supply can be connected either to VDD or an external independent power
supply (3.0 to 3.6V) for the USB transceivers (refer to Figure 1 and Figure 2). For example,
when the device is powered at 1.8V, an independent power supply 3.3V can be connected
to VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent
from VDD or VDDA but it must be the last supply to be provided and the first to disappear.
The following VDDUSB conditions must be respected:
•During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD.
•During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD.
•The VDDSUB rising and falling time rate specifications must be respected (refer to
operating conditions at power-up / power-down (regulator ON) table and operating
conditions at power-up / power-down (regulator OFF) table provided in the product
datasheet).
•In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
–TheV
DDUSB supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
If only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.

Power supplies AN4661
8/54 DocID027559 Rev 5
Figure 1. VDDUSB connected to VDD power supply
Figure 2. VDDUSB connected to external power supply.
In the STM32F7x3xx devices, the USB PHY HS sub-system uses an additional power
supply pin:
•The VDD12OTGHS pin is the output of the PHY HS regulator (1.2 V). An external
capacitor of 2.2 µF must be connected on the VDD12OTGHS pin.
Note: The PHY HS has another OTG_HS_REXT pin needed for calibration. This pin must be
connected to gnd via an external precise resistor (3 Kohm +/- 1%).
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DocID027559 Rev 5 9/54
AN4661 Power supplies
53
1.1.3 Independent SDMMC2 supply for STM32F767xx/STM32F777xx
and STM32F72xxx/STM32F73xxx devices
The VDDSDMMC is an independent power supply for SDMMC2 peripheral IOs (PD6, PD7,
PG9..12). It can be connected either to VDD or an external independent power supply.
For example, when the device is powered at 1.8V, an independent power supply 3.3V can
be connected to VDDSDMMC. When the VDDSDMMC is connected to a separated power
supply, it is independent from VDD and VDDA but it must be the last supply to be provided
and the first to disappear. The following VDDSDMMC conditions must be respected:
•During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than
VDD.
•During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower
than VDD.
•The VDDSDMMC rising and falling time rate specifications must be respected.
•In the operating mode phase, VDDSDMMC could be lower or higher than VDD: the
associated GPIOs (PD6, PD7, PG9..12) powered by VDDSDMMC are operating between
VDDSDMMC_MIN and VDDSDMMC_MAX. If VDDSDMMC = VDD, the associated GPIOs
powered by VDDSDMMC are operating between VDD_MIN and VDD_MAX.
Figure 3. VDDSDMMC connected to external power supply
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Power supplies AN4661
10/54 DocID027559 Rev 5
1.1.4 Independent DSI supply for STM32F769xx/STM32F779xx devices
The DSI (Display Serial Interface) sub-system uses several power supply pins which are
independent from the other supply pins:
•The VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI
DPHY. This supply must be connected to global VDD.
•The VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected
externally to VDD12DSI.
•The VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data
lanes pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.
•The VDDDSI pin is an isolated supply ground used for DSI sub-system.
If the DSI functionality is not used at all, then:
•The VDDDSI pin must be connected to global VDD.
•The VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor
is no more needed.
•The VSSDSI pin must be grounded.
1.1.5 Battery backup domain
Backup domain description
To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when
VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a
battery or by another source.
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
•PC14 and PC15 can be used as LSE pins only.
•PC13 can be used as tamper pin (TAMP1).
•PI8 can be used as tamper pin (TAMP2).
1.1.6 Voltage regulator
The voltage regulator is always enabled after reset. It works in three different modes
depending on the application modes.
•In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals).
•In Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the
contents of the registers and SRAM.
•In Standby mode, the regulator is powered down. The contents of the registers and
SRAM are lost except for those concerned with the standby circuitry and the backup
domain.
Note: Depending on the selected package, there are specific pins that should be connected either
to VSS or VDD to activate or deactivate the voltage regulator. Refer to the voltage regulator
section in the datasheet for more details.

DocID027559 Rev 5 11/54
AN4661 Power supplies
53
1.2 Power supply scheme
•VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins. The VDD pins must be connected to
VDD with external decoupling capacitors: one single tantalum or ceramic capacitor
(min. 4.7 F) for the package + one 100 nF ceramic capacitor for each VDD pin.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
The VDDA pin must be connected to two external decoupling capacitors (100 nF
ceramic + 1 F tantalum or ceramic).
•VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers. For example, when the device is powered at 1.8V, an
independent power supply 3.3V can be connected to VDDUSB.
The VDDUSB pin must be connected to two external decoupling capacitors (100 nF
ceramic + 1 F tantalum or ceramic).
•VBAT = 1.65 to 3.6 V: power supply for the RTC, the external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
The VBAT pin can be connected to the external battery (1.65 V < VBAT < 3.6 V). If no
external battery is used, it is recommended to connect this pin to VDD with a 100 nF
external ceramic decoupling capacitor.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 1.3.5: Internal reset OFF).
•The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, a 100 nF and a 1 F capacitors must be
connected on this pin. In all cases, VREF+ must be kept between (VDDA-1.2 V) and
VDDA with minimum of 1.7 V.
•Additional precautions can be taken to filter analog noise:
–V
DDA can be connected to VDD through a ferrite bead.
–TheV
REF+ pin can be connected to VDDA through a resistor (typ. 47 ).
•For the voltage regulator configuration, there is a specific BYPASS_REG pin (not
available on all the packages) that should be connected either to VSS or VDD to activate
or deactivate the voltage regulator specific.
Note: Refer to the voltage regulator section of the related device datasheet for more details.
•When the voltage regulator is enabled, VCAP1 and VCAP2 pins must be connected to
2*2.2 F low ESR < 2 ceramic capacitor. In the STM32F7x2Rx devices, only the
VCAP1 pin is available and must be connected to 4.7 µF low ESR between 0.1 and
0.2 ceramic capacitor.

Power supplies AN4661
12/54 DocID027559 Rev 5
Figure 4. Power supply overview (STM32F74xxx/STM32F75xxx)
1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and 1
F) must be connected.
2. VREF+ is either connected to VREF+ or to VDDA (depending on package).
3. VREF- is either connected to VREF- or to VSSA (depending on package).
4. 19 is the number of VDD and VSS inputs.
5. Refer to Section 1.3.7: Regulator ON/OFF and internal reset ON/OFF availability to connect
BYPASS_REG and PDR_ON pins.
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AN4661 Power supplies
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Figure 5. STM32F769xx/STM32F779xx power supply scheme
1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VDDA=VDD and VSSA=VSS.
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Figure 6. STM32F767xx/STM32F777xx power supply scheme
1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VDDA=VDD and VSSA=VSS.
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AN4661 Power supplies
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Figure 7. STM32F7x2xx power supply scheme
1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VDDA=VDD and VSSA=VSS.
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Figure 8. STM32F7x3xx power supply scheme
1. The VDDUSB allows supplying the PHY FS in PA11/PA12 and the PHY HS on PB14/PB15.
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AN4661 Power supplies
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2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA=VDD and VSSA=VSS.
1.3 Reset & power supply supervisor
1.3.1 Power-on reset (POR)/power-down reset (PDR)
The device has an integrated POR/PDR circuitry that allows a proper operation starting from
1.8 V.
The device remains in reset mode when VDD/VDDA is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power-down reset threshold, refer to the electrical characteristics of the
datasheet.
Figure 9. Power on reset/power down reset waveform
1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge
is 1.70 V (typ.). Refer to the product datasheets for the actual value.
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
1.3.2 Programmable voltage detector (PVD)
The PVD can be used to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
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A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to
indicate if VDD is higher or lower than the PVD threshold. This event is internally connected
to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers.
The PVD output interrupt can be generated when VDD drops below the PVD threshold
and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling
edge configuration. As an example the service routine could perform emergency shutdown
tasks.
Figure 10. PVD threshold
1.3.3 System reset
A system reset sets all the registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the backup domain (see Figure 11).
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset).
2. Window watchdog end of count condition (WWDG reset).
3. Independent watchdog end of count condition (IWDG reset).
4. A software reset (Software reset).
5. A low-power management reset.
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AN4661 Power supplies
53
Figure 11. Reset circuit
1.3.4 Internal reset ON
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
For more details about the internal reset ON, refer to the datasheets (DS10915, DS10916).
1.3.5 Internal reset OFF
This feature is available only on the packages featuring the PDR_ON pin. The internal
power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON
pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be
connected to VSS. Refer to Figure 12: Power supply supervisor interconnection with internal
reset OFF.
Figure 12. Power supply supervisor interconnection with internal reset OFF
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The supply ranges which never go below 1.8V minimum should be better managed by the
internal circuitry (no additional component needed, thanks to the fully embedded reset
controller).
When the internal reset is OFF, the following integrated features are no more supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•The brownout reset (BOR) circuitry must be disabled.
•The embedded programmable voltage detector (PVD) is disabled.
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
All the packages, except for the LQFP64 and the LQFP100, allow to disable the internal
reset through the PDR_ON signal when connected to VSS.
Figure 13. NRST circuitry timing example
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