ST STM32H74xI/G User manual

May 2019 AN4938 Rev 4 1/46
1
AN4938
Application note
Getting started with STM32H74xI/G and STM32H75xI/G
hardware development
Introduction
This application note is intended for system designers who develop applications based on
STM32H750 Value line, STM32H742, STM32H743/753, STM32H745/755 and
STM32H747/757 lines, and who need an implementation overview of the following
hardware features:
•Power supply
•Package selection
•Clock management
•Reset control
•Boot mode settings
•Debug management.
This document describes the minimum hardware resources required to develop an
application based on STM32H74xI/G and STM32H75xI/G microcontrollers.
Reference documents
The following documents are available on www.st.com:
•STM32H742xI/G and STM32H743xI/G datasheet
•STM32H745xI/G datasheet
•STM32H747xI/G datasheet
•STM32H750xB datasheet
•STM32H753xI/G datasheet
•STM32H755xI/G datasheet
•STM32H757xI/G datasheet
• Oscillator design guide for STM8S, STM8A and STM32 microcontrollers application note
(AN2867)
•STM32 microcontroller system memory boot mode application note (AN2606).
Table 1. Applicable products
Generic part numbers Corresponding product lines
STM32H74xI/G,
STM32H75xI/G
STM32H742, STM32H750 Value, STM32H743/753,
STM32H745/755, STM32H747/757
www.st.com

Contents AN4938
2/46 AN4938 Rev 4
Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Independent analog supply and reference voltage . . . . . . . . . . . . . . . . . 7
2.1.2 USB transceiver independent power supply . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.4 LDO voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.5 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 15
2.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3 Analog voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.4 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.5 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.6 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.7 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Alternate function mapping to pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 HSE oscillator clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.1 External user clock (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 22
4.2 LSE oscillator clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.1 External clock (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 23
4.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 System bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AN4938 Rev 4 3/46
AN4938 Contents
4
6 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.1 TPIU trace port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.2 External debug trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 31
6.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 31
7 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.3 Ground and power supply (VSS,VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 Reference design description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Recommended PCB routing guidelines for
STM32H74xI/G and STM32H75xI/G devices . . . . . . . . . . . . . . . . . . . . . 37
9.1 PCB stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3 Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4 High speed signal layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.1 SDMMC bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.2 Flexible memory controller (FMC) interface . . . . . . . . . . . . . . . . . . . . . . 40

Contents AN4938
4/46 AN4938 Rev 4
9.4.3 Quadrature serial parallel interface (QUADSPI) . . . . . . . . . . . . . . . . . . 41
9.4.4 Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

AN4938 Rev 4 5/46
AN4938 List of tables
5
List of tables
Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3. STM32H74xI/G and STM32H75xI/G bootloader communication peripherals . . . . . . . . . . 26
Table 4. TPIU trace pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5. External debug trigger pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Flexible SWJ-DP assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

List of figures AN4938
6/46 AN4938 Rev 4
List of figures
Figure 1. VDD33USB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. VDD33USB/VDD50USB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. PVD threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 18
Figure 8. NRST circuitry timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. STM32CubeMX example screen-shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Host to board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. STM32H753XI reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. Four layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. Six layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Decoupling capacitor placement depending on package type . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Example of decoupling capacitor placed underneath
the STM32H74xI/G and STM32H75xI/G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AN4938 Rev 4 7/46
AN4938 General information
45
1 General information
This document applies to STM32H74xI/G and STM32H75xI/G Arm®(a)-based devices.
2 Power supplies
2.1 Introduction
STM32H74xI/G and STM32H75xI/G devices require a 1.71 to 3.6 V operating voltage
supply (VDD), which can be reduced down to 1.62 V by using an external power supervisor
and connecting PDR_ON pin to VSS (refer to the datasheets for details).
The digital power can be supplied either by a internal system supply voltage regulator or
directly by an external supply voltage. This digital power voltage can be set dynamically at
different values, the highest value allowing to achieve the maximum performance.
The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM)
can be powered from the VBAT voltage (1.2 to 3.6 V) when the main VDD supply is powered
OFF.
Note: Refer to the product datasheets for more details on the supply voltage range.
2.1.1 Independent analog supply and reference voltage
To improve analog peripheral performance, the analog peripherals feature an independent
power supply which can be separately filtered and shielded from noise on the PCB:
•The analog supply voltage input is available on a separate VDDA pin.
•An isolated supply ground connection is provided on the pin VSSA.
To ensure a better accuracy of low-voltage inputs, the user can connect a separate external
reference voltage on VREF+.
In addition, the STM32H74xI/G and STM32H75xI/G microcontrollers embed an internal
voltage reference buffer, which can be used as voltage reference for ADCs, DACs, as well
as external components through the VREF+ pin. This buffer supports four voltages that can
be configured through the VREFBUF_CSR register.
When available (depending on the package), VREF– pin must be externally tied to VSSA.
VDDA minimum value (VDDA_MIN) depends on the analog peripheral and on whether a
reference voltage is provided or not:
•If no analog peripheral is used, VDDAmin equals 0 V.
•When an ADC or a comparator is used, VDDA_MIN equals 1.62 V.
•When a DAC is used, VDDA_MIN equals 1.8V.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Power supplies AN4938
8/46 AN4938 Rev 4
•When an OPAMP is used, VDDA_MIN equals 2.0 V.
•When a reference voltage (VREFBUF_OUT) is provided by the device on VREF+ pin,
VDDA_MIN depends on the required level for this voltage.
Note: Refer to the product datasheets for more details on VREF+ reference voltage range.
2.1.2 USB transceiver independent power supply
There are different ways to supply the USB transceivers, depending on VDD33USB and
VDD50USB availability:
•When the VDD50USB pin is available, this pin can be used to supply an internal
regulator dedicated to USB transceivers. In this case, VDD50USB pin should receive a
voltage ranging from 4.0 to 5.5 V, typically supplied from the VBUS line of the USB
connector. The regulated power (3.0 to 3.6 V) is available on VDD33USB.
In this configuration VDD50USB voltage must respect the following condition:
An external capacitor must be connected to VDD33USB.
•When the VDD33USB pin is available, this pin can be used to supply the internal
transceiver. In this case, VDD33USB pin should receive a voltage ranging from 3.0 to
3.6 V. If VDD50USB is also available, it must be connected to VDD33USB. As an
example, when the device is powered at 1.8 V, an independent 3.3 V power supply can
be applied to VDD33USB.
When VDD33USB is connected to a separate power supply, it is independent from VDD
and VDDA. It must be the last supply applied and the first supply switched OFF. The
following conditions must be respected (see Figure 2):
– During the power-on and power-down phases (VDD < VDD minimum value),
VDD33USB should always be lower than VDD.
–V
DD33USB rising and falling time specifications must be respected (refer to table
power-up/power-down operating conditions (regulator ON) and table power-
up/power-down operating conditions (regulator OFF) provided in the device
datasheets).
– In operating mode, VDD33USB can be either lower or higher than VDD:
If a USB interface is used (USB OTG_HS/OTG_FS), the associated GPIOs
powered by VDD33USB operate between VDD33USB_MIN and VDD33USB_MAX(see
Figure 2).
VDD33USB supplies both USB OTG_HS and USB OTG_FS transceivers. If only
one USB transceiver is used in the application, the GPIOs associated to the other
USB transceiver are still supplied by VDD33USB.
If no USB interface is used (USB OTG_HS/OTG_FS), the associated GPIOs
powered by VDD33USB operate in VDD range (between VDD_MIN and VDD_MAX).
In the above two configurations, an external capacitor must be connected to
VDD33USB.
•When neither VDD33USB nor VDD50USB is available, VDD pins are use to supply
USB transceivers and must be in the range of 3.0 to 3.6 V for the transceiver to operate
correctly.
VDD50USB VDD 300 mV+<

AN4938 Rev 4 9/46
AN4938 Power supplies
45
Figure 1. VDD33USB connected to VDD power supply
Figure 2. VDD33USB/VDD50USB connected to external power supply
1. VDDx can be any power supply voltage among VDDA, VDD33USB, VDD50USB and VDDDSI.
2. If the SMPS is available, VDD and VDDSMPS must be wired together to follow the same voltage sequence.
06Y9
WLPH
3RZHURQ 3RZHU
GRZQ
2SHUDWLQJPRGH
9''B0$;
9''B0,1
9''
9'' 9''86%
06Y9


9%25

2SHUDWLQJPRGH3RZHURQ 3RZHUGRZQ WLPH
9
9'';

9''
,QYDOLGVXSSO\DUHD 9'';9''P9 9'';LQGHSHQGHQWIURP9''

Power supplies AN4938
10/46 AN4938 Rev 4
2.1.3 Battery backup domain
Backup domain description
To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when
VDD is turned off, VBAT pin can be connected to an optional 1.2-3.6 V standby voltage
supplied by a battery. Otherwise, VBAT must be connected to another source, such as VDD.
When the backup domain is supplied by VBAT (analog switch connected to VBAT since VDD
is not present), the following functions are available:
•PC14 and PC15 can be used as LSE pins only.
•PC13 can be used as tamper pin (TAMP1).
•PI8 can be used as tamper pin (TAMP2).
•PC1 can be used as tamper pin (TAMP3).
During tRSTTEMPO (temporization at VDD startup) or after a power-down reset (PDR) is
detected, the power switch between VBAT and VDD remains connected to VBAT
.
During the startup phase, if VDD is established in less than tRSTTEMPO and it is higher than
VBAT + 0.6 V, a current may be injected into VBAT pin through an internal diode connected
between VDD and the power switch (VBAT). If the power supply/battery connected to the
VBAT pin cannot support this current injection, it is strongly recommended to connect an
external low-drop diode between this power supply and the VBAT pin.
Refer to the device datasheets for the actual value of tRSTTEMPO.
Battery charging
When VDD is present, the external battery connected to VBAT can be charged through an
internal resistance. This operation can be performed either through an internal 5 kΩor
1.5 kΩresistor. The resistor value can be configured by software.
Battery charging is automatically disabled in VBAT mode.
2.1.4 LDO voltage regulator
The LDO voltage regulator is always enabled after reset with a default output level set to
power scale 3 (VOS3). The LDO can operate in three different modes depending on the
application operating modes:
•In Run mode, the regulator supplies full power to the core and the digital domain.
•In Stop mode, the regulator supplies low power to the core and to the digital domain,
thus preserving the contents of the registers and SRAM.
•In Standby mode, the regulator is powered down. The contents of the registers and
SRAM are lost except for those related to the standby circuitry and the backup domain.
In Run and Stop mode, the LDO voltage regulator can be dynamical scaled by software to
different voltage levels: VOS0, VOS1, VOS2, and VOS3, SVOS3, SVOS4 or SVOS5.
The LDO regulator requires a capacitor on VCAP pins.

AN4938 Rev 4 11/46
AN4938 Power supplies
45
2.1.5 SMPS step-down converter
To optimize power consumption, some devices embed a high power-efficient DC/DC non-
linear switched-mode power supply voltage down-converter regulator. It can be enabled via
the SDEN bit of the PWR_CR3 register.
The SMPS can be used to deliver power either in internal or external supply mode.
1. Internal supply mode (Direct mode):
VCORE domain direct supply follows the device system operating modes (Run, Stop
and Standby) where the output voltage is set according to the voltage scaling
configured via VOS and SVOS bits.
The SMPS can also supply the internal voltage regulator (LDO) in Normal operating
mode or High-performance mode according to SDEXTHP bit setting in PWR_CR3.
2. External supply mode
In this mode, the SMPS can be used to supply external circuits. It operates in MR mode
(SDEXTHP bit set to 1 in PWR_CR3) in order to achieve a high performance with an
output voltage of 2.5 V or 1.8 V (configured through SDLEVEL bits of PWR_CR3).

Power supplies AN4938
12/46 AN4938 Rev 4
2.2 Power supply scheme
Power supplies
•VDD = 1.62 to 3.6 V: external power supply for I/Os, Flash memory and system analog
blocks such as reset and PLL
This power supply is provided externally through VDD pins. VDD pins must be
connected to VDD with external decoupling capacitors: one single tantalum or ceramic
capacitor (of 4.7 µF minimum capacitance) for the package and a 100 nF ceramic
capacitor for each VDD pin.
When VDD is lower than 1.71 V, an external reset controller is required.
Note: VDD minimum value of 1.62 V is obtained when the internal reset controller is OFF (refer to
Section 2.3.6: Internal reset OFF).
•VSSA, VDDA = 1.62 to 3.6 V: external analog power supplies for ADCs, DACs and
OPAMPs.
VDDA pin must be connected to two external decoupling capacitors (100 nF ceramic
capacitors and a 1 µF tantalum or ceramic capacitor).
•VDD33USB and VDD50USB: external power supplies for USB transceiver
When VDD50USB is used to provide power, this pin must be connected to the USB
connector VBUS line and to a 4.7 µF decoupling capacitor (CIN). In addition,
VDD33USB must be connected to a 1 µF capacitor and its maximum ESR should be
600 mΩ.
When VDD33USB is used to power the USB transceiver (3.0 to 3.6 V), if the
VDD50USB pin is available, it must connected to VDD33USB, which must be
connected to two external decoupling capacitors (a 100 nF ceramic capacitor and a
1 µF tantalum or ceramic capacitor).
•VBAT = 1.2 to 3.6 V: power supply for the RTC, the external 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
The VBAT pin can be connected to the external battery (1.2 V < VBAT < 3.6 V). If no
external battery is used, it is mandatory to connect this pin to an external power supply:
as an example, VBAT pin can be connected to VDD through a 100 nF external ceramic
decoupling capacitor.
•VREF+ external reference voltage for analog peripherals
VREF+ pin can be connected to VDDA external power supply. If a separate external
reference voltage is applied to VREF+, a 100 nF and a 1 F capacitors must be
connected on this pin. In all cases, VREF+ must be kept below VDDA. VREF+ lower limit
is 2 V when VDDA is above 2 V and the ADC is used, otherwise it is 1.62 V.
•VDDLDO = 1.62 to 3.6 V: external power supply for voltage regulator
When the LDO voltage regulator is enabled, both VCAP1 and VCAP2 pins must be
connected to a 2.2 µF ceramic capacitor with a low ESR (< 100 m). It is
recommended to connect VCAP1 pin to VCAP2 pin (for more details, refer to
Figure 18: STM32H753XI reference schematic).
If VCAP3 is available, it must be connected to the other VCAP pins but not additional
capacitor is required. In addition, the VDDLDOx pins must be connected together and
to a 4.7 µF tantalum or ceramic capacitor.

AN4938 Rev 4 13/46
AN4938 Power supplies
45
Four additional power supplies and pins are used on devices that feature the SMPS:
•VDDSMPS = 1.62 to 3.6 V: SMPS step-down converter power supply
VDDSMPS must be kept at the same voltage level as VDD.
VDDSMPS pin must be connected to an external 4.7 F capacitor with a 100 m
equivalent series resistance (ESR).
VSSSMPS is the SMPS step-down converter ground.
•VLXSMPS: SMPS step-down converter supply
VLXSMPS output is coupled to a 2.2 H inductor with a 220 pF external capacitor.
•VFBSMPS = VCORE = 1.8 or 2.5 V: external SMPS step-down converter sense feedback
voltage
VFBSMPS input pin must be connected to a 10 F capacitor with a 20 mESR.
Note: Refer to the corresponding datasheet for more details regarding the external components
required for the SMPS.
Four additional power supplies and pins are available to supply the internal DSI regulator on
STM32H7x7I/G devices:
•VDDDSI = 1.8 to 3.6 V: supply voltage for the DSI internal regulator
VDDDSI is the DSI regulator supply input, while VSSDSI is the DSI regulator ground.
•VDD12DSI = 1.15 to 1.3 V: optional supply voltage for the DSI PHY (DSI regulator OFF)
•VCAPDSI: DSI regulator output
To achieve a better dynamic performance of the regulator, VCAPDSI pin must be
connected to an external capacitor, which recommended value is 2.2 µF.
Additional precautions can be taken to filter analog noise:
•VDDA can be connected to VDD through a ferrite bead.
•The VREF+ pin can be connected to VDDA through a resistor (typically 47 Ω).

Power supplies AN4938
14/46 AN4938 Rev 4
Figure 3. Power supply overview
1. The SMPS is available only on STM32H7x5I/G and STM32H7x7I/G microcontrollers.
2. The internal DSI regulator and PHY are available only on STM32H7x7I/G microcontrollers.
06Y9
%.83
,2V
9''GRPDLQ
$QDORJGRPDLQ
&RUHGRPDLQ9&25(
%DFNXSGRPDLQ
'GRPDLQ
6\VWHP
ORJLF
(;7,
3HULSKHUDOV
5$0
'GRPDLQ
&38SHULSKHUDOV
5$0
/HYHOVKLIWHU
23$03
&RPSDUDWRU
9ROWDJH
UHJXODWRU
$'&'$&
)ODVK
'GRPDLQ
SHULSKHUDOV
5$0
3RZHU
VZLWFK
3RZHUVZLWFK
9&$3
966
9''/'2
9%$7
9''$
95()
95()
966$
%DFNXS
UHJXODWRU
9''
%DFNXS
5$0
3RZHUVZLWFK
+6,&6,
+6,
+6(3//V
,2V
3RZHU
VZLWFK
86%
UHJXODWRU
9''86% 9''86%
966
966
966
5()B%8)
966
,2
ORJLF
95()
86%
,2V
966
96:
/6,/6(
57&:DNHXS
ORJLFEDFNXS
UHJLVWHUV
5HVHW
,2
ORJLF
9%.3
9%$7
FKDUJLQJ
95()
9''$
9%$7
WR9
[)
1[Q)
[)
Q)
Q)[)
)
Q)
9''
9''/'2
Q)[)
95()
9''86% 9''86%
6WHS
'RZQ
&RYHUWHU
6036
9''6036
9/;6036
9)%6036
9666036
9'''6,
'6,
3+<
'6,
UHJXODWRU
966'6,
9'''6,
9&$3'6,

)

AN4938 Rev 4 15/46
AN4938 Power supplies
45
2.3 Reset and power supply supervisor
2.3.1 Power-on reset (POR)/power-down reset (PDR)
The devices have an integrated POR/PDR circuitry that allows a proper operation starting
from 1.71 V.
The devices remain in reset mode when VDD is below a specified threshold, VPOR/PDR,
without the need for an external reset circuit. For more details concerning the power
on/power-down reset threshold, refer to the electrical characteristics of the datasheet.
Figure 4. Power on reset/power down reset waveform
1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.66 V (typical) and VPOR/PDR falling edge
is 1.62 V (typical). Refer to the device datasheets for the actual values.
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
2.3.2 Programmable voltage detector (PVD)
The PVD can be used to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the PWR powercontrol/status register (PWR_CSR1), to
indicate if VDD is higher or lower than the PVD threshold. This event is internally connected
to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers.
The PVD output interrupt can be generated when VDD drops below the PVD threshold
and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling
edge configuration. As an example the service routine could perform emergency shutdown
tasks.
06Y9
9''
7
325
3'5
K\VWHUHVLV
7HPSRULVDWLRQ75677(032
SZUBSRUBUVW

Power supplies AN4938
16/46 AN4938 Rev 4
Figure 5. PVD threshold
2.3.3 Analog voltage detector (AVD)
The AVD can be used to monitor VDDA power supply by comparing it to a threshold selected
through the ALS[1:0] bits of the PWR power control register (PWR_CR1). The threshold
value can be configured to 1.7, 2.1, 2.5 or 2.8 V (refer to the devices datasheets for the
actual values).
The AVD is enabled by setting the AVDEN bit in PWR_CR1 register. An interrupt can be
raised when VDDA goes above or below the configured threshold.
2.3.4 System reset
A system reset sets all the registers to their default values except the reset flags in the clock
controller RCC_RSR register and the registers in the backup domain (see Figure 6).
A system reset (nreset signal) resets all registers to their default values except for the reset
flags in the clock controller RCC_RSR (or RCC_C1_RSR) register and the registers in the
backup domain.
A system reset can be generated when one of the following events occurs:
•A low level on the NRST pin (external reset)
•A reset from the brownout reset block via the pwr_bor_rst internal signal
•The input voltage (VDD) drops below a threshold level (pwr_por_rst)
•The independent watchdog end-of-count condition (iwdg1_out_rst)
•A window watchdog end -of-count condition (wwdg1_out_rst)
•A reset from low-power mode (lpwr_rst)
•A software reset from the Arm®Cortex®-M7 core, generated via the SFTRESET signal.
069
9''
P9
K\VWHUHVLV
39'WKUHVKROG
39'RXWSXW
939'
ULVLQJHGJH
939'
IDOOLQJHGJH

AN4938 Rev 4 17/46
AN4938 Power supplies
45
Figure 6. Reset circuit
2.3.5 Internal reset ON
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
For more details about the internal reset ON, refer to the datasheets.
2.3.6 Internal reset OFF
This feature is available only on the packages featuring the PDR_ON pin. The internal
power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON
pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be
connected to VSS. Refer to Figure 7: Power supply supervisor interconnection with internal
reset OFF.
06Y9
9''
)LOWHU
3XOVHJHQHUDWRU
VPLQ
538
25
QUHVHW6\VWHP5HVHW
1567
([WHUQDOUHVHW
&5
5&&
6)75(6(7
OSZUBUVW
ZZGJBRXWBUVW
LZGJBRXWBUVW
SZUBSRUBUVW
SZUBERUBUVW

Power supplies AN4938
18/46 AN4938 Rev 4
Figure 7. Power supply supervisor interconnection with internal reset OFF
The supply ranges which never go below 1.71 V minimum should be better managed by the
internal circuitry (no additional component needed, thanks to the fully embedded reset
controller).
When the internal reset is OFF, the following integrated features are no more supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•The brownout reset (BOR) circuitry must be disabled.
•The embedded programmable voltage detector (PVD) is disabled.
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
All the packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to VSS.
06Y9
670+
3'5B21 5HVHW
FRQWUROOHU
9ROWDJHUHJXODWRU 9W\S9PLQ
1567
Nȍ
)
9ROWDJHVXSHUYLVRU
DFWLYHORZRSHQGUDLQ
RXWSXW
287
6701
9'' 9%$7
9''
966966$

AN4938 Rev 4 19/46
AN4938 Power supplies
45
Figure 8. NRST circuitry timing example
2.3.7 Bypass mode
The power management unit can be bypassed. This feature can be configured by software.
When bypassed, the core power supply should be provided through VCAPx pins connected
together.
In Bypass mode, the internal voltage scaling is not managed internally, and the external
voltage value must be consistent with the targeted maximum frequency (see datasheet for
the actual VOS level).
In Stop mode, the best trade-off between power consumption and performance can be
obtained by preselecting the SVOS level in the PWR_CR1 register (refer to the product
datasheet for details on SVOS level).
In Standby mode the external source will be switched off and the VCORE domains powered
down. The external source will be switched on when exiting Standby mode.
In Bypass mode, the external voltage must be present before or at the same time as VDD. To
avoid conflict with the LDO, the external voltage must be kept above 1.15 V until the LDO is
disabled by software.
2SHUDWLRQ 3RZHU'RZQSKDVH3RZHU2QSKDVH
069
9''
WLPH
9
9''GXULQJRSHUDWLRQNHSWDERYH9
WLPH
1567
1567.HSWORZE\
LQWHUQDOFLUFXLWU\
9''
5HVHWE\
LQWHUQDO
VRXUFHV
1567IRUFHGORZE\H[WHUQDO
VXSHUYLVRU
VXSHUYLVRU
ORZWULSSRLQW
VXSHUYLVRU
KLJKWULSSRLQW
1567.HSWORZE\
H[WHUQDOVXSHUYLVRU
75677(032
7VXSHUYLVRU
7VXSHUYLVRU!75677(032
7VXSHUYLVRU75677(032

Alternate function mapping to pins AN4938
20/46 AN4938 Rev 4
3 Alternate function mapping to pins
In order to easily explore the peripheral alternate functions mapping to the pins it is
recommended to use the STM32CubeMX tool available on http://www.st.com.
Figure 9. STM32CubeMX example screen-shot