ST STM8L Installation and operating instructions

July 2013 DocID16139 Rev 5 1/42
AN3029
Application note
Getting started with STM8L and STM8AL
Introduction
This application note complements the information in the STM8L and STM8AL datasheets
by describing the minimum hardware and software environment required to build an
application around an STM8L or STM8AL 8-bit microcontroller device.
A brief description of the principal hardware components is given. The power supply,
analog-to-digital converter (ADC), clock management, and reset control are described in
some detail. In addition, some hardware recommendations are given. This application note
also contains detailed reference design schematics with descriptions of the main
components. The STM8 development tools and software toolchain are common to STM8L,
STM8S, STM8AL, and STM8AF and are presented in Section 8, and Section 9. Section 10
describes how to set up the STM8 development environment. Finally, Section 11 provides a
list of relevant documentation and online support resources.
Table 1. Applicable products
Product family Part numbers
Microcontrollers
– STM8L051/52
– STM8L101
– STM8L151C2/K2/G2/F2 and STM8L151C3/K3/G3/F3
– STM8L151x4, STM8L151x6, STM8L152x4, STM8L152x6
– STM8L151x8, STM8L152x8, STM8L151R6, STM8L152R6, STM8L162R8,
STM8L162M8
– STM8AL313x, STM8AL314x, STM8AL316x, STM8AL3L4x, STM8AL3L6x
www.st.com

Contents AN3029
2/42 DocID16139 Rev 5
Contents
1 Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Clock management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.2 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Hardware reset implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.7 User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.8 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DocID16139 Rev 5 3/42
AN3029 Contents
3
7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1.1 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1.2 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2 STice emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2.1 STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2.2 STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2.3 In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.3 RLink and STLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.1 Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.3 Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 Setting up the STM8 development environment . . . . . . . . . . . . . . . . . 28
10.1 Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.2 Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.2.1 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.2.2 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.3 Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3.1 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3.2 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3.3 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3.4 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3.5 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.3.6 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Documentation and online support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

List of tables AN3029
4/42 DocID16139 Rev 5
List of tables
Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DocID16139 Rev 5 5/42
AN3029 List of figures
5
List of figures
Figure 1. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Typical layout of VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17. STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. STM8 firmware library online help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22. Connecting the debug instrument to the STM8L101-EVAL evaluation board . . . . . . . . . . 34
Figure 23. Connecting the debug instrument to the STM8L152x-EVAL evaluation board . . . . . . . . . 35
Figure 24. STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 25. STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 26. STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Hardware requirements summary AN3029
6/42 DocID16139 Rev 5
1 Hardware requirements summary
To build an application around an STM8L or STM8AL device, the application board should
provide the following features:
•Power supply (mandatory)
•Clock management (optional)
•Reset management (optional)
•Debugging tool support: Single wire interface module (SWIM) connector (optional)
2 Power supply
2.1 Power supply overview
The STM8L or STM8AL can be supplied through a 1.65 V to 3.6 V external source (1.8 V to
3.6 V for STM8L05xxx). For medium density STM8L15xxx, medium density
STM8AL31xx/STM8AL3Lxx, and high density STM8L15xxx/STM8L162xx with BOR, the
power supply must be above 1.8 V at power-on and can go down to 1.65 V at power-down.
An on-chip power management system provides the constant digital supply to the core logic,
both in normal and low power modes. This guarantees that the logic consumes a constant
current over the voltage range. It is also capable of detecting voltage drops and generate
reset to avoid heratic behavior.
The STM8L and STM8AL devices provide:
•Depending on packages, one pair of pads (VDD/VSS), or several pairs of pads
(VDDx/VSSx) from 1.65 V or 1.8 V to 3.6 V.
All VDDx and VSSx must be at the same potential respectively. The VDDx pins must be
connected to VDD with external decoupling capacitors: one 100 nF Ceramic capacitor
for each VDDx pin and one single 1 µF Tantalum or Ceramic capacitor.
The STM8L15xxx, STM8AL31xx, and STM8L162xx devices also provide in some
packages:
•One pair of pads, VDDA/VSSA, dedicated to analog functions. VDDA and VSSA must be
at the same potential respectively as VDD and VSS. Refer to Section 3: Analog-to-digital
converter (ADC) for more details. The VDDA pin must be connected to two external
decoupling capacitors (one 100 nF Ceramic capacitor and one single 1 µF Tantalum or
Ceramic capacitor). Additional precautions can be taken to filter analog noise: VDDA
can be connected to VDD through a ferrite bead.
STM8L152xx, STM8AL3Lxx and STM8L162xx devices manage the supply voltage needed
by the LCD in three different ways (see Figure 1):
1. If the LCD feature is not used, connect the VLCD pin to VDD.
2. Apply to VLCD the voltage to be applied to the LCD.
3. Leave the STM8L152xx/STM8L162xx/STM8AL3Lxx to provide the correct voltage, via
its programmable LCD booster, by connecting the VLCD pin to a 1µF capacitor.

DocID16139 Rev 5 7/42
AN3029 Power supply
41
Figure 1. Power supply
1. Optional: if a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and 1
µF) must be connected. VREF+ is either connected to VDDA or VREF.
2. N is the number of VDD and VSS inputs.
Note: The capacitors must be connected as close as possible to the device supplies.
Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be
connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance
ground must be connected as close as possible to VSS.
2.2 Main operating voltages
STM8L and STM8AL devices are processed in 0.13 µm technology. The STM8L and
STM8AL core and I/O peripherals need different power supplies. In fact, STM8L and
STM8AL devices have an internal regulator with a nominal target output of 1.8 V.
MS30982V1
VLCD
STM8L/STM8AL
N × 100 nF
VDD
+ 1 × 10 μF
100 nF + 1 μF
100 nF + 1 μF
(note 1)
VLCD VREF+
VDDA
VSSA
VDD 1/2/... /N
VSS 1/2/... /N
VREF
VDD
1 μF
(optional)
(note 2)
(note 2)

Power supply AN3029
8/42 DocID16139 Rev 5
2.3 Power-on/power-down reset (POR/PDR)
The input supply to the main and low power regulators is monitored by a power-on/power-
down reset circuit. The monitoring voltage begins at 0.7 V.
During power-on, the POR/PDR keeps the device under reset until the supply voltages (VDD
and VDDA) reach their specified working area. Maximum power on time tVDD[max] must be
respected, as the internal reset provided for supply stabilization is maintained for ~1 ms.
At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a
reset release is defined in the electrical characteristics section of the product datasheets.
A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.
The POR/PDR also generates a reset when the supply voltage drops below the VPDR
threshold (isolated and repetitive events).
Correct device reset during power-on sequence is guaranteed when tVDD[max] is respected.
It is recommended to use an internal BOR or an external reset circuit (especially for
STM8L101xx devices) to ensure correct device reset during power-down when VPDR < VDD
< VDD[min].
For better power monitoring, the STM8L15xxx, STM8L162xx, STM8AL31xx, and
STM8AL3Lxx provide a brown out reset (BOR) and programmable power voltage detection
(PVD) for an earlier detection of voltage drop.
Recommendations
All pins need to be properly connected to the power supplies. These connections, including
pads, tracks and vias should have the lowest possible impedance. This is typically achieved
with thick track widths and preferably dedicated power supply planes in multi-layer printed
circuit boards (PCBs).
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C)
at 100 nF with one chemical C (1..2 µF) in parallel on the STM8L/STM8AL devices. The
ceramic capacitors should be placed as close as possible to the appropriate pins, or below
the appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF,
but exact values depend on the application needs. Figure 2 shows the typical layout of such
a VDD/VSS pair.
Figure 2. Typical layout of VDD/VSS pair
MS32523V1
Via to VSS Via to VDD
Cap.
VDD VSS
STM8

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AN3029 Analog-to-digital converter (ADC)
41
3 Analog-to-digital converter (ADC)
This section does not apply to STM8L101xx devices.
3.1 Analog power
For some packages, the ADC unit has an independent, analog supply voltage, isolated on
input pin VDDA, which allows the ADC to accept a very clean voltage source. This analog
voltage, VDDA, should be identical to the digital voltage supply on pin VDD. To filter some
noise, a ferrite bead can be added between VDD and VDDA. This ferrite bead should be
chosen according to the frequencies to be filtered.
Some packages also provide a separate external analog reference voltage input for the
ADC unit on the VREF+ pin. This gives better accuracy on low voltage input as follows:
•The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitor must be
connected on this pin. To compensate for peak consumption on VREF
, the 1 µF
capacitor may be increased to 10 µF when the sampling speed is low. In all cases,
VREF+ must be kept between 2.4 V and VDDA. If VDDA is below 2.4, VREF+ must be
equal to VDDA. This input is internally bonded to VDDA in the devices that have no
internal VREF+ pin.
•VREF- (input, analog reference negative): The lower/negative reference voltage is
internally bonded to VSSA.
3.2 Analog input
The devices include up to 28 analog input channels (including four fast channels), each
multiplexed with an I/O, which are converted by the ADC one at a time.
The external input impedance (RAIN) max value is 50 kΩ. The four fast channels can convert
at maximum speed (1 MHz) if RAIN is less than 0.5 kΩ.
Please refer to Figure 3.
Figure 3. Analog input interface
Please refer to the applicable datasheets and reference manuals for more details.
MS32530V1
Sample and hold
ADC converter
12-bit
converter
RADC
CADC
VT
0.6 V
VT
0.6 V
VDD
AINx
RAIN
Cparasitic IL
VAIN

Clock management AN3029
10/42 DocID16139 Rev 5
4 Clock management
The STM8L101xx devices have no external clock, so no precautionary measures are
needed.
4.1 Clock management overview
STM8L05xxx, STM8L15xxx, STM8L162xx, STM8AL31xx and STM8AL3Lxx devices offer a
flexible way of selecting the core and peripheral clocks (ADC, memory, and digital
peripherals). The devices have internal and external clock source inputs, both of which have
a high speed and a low speed version. Any of those four clocks can be use for the CPU and
most of the peripherals through a programmable prescaler. An I/O can be programmed as
output clock (CCO) to reflect one of the four clocks (with or without prescaling).
The signal which leaves the I/O represents an output clock (CCO) divided by a division
factor.
4.2 Internal clocks
STM8L and STM8AL devices have two kinds of internal clock: A high speed internal clock
(HSI) running at 16 MHz and a low speed internal clock (LSI) running at 38 kHz.
After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.
4.3 External clock
STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices have
two kinds of external clock: A high speed external clock (HSE) running at up to 16 MHz and
a low speed external clock (LSE) running at 32.768 kHz.
4.3.1 HSE clock
STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices can
connect to an external crystal or an external oscillator.
Note: When no external clock is used, OSCIN and OSCOUT can be used as general purpose
I/Os.
Figure 4 describes the external clock connections.
External clock
•Frequency: 0 kHz … 16 MHz
•Input hysteresis: 100 mV
Caution: Without prescaler, a duty cycle of 45/55 % maximum must be respected at high speed

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AN3029 Clock management
41
Crystal/ceramic resonator
•Frequency range: 1 to 16 MHz
•Stabilization time: Programmable from 1 to 4096 cycles
•Oscillation mode: Preferred fundamental
•Output duty cycle: Max 55/45%
•I/Os: Standard I/O pins multiplexed with OSCIN and OSCOUT
•Cload: 10 to 20 pF
•Drive level maximum: at least 100 µW
The values of the load capacitors CL1 and CL2 are heavily dependent on the crystal type and
frequency. Refer to the datasheet of the crystal manufacturer to select the capacitances. For
best oscillation stability, CL1 and CL2 normally have the same value. Typical values are in
the range from below 20 pF up to 40 pF (cload: 10 to 20 pF). The parasitic capacitance of
the board layout also needs to be considered and typically adds a few pF to the component
values (refer to AN2867).
A clock security system prevents any CPU fatal error from a HSE failure, as it safely
switches to HSI.
Figure 4. HSE clock sources
Hardware configuration
External clockCrystal/ceramic resonators(1)
1. The value of REXT depends on the crystal characteristics. A 0 Ωresistor works well with most oscillators
but, it is not optimal. A typical value is in the range 5 to 6 RS(resonator series resistance). To fine-tune the
REXT value, refer to AN2867 (Oscillator design guide for ST microcontrollers).
MS32524V1
OSCIN OSCOUT
External source
STM8
(I/O available)
MS32529V1
Load capacitors
STM8
CL2
CL1
Q1
OSCIN OSCOUT
REXT (1)

Clock management AN3029
12/42 DocID16139 Rev 5
Recommendations
In the PCB layout all connections should be as short as possible. Any additional signals,
especially those that could interfere with the oscillator, should be locally separated from the
PCB area around the oscillation circuit using suitable shielding.
4.3.2 LSE clock
The low-speed external clock signal (LSE) can be generated from two possible clock
sources:
•LSE external crystal/ceramic resonator (see Figure 6)
•LSE user external clock (see Figure 6)
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency of
32.768 kHz. The external clock signal (square, sine or triangle) with a duty cycle of about
50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance
(see Figure 5 and Figure 6).
Figure 5. External clock
1. OSC32_IN and OSC32_OUT pins can be used also as GPIO but, it is recommended not to use them as
both RTC and GPIO pins in the same application.
External crystal/ceramic resonator (LSE crystal)
The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the
advantage of providing a low-power, but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The resonator and the load capacitors have to be connected as close as possible to the
oscillator pins in order to minimize output distortion and start-up stabilization time. The load
capacitance values must be adjusted according to the selected oscillator.
OSC32_OUTOSC32_IN
External source
(Hi-Z)
ai15765
Microcontroller

DocID16139 Rev 5 13/42
AN3029 Clock management
41
Figure 6. Crystal/ceramic resonators
1. To avoid exceeding the maximum value of CL1 and CL2 (15 pF), it is strongly recommended to use a
resonator with a load capacitance CL= 7 pF. To fine-tune the choice, refer to the gmcrit calculation in
AN2867 (Oscillator design guide for ST microcontrollers).
2. OSC32_IN and OSC32_OUT pins can be used also as GPIO, but it is recommended not to use them as
both RTC and GPIO pins in the same application.
3. The value of REXT depends on the crystal characteristics. A 0 Ωresistor works with most oscillators. A
typical value is in the range 5 to 6 RS. To fine-tune the REXT value refer to AN2867 (Oscillator design guide
for ST microcontrollers).
OSC32_OUTOSC32_IN
ai15764
CL1 CL2
Microcontroller
REXT(3)

Reset control AN3029
14/42 DocID16139 Rev 5
5 Reset control
5.1 Reset management overview
The reset pin is a 3.3 V bidirectional I/O. After startup it can be programmed by software to
be used as a general purpose I/O.
Its output buffer driving capability is fixed to IolMIN = 2 mA @ 0.45 V in the 1.8 V to 3.6 V
range which includes a ~45 k pull-up. Output buffer is reduced to the n-channel MOSFET
(NMOS). The receiver includes a glitch filter, whereas the output buffer includes a 20 µs
delay.
There are many reset sources, including:
•External reset through the NRST pin
•Power-on reset (POR) and brown-out reset (BOR): During power-on, the POR keeps
the device under reset until the supply voltage (VDD and VDDx) reach the voltage level
at which level the BOR starts to function. STM8L101xx devices have only a POR.
•Independent watchdog reset (IWDG)
•Window watchdog reset (WWDG), featuring also software reset: only for STM8L05xx,
STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx.
•SWIM reset: An external device connected to the SWIM interface can request the
SWIM block to generate a microcontroller reset.
•Illegal opcode reset: If a code to be executed does not correspond to any opcode or
prebyte value, a reset is generated.
Figure 7 shows a simplified functional I/O reset schematic.
Figure 7. Reset management
RPU
System reset
Filter
100 nF
External
reset circuit
NRST
ai14866d
Illegal op code reset
Swim reset
POR/BOR reset
IWDG/WWDG/software reset
Delay
STM8
VDD_IO
Pulse
generator
(min 20 μs)

DocID16139 Rev 5 15/42
AN3029 Reset control
41
5.1.1 Output characteristics
•A valid pulse on the pin is guaranteed with a ≥20 ns pulse duration on the internal
output buffer.
•After a valid pulse is recognized, a pulse on the pin of at least 20 µs is guaranteed
starting from the falling edge of A.
Figure 8. Output characteristics
5.1.2 Input characteristics
•All pulses with a duration less than 50 ns are filtered
•All train/burst spikes with a ratio of 1/10 must be filtered. This means that a negative
spike of up to 50 ns is always filtered, when a 5 ns interval between spikes occurs (ratio
1/10).
•All pulses with duration more than 300 ns are recognized as valid pulses
Figure 9. Input characteristics
MS32525V1
≥ 20 n
20 μs pulse stretch min
A
Pad
Reset requested
MS32526V1
Pad
System rese
t
>5 ns >5 ns
<50 ns <50 ns <50 ns
300 ns
Valid Reset requestedNegative train of glitch filtered

Reset control AN3029
16/42 DocID16139 Rev 5
5.2 Hardware reset implementation
The STM8L and STM8AL do not require an external reset circuit to power-up correctly. Only
a pull-down capacitor is recommended (see Figure 7). However, charging/discharging the
pull-down capacitor through an internal resistor has a negative influence on the device
power consumption. Therefore, the recommended capacitor value of 100 nF can be
reduced down to 10 nF to limit such power consumption.
The STM8L101xx reset state is released 1 ms after the POR value (1.35 V to 1.65 V) is
reached. At this time, VDD should be in the 1.65 V to 3.6 V range.
For medium density devices and medium+ and high density devices operating from 1.8 V at
power-on: the reset state is released 1 ms after the BOR minimum value (~1.75 V) is
reached.

DocID16139 Rev 5 17/42
AN3029 Recommendations
41
6 Recommendations
6.1 Printed circuit board
For technical reasons, it is best to use a multi-layer PCB with a separate layer dedicated to
the VSS and another layer to the VDD supply. This results in a good decoupling, as well as a
good shielding effect. For many applications, economical requirements prohibit the use of
this type of board. In this case, the most important feature is to ensure a good structure for
the VSS and power supply.
6.2 Component position
A preliminary layout of the PCB must separate the different circuits according to their
electromagnetic interference (EMI) contribution. This reduces cross-coupling on the PCB,
for instance, noisy, high-current circuits, low voltage circuits, and digital components.
6.3 Ground and power supply (VSS, VDD)
The VSS should be distributed individually to every block (noisy, low level sensitive, and
digital) with a single point for gathering all ground returns. Loops must be avoided or have a
minimum surface. The power supply should be implemented close to the ground line to
minimize the surface of the supply loop. This is due to the fact that the supply loop acts as
an antenna, and is therefore the main emitter and receiver of EMI. All component-free
surfaces of the PCB must be filled with additional grounding to create a kind of shield
(especially when using single-layer PCBs).
6.4 Decoupling
The standard decoupler for the external power is a 1 µF pool capacitor. Supplementary 100
nF capacitors must be placed as close as possible to the VSS/VDD pins of the
microcontroller to reduce the area of the current loop.
As a general rule, decoupling all sensitive or noisy signals improves electromagnetic
compatibility (EMC) performances.
There are two types of decouplers:
•Capacitors close to components. Inductive characteristics, which apply to all capacitors
beyond a certain frequency, must be taken into account. If possible, parallel capacitors
with decreasing values (0.1, 0.01,... µF) should be used.
•Inductors. Although often ignored, ferrite beads, for example, are excellent inductors
due to their good dissipation of EMI energy and there is no loss of DC voltage (which is
not the case when simple resistors are used).

Recommendations AN3029
18/42 DocID16139 Rev 5
6.5 Other signals
When designing an application, the following areas should be closely studied to improve
EMC performances:
•Noisy signals (clock)
•Sensitive signals (high impedance)
•Signals for which a temporary disturbance permanently affects operation of the
application, for example, interrupts and handshaking strobe signals (but not LED
commands).
A surrounding VSS trace for such signals increases EMC performances, as does a shorter
length or absence of noisy and sensitive traces (crosstalk effect).
For digital signals, the best possible electrical margin must be reached for the two logical
states. Slow Schmitt triggers are recommended for eliminating parasitic states.
6.6 Unused I/Os and features
Microcontrollers are designed for a variety of applications, where often a particular
application does not use 100 % of the microcontroller resources.
To avoid unnecessary power consumption (especially important for battery powered
applications) and also to improve EMC performance, unused clocks, counters, or I/Os,
should not be left free, I/Os should be forced externally (pull-up or pull-down to the unused
I/O pins), and unused functions should be ‘frozen’ or disabled.
Alternatively, unused I/Os can be programmed as push-pull ‘low’ to keep them at a defined
level without using external components. However in this case, the I/O is not driven during
the power up phase, until the I/O is configured. This can add a little extra power
consumption, and may be undesirable in very power sensitive applications.
6.7 User options
STM8L and STM8AL devices have user option features that can be used for remapping or
enabling/disabling an automatic reset or low speed watchdog. For more details, please refer
to the product datasheets.
6.8 Bootloader
STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices have a
bootloader embedded in a ROM memory. Through this firmware the device memory can be
re-programmed via:
•USART communication interface for medium density devices
•USART1, USART2, USART3, SPI1, and SPI2 communication interfaces for medium+
and high density devices.

DocID16139 Rev 5 19/42
AN3029 Reference design
41
7 Reference design
7.1 Component references
Table 2. Component list
ID Component name Reference Quantity Comments
1 Microcontroller STM8L, STM8AL 1
Refer to the ‘pinouts and pin description’
and ‘package characteristics’ sections of
the STM8L and STM8AL datasheets, to
choose the right package
2 Battery 1.65 V to 3.6 V(1)
1. 1.8 V to 3.6 V for STM8L05xxx.
1 Min 1.8 V when BOR is enabled
3 Capacitor 1 µF n Decoupling capacitor
4 Capacitor 100 nF n Ceramic capacitor (decoupling capacitor)
Components below are optional
5 Capacitor 10 µF 1 Ceramic capacitor (decoupling capacitor)
6 Crystal 1 to 16 MHz 1 -
7 Capacitor 20 to 40 pF 2 Used for crystal
Crystal 32 kHz 1 -
8 Capacitor 5 to 20 pF 2 Used for crystal
Ferrite bead Depends on noise to be filtered
9 SWIM connector 4 pins 1 -

Reference design AN3029
20/42 DocID16139 Rev 5
7.2 Schematics
Figure 10. Reference design
1. If these components are removed, they have to be replaced by a short connection.
2. Optional: if a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and 1 µF) must be
connected. VREF+ is either connected to VDDA or VREF.
3. One 100 nF Ceramic capacitor for each VDDx pin and one single 1 µF Tantalum or Ceramic capacitor.
VDD1
VDDA
VREF+
VSS1/2 ... N
VLCD NRST
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
Biggest package
20pF
1-16MHz
0 Ohm
20pF
41 3 2
32.768kHz
6.8pF
6.8pF
100 μH
BEAD
1uF
1uF
Only if accurate High Speed
Oscillator is needed
1uF OR OR
For noisy
environment
VSS
3.6V-1.8V
(1.65V)
0 Ohm
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CPPTUFSJTVTFEUP
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see note 1
External reset circuit
To power LCD
specifically
ai18711b
(see note 2)
VDD2
VDD3
VDD4
10
0n
F
10
0n
F
10
0n
F
10
0n
F
(see note 3)
10
0n
F
10
0n
F
VREF
1uF
10
0n
F
VDD
VSS
VSS
VDD
VDD
VSS
2.5V<V LCD<3.6V