NXP Semiconductors LPC86 Series Guide

LPC86XHDG
LPC86x Hardware Design Guide
Rev. 0 — 8 May 2023 User guide
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Keywords LPC86x, hardware design, LPC86x power circuit
Abstract This document provides guide for LPC86x hardware design, including power system, clock, pin
status, and PCB layout.

NXP Semiconductors LPC86XHDG
LPC86x Hardware Design Guide
1 Introduction
The LPC86x is introduced to market by NXP. It is an Arm Cortex-M0+ based, low-cost 32-bit MCU supporting up
to 64 kB of flash memory and 8 kB of SRAM.
This document provides guide for LPC86x hardware design, including power system, clock, pin status, and PCB
layout. This guide is expected to help customers to avoid any board bring-up problems.
2 Power system
2.1 Power supply configurations
LPC86x has several power supplies: VDD/VSS, VDDA/VSSA, and VREFP/VREFN. Table 1 describes the
configuration of these power supplies.
Package - Pin number
Pin name Description Operating voltage LQFP64 HVQFN48 HVQFN32
7 29 19
26 — —VDD Supply voltage for the I/O pad,
and core voltage regulator 1.8 V – 3.6 V
39 — —
8 30 33
25 — —VSS Ground GND
40 — —
VDDA[1] Analog supply voltage VDD 52 40 —
VSSA[2] Analog ground GND 53 41 —
VREFP[3] ADC positive reference voltage ≤ VDD 42 32 21
VREFN[2] ADC negative reference voltage GND 41 31 20
Table 1. LPC86x - Power supply configurations
[1] All VDD and VDDA pins must be shortened and connected externally together to a common reference on the PCB. A decoupling capacitor must be used
per each supply pin and a local Bulk capacitor just for the VDD and VDDA domains.
[2] VSSA and VREFN must be shortened to GND at package level.
[3] VREFP must be equal or less than VDD and VDDA.
2.2 Bulk and decoupling capacitors
In application design, to improve design stability, bulk, and decoupling capacitors are normally used. Bulk
capacitance is used to help supply a power rail with instantaneous power that exceeds the ability of the power
supply feedback loop to react to. These capacitors tend to be large as they are not meant to perform any high
frequency power decoupling.
Bypass/decoupling capacitors are needed to allow for local high-frequency interference to instantaneous power
requirements of a device.
Figure 1 to Figure 3 provide circuit design references for applying Bulk and decoupling capacitors on different
package of LPC86x.
•Figure 1 is for LPC86x LQFP64 package.
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Figure 1. Bulk and decoupling capacitors for LPC86x LQFP64
•Figure 2 is for LPC86x HVQFN48 package.
Figure 2. Bulk and decoupling capacitors for LPC86x HVQFN48
•Figure 3 is for LPC86x HVQFN32 package.
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LPC86x Hardware Design Guide
Figure 3. Bulk and decoupling capacitors for LPC86x HVQFN32
2.3 Power measurement
For LPC86x chip power consumption measurement, the measurement circuits is as shown in Figure 4. Only the
current into LPC86x VDD should be measured. P1 is designed for the measurement of LPC86x total current
here using multi-meter's voltage mode, by measuring the voltage on R24, then calculate the current by dividing
by the resistance value of R24. JP2 is designed for the measurement of LPC86x total current here using multi-
meter's current mode, by removing R51. The user can choose either of these two methods to measure the
LPC86x chip power consumption. The default method is using P1.
Figure 4. Power consumption measurement for LPC86x
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2.4 Board design for VREFP and VREFN
To improve ADC conversion accuracy, ADC module provide VREFP and VREFN inputs as accurate external
reference voltage.
For best performance, normally select VREFP and VREFN at the same voltage levels as VDD and VSS.
When selecting VREFP and VREFN different from VDD and VSS, ensure that the voltage midpoints are the
same (required by design specification):
(1)
For LPC86x ADC external reference voltage board connection design, see VREFP/VREFN design circuit shown
in Figure 5.
P2 is used as VREFP/VREFN select.
•When P2 is not installed, VREFP connects to 3.3 V and VREFN connects to GND.
•When P2 is installed and R53 and R54 are changed to B side, VREFP connects to P2-1 external V+ and
VREFN connects to P2-3 external V-.
Figure 5. Board design for VREFP/VREFN
3 Clock circuit
LPC86x provides the interface for a crystal or an external clock to control the internal clock generator circuit.
XTALIN is the input to the crystal oscillator amplifier. XTALOUT is the output of the crystal oscillator amplifier.
XTALIN and XTALOUT pins require pins with special characteristics and cannot be moved to other physical
pins. These functions are mapped to a fixed port pin in Switch Matrix. XTALIN and XTALOUT function is
associated with 10, 11 bits in the PINENABLE0 register.
Pin number
Pin name Description LQFP64 HVQFN48 HVQFN32
XTALIN
Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed
1.95 V in slave mode
34 26 18
XTALOUT Output from the oscillator circuit 33 25 17
Table 2. XTALIN and XTALOUT pins
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LPC86x Hardware Design Guide
3.1 XTAL oscillator mode
In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2 must be connected
externally to XTALIN and XTALOUT, as shown in Figure 6.
Figure 6. XTAL oscillator operation circuit
In user application design, when user selected the proper crystal, the external load capacitor CX1 and CX2
values can also be generally determined by the following expression:
(2)
Where:
•CL: Crystal load capacitance
•CPad: Pad capacitance of the XTALIN and XTALOUT pins (~3 pF).
•CParasitic: Parasitic or stray capacitance of external circuit.
Although CParasitic can be ignored in general, the actual board layout and placement of external components
influences the optimal values of external load capacitors. Therefore, it is recommended to fine-tune the values
of external load capacitors on actual hardware board to get the accurate clock frequency.
3.2 Slave mode (External clock input mode)
In slave mode, the input clock signal should be coupled with a capacitor of 100 pF, as shown in Figure 7, with
an amplitude between 200 mV (RMS) and 1000 mV (RMS). It corresponds to a square wave signal with a signal
swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates
the input voltage by a factor Ci/(Ci + Cg).
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LPC86x Hardware Design Guide
Figure 7. Slave mode operation of the on-chip oscillator
4 I3C circuit
LPC86x provides the MIPI Alliance Improved Inter-Integrated Circuit (MIPI I3C). It brings major improvements
in use and power over I2C and provides an alternative to SPI for mid-speed applications with bus capable of 12
MHz clock speeds.
4.1 Pin description
I3C comes with three pins for the function:
•For clock
•For data
•For pullup resistor control
The three pins all are movable functions pins and can be assigned to any GPIO pins through Switch Matrix.
Pin name Description Type Pin assignment
I3C0_SCL Clock for I3C master or slave function I/O Movable functions pin
I3C0_SDA Data for I3C master or slave function I/O Movable functions pin
I3C0_PUR Pullup resistor control for I3C master function O Movable functions pin
Table 3. I3C pins description
4.2 Design I3C circuit compatible with I2C
The I3C circuit design requires to be compatible with I2C. Figure 8 shows an I3C circuit reference design.
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LPC86x Hardware Design Guide
This design has the default function of I3C connection. When the I2C connection is required, remove R56 and
install R58 and R59.
Figure 8. A sample design for I3C circuit compatible with I2C
5 Pin state and unused pins termination
The unused pins must be connected externally to get a stable condition and configured correctly by software to
minimize the overall power consumption of the part. Unused pins with GPIO function should be configured as
outputs set to LOW with their internal pullup disabled.
Table 4 describes the LPC86x pins state and terminations for the unused pins.
Pin name Reset state Recommended termination of unused pins
RESET Tri-status
Without internal pullup
Can be left unconnected if the application does not use it. (In this
case, during Power On Reset, the chip uses internal reset signal)
GPIO Tri-status
Without internal pullup
Can be left unconnected if driven LOW and configured as GPIO
output with pull-up disabled by software
XTALIN — Connect to ground. When grounded, the main oscillator is disabled
XTALOUT — Can be left unconnected
VDDA — Tie to VDD
VSSA — Tie to VSS
VREFP — Tie to VDD
VREFN — Tie to VSS
Table 4. LPC86x pins state and terminations for the unused pins
For ISP select pin (PIO0_12)，because the reset state is Tri-status without internal pullup, an external pullup
resistor is needed, otherwise, after reset, the LPC86x enters the ISP state as default.
For WAKEUP pin (PIO0_4), if the LPC86x must wake up from deep power-down mode via the WAKEUP pin,
do not assign any movable function to this pin and must be externally pulled HIGH before entering deep power-
down mode. A LOW-going pulse as short as 50 ns causes the chip to exit deep power-down mode and wakes
up the part. The WAKEUP pin can be left unconnected or be used as a GPIO or for any movable function if an
external WAKEUP function is not needed.
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6 General PCB layout guide
6.1 PCB layout suggestions for crystal oscillator circuit
The crystal oscillator is an analog circuit and must be designed carefully according to the analog-board layout
rules:
•Signal traces to the XTAL/EXTAL pins, the crystal and the external capacitors must be as short as possible,
these traces pins should only be connected to required oscillator components and must not be connected to
any other devices or components. The connection between the MCU and the external oscillator should not
have vias on the trace.
•Do not lay out other signal lines under crystal unit for multi-layered PCB. The crystal oscillator is sensitive to
stray capacitance and noise from other signals. It should be placed away from high-frequency devices and
traces in order to avoid the capacitive coupling between the XTAL and EXTAL pins and their PCB traces.
•Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input
and output pins of the chip. Ensure that the load capacitors CXTAL, CEXTAL, have a common ground plane
(GROUND plane first layer).
•Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the
parasitics as small as possible.
•Lay out the ground pattern under crystal unit (GROUND second layer).
Figure 9 shows the recommended placement and routing for the oscillator layout.
Figure 9. Recommended placement and routing for the crystal oscillator PCB layout
6.2 Motor control pin arrangement in board design
LPC86x provides Flextime with PWM channels which can be designed for motor control signals from AT to
CB. See Table 5. There are three selections for PWM channel assigned to different pins. User can design with
Switch Matrix to choose different selection for FTMx_CHy.
Function name Type Selection 0 Selection 1 Selection 2 Selection 3
FTM0_EXTCLK I P0_24 P0_30 — Not connected
FTM0_CH0 I/O P0_17 P1_1 — Not connected
FTM0_CH1 I/O P0_18 P1_2 P0_16 Not connected
Table 5. Flextime PWM channels pin assignment
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Function name Type Selection 0 Selection 1 Selection 2 Selection 3
FTM0_CH2 I/O P0_19 P1_3 P1_2 Not connected
FTM0_CH3 I/O P0_20 P1_4 P0_27 Not connected
FTM0_CH4 I/O P0_21 P1_5 P0_25 Not connected
FTM0_CH5 I/O P0_22 P1_6 P0_24 Not connected
FTM0_FAULT0 I P0_10 P1_7 P0_28 Not connected
FTM0_FAULT1 I P0_11 P1_12 P1_3 Not connected
FTM0_FAULT2 I P0_13 P1_13 — Not connected
FTM0_FAULT3 I P0_23 P1_14 — Not connected
FTM1_EXTCLK I P0_25 P0_29 — Not connected
FTM1_CH0 I/O P0_15 P1_8 — Not connected
FTM1_CH1 I/O P0_16 P1_9 — Not connected
FTM1_CH2 I/O P0_26 P0_31 — Not connected
FTM1_CH3 I/O P0_27 P1_0 — Not connected
FTM1_QD_PHA I P0_24 P0_29 — Not connected
FTM1_QD_PHB I P0_25 P0_30 — Not connected
Table 5. Flextime PWM channels pin assignment...continued
Motor control design requires that the PWM channels must be consistent, AT~CB correspond to PWM channels
0~5 or 5~0 respectively and prefer to 0~5.
During PCB layout, designer should consider arranging the PWM channels in same order with the AT~CB pins,
this way can avoid across wires on the board which results more difficulties for PCB routing.
Motor control AT-CB Flextimer PWM channels
PWM_AT FTM0_CH0
PWM_AB FTM0_CH1
PWM_BT FTM0_CH2
PWM_BB FTM0_CH3
PWM_CT FTM0_CH4
PWM_CB FTM0_CH5
Table 6. PCB layout pins sequence for PWM channels and AT~CB pins
6.3 EMI/EMC and ESD considerations for layout
In application design, the main purposes for EMC/EMI consideration are:
•The radiated and conducted EMI from the board should be lower than the allowed levels by the standards you
are following (EMI).
•The ability of the board to operate successfully counteracting the radiated and conducted electromagnetic
energy from other systems around it (EMC).
Every board or system is different as far as EMI/EMC and ESD issues are concerned, requiring its own solution.
However, the common guides to reduce an unwanted generation of electromagnetic energy are as shown
below:
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