Sundance Spas SMT370v2 User manual

SMT370v2
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

Version 1.0 Page 2 of 44 SMT370v2 User Manual
Revision History
Date Comments Engineer Version
14/02/03 First release PSR 1.0
08/03/03 Details added about registers and external
signals – figure references – examples.
PSR 1.1
31/03/03
FPGA Firmware changed – ADC/DAC Triggers
and ADC decimators added – SHBA and B 16
or 32 bits.
PSR 1.2

Version 1.0 Page 3 of 44 SMT370v2 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Table of figures........................................................................................................... 4
Contacting Sundance. ................................................................................................ 5
Notes. ......................................................................................................................... 5
Precautions................................................................................................................. 5
Block Diagram. ........................................................................................................... 7
Architecture Description. ............................................................................................ 8
Virtex FPGA. ........................................................................................................... 9
Communication Ports (CommPorts). ...................................................................... 9
SHB. ..................................................................................................................... 10
Memory................................................................................................................. 10
Clock management. .............................................................................................. 11
TTL I/Os. ............................................................................................................... 11
External triggering................................................................................................. 11
ADCs and DAC. .................................................................................................... 11
LEDs. .................................................................................................................... 12
Sundance Standards. ............................................................................................... 12
Communication Ports............................................................................................ 12
Sundance High-speed Bus. .................................................................................. 13
SMT370 communication links. .............................................................................. 13
ADC Performance. ................................................................................................... 14
DAC Performance. ................................................................................................... 16
SHB pinout. .............................................................................................................. 18
FPGA Pinout............................................................................................................. 19
At power-up and on reset. ........................................................................................ 23
Connector position.................................................................................................... 24
Operating conditions................................................................................................. 25
Safety.................................................................................................................... 25
EMC...................................................................................................................... 25
General Requirements.......................................................................................... 25

Version 1.0 Page 4 of 44 SMT370v2 User Manual
Power Consumption.............................................................................................. 25
Register settings....................................................................................................... 26
Register 0x0 – DAC Register (report to AD9777 datasheet for more details). ...... 26
Register 0x1 – DAC register (report to AD9777 datasheet for more details)......... 27
Register 0x2 – DAC register (report to AD9777 datasheet for more details)......... 28
Register 0x3 – DAC register (report to AD9777 datasheet for more details)......... 29
Register 0x4 – DAC register (report to AD9777 datasheet for more details)......... 30
Register 0x5 – Clock management. ...................................................................... 31
Register 0x6 – Channel selection – Triggers – Decimator. ................................... 33
Register 0x7 – DAC control – Pattern generator................................................... 34
Register 0xE – DAC Register Read back.............................................................. 36
Register 0xF – Serial Interfaces load. ................................................................... 37
Example code for 3L Diamond – Configuring registers/Data capture/Direct2DAC. .. 38
Example code for 3L Diamond – Configuring registers/Data capture/Pattern
Generator. ................................................................................................................ 41
Table of figures.
Figure 1 - Block Diagram............................................................................................ 7
Figure 2 - CommPort interface data path.................................................................. 13
Figure 3 - SHB interface structure. ........................................................................... 13
Figure 4 - ADC Performance. ................................................................................... 14
Figure 5 - FFT ADC Channel - On-board clock. ....................................................... 15
Figure 6 - DAC Performance. ................................................................................... 16
Figure 7 - FFT DAC Channel.................................................................................... 17
Figure 8 - SHB Pinout............................................................................................... 18
Figure 9 - Connector Location. ................................................................................. 24
Figure 10 - Clock Routing......................................................................................... 32

Version 1.0 Page 5 of 44 SMT370v2 User Manual
Contacting Sundance.
You can contact Sundance for additional information by sending email to
[email protected].
Notes.
- SMT370 denotes in this document SMT370v2.
- SHB stands for Sundance High-speed Bus.
- CommPort denotes an 8-bit communication port following the TI C4x
standards.
Precautions
In order to guarantee that the SMT370 functions correctly and to protect the module
from damage, the following precautions should be taken:
- The SMT370 is a static sensitive product and should be handled
accordingly. Always place the module in a static protective bag during
storage and transition.
- When operated in a closed environment make sure that the heat
generated by the system is extracted e.g. a fan extracting heat or blowing
cool air.

Version 1.0 Page 6 of 44 SMT370v2 User Manual
Outline description.
The SMT370v2 is a dual high-speed ADC/DAC module offering the following
features:
- Two 14-bit ADCs (AD6645-105) sampling at up to 105MHz,
- Dual 16-bit TxDAC (AD9777) sampling at up to 400MHz (interpolation),
- Single width module,
- Two Sundance High-speed Bus (SHB) connectors,
- Two 20 MegaByte/s communication ports,
- Low-jitter on-board system clock,
- Xilinx Virtex-II FPGA,
- 50-Ohm terminated analogue inputs and outputs, external triggers and clocks
via MMBX (Huber and Suhner) connectors,
- User defined pins for external connections,
- Compatible with a wide range of Sundance SHB modules,
- TIM standard compatible,
- Default FPGA firmware implementing all the functions described along this
documentation.

Version 1.0 Page 7 of 44 SMT370v2 User Manual
Block Diagram.
The following diagram shows the architecture of the SMT370v2.
Board Reset
2x Comm-Port/SDL
24 I/O pins
106 I/O pins; 44-bit data
Xilinx FPGA
Virtex-II, FG456
XC2V1000-6
324 I/O Pins
1.5V Core
3.3V I/O
One bank of 1Mx32 bits of
NtSRAM - 166 MHz
J2 Bottom Primary TIM
Connector
J1 Top Primary TIM
Connector
2x CommPorts/SDLs 0& 3
#1
120 I/O pins
AC or DC
coupling*
2xAD6645 ADCs
14-bit @ 105MSPS
52-pin LQFP
30 I/O pins; 28-bit data; ctl
1x AD9777 DAC
16-bit @ 400MSPS
80-pin TQFP
44 I/O pins; 16-bit data; ctl
#4#3
RF
transformer
#2
Clock feedback
Trig
1
Trig
2
6-pin JTAG
header
On-board Oscillator
50 MHz
4 LEDs or
4 LVTTL I/O pins
FPGA PROM
XC18V04
Clock
Multiplexer
Clock
parameters
3 Power
supply
LEDs
‘FPGA configured’
LED
Clock feedback
Clk
1
Filter
Filter
2xClock
synthesizers
Clk
2
Clock selection
2Sundance High-speed
Bus connector: 2 x 60 bits
AC or DC
coupling*
RF
transformer
JTAG chain
* Option to the board
Figure 1 - Block Diagram.
Connections to the outside world are greyed out.
Main parts of the board are described in the next part of this document.

Version 1.0 Page 8 of 44 SMT370v2 User Manual
Architecture Description.
The module consists of a Xilinx Virtex-II FPGA, two Analog Devices (14-bit monolithic
sampling Analog-to-Digital converters) AD6645 and one Analog Devices AD9777
(Dual TxDAC+ Digital-to-Analog converter).
The AD6645 is a 14-bit monolithic sampling analog-to-digital converter. The chip
provides CMOS-compatible digital outputs. It is the Analog Devices’ fourth generation
of wideband ADCs. The AD6645 maintains outstanding AC performance up to input
frequencies of 200 MHz, which makes it suitable for multi-carrier 3G applications.
The AD6645 is able to sample from 30 up to 105 MHz. Nevertheless, it is possible to
reduce that rate by performing decimation on the data flow.
The AD9777 dual interpolating (2x/4x/8x) DAC consists of two data channels that can
be operated independently or coupled to form a complex modulator in an image
reject transmit architecture. This programmable converter has a resolution of 16 bits.
It features a Serial Port Interface (SPI) for programming. The chip features a
selectable 2x/4x/8x interpolation filter, an Fs/2, Fs/4 or Fs/8 digital quadrature
modulation with image rejection, a direct IF mode, a programmable channel gain and
offset control, a programmable internal clock divider, a straight binary to two’s
complement data interface and a single port or dual data interface.
Parallel busses connect both ADCs and the DAC to the FPGA, which is responsible
for transferring samples from/to the converters. An on-board frequency synthesizer
generates differential encode lines (sampling clocks) to feed the converters; a
connector for external clocks is also available. Each input analogue signal to the
ADCs goes through an extra stage, which can be an opamp (DC coupling) or an RF
transformer (AC coupling). The option must be defined when ordering the SMT370.
When it comes to the DAC, its outputs can only be set as AC coupled (output RF
transformer). Both ADCs can be coupled together. i.e. they have the same sampling
clock or have two separate clocks, one external and one coming from the on-board
clock synthesizer.
The Xilinx FPGA Virtex-II is configured via a 6-pin JTAG header or from the on-board
Xilinx PROM (XC18V04) at startup. The default configuration mode is from a PROM,
which contains the standard modes of operation (as described in this document). An
on-board LED indicates that the FPGA is configured. Both devices, FPGA and
PROM are in the JTAG chain.
The SMT370 is also populated with some NtSRAM memory. It is 32-bit wide and to
store two 16-bit samples at the same address at up 160 MHz. Its size is 1
Megawords of 32-bits. The FPGA is implemented with an NtSRAM interface to
write/read to/from it. Memory accesses are made via the control register. A ‘pattern
generator’ function is available to store a pattern (or period or frame) into the
memory, read back continuously and send samples out to the DAC. This
configuration allows to board to work as a periodic generator in stand-alone mode.

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Two Communication links (CommPorts) following the Texas Instrument C4x standard
are connected to the FPGA and will be used to receive control words or for other
purpose. They can achieve transfers at up to 20Mbytes/s.
Two full SHB connectors (60-pin) are accessible from the FPGA. The first connector
(SHBA) is set as output only and is dedicated for sending out samples coming from
the ADC. The second connector (SHBB) is set as input only to receive samples,
which are redirected to the DAC. Please refer to the SHB specifications for more
details about ways connectors can be configured. Both SHB can be implemented as
either two 16-bit interfaces or a single 32-bit interface. In the case of a 32-bit
interface, both ADCs must receive the same sampling clock signal.
Four LEDs are driven by the FPGA. Four LVTTL I/Os for general purpose are also
available. No clamping diodes to 3.3 Volts and ground are available on the board to
avoid damaging pads on the FPGA. It is therefore to the customer to male sure the
signals connected to these I/Os are LVTTL and don’t show any overshoots.
External Clock, trigger and analogue input signals are all single-ended. External
connections to the board are all 50-Ohm terminated. External triggers have clamping
diodes to 3.3V and to Ground to avoid damaging the FPGA they are connected to.
A global reset signal is mapped to the FPGA from the top TIM connector to reset the
FPGA and reload the FPGA
Virtex FPGA.
The SMT370 is populated with a Xilinx Virtex FPGA (XC2V1000-6FG456). This
device controls major functions on the module, like CommPorts and SHB
communications, data flows to and from the converters, memory and clock
generation.
This FPGA needs being configured after power-up and after a module reset. This
operation is possible thanks to the on-board Xilinx PROM. This operation can be
done automatically when jumper J8 (Figure 9 - Connector Location.)is fitted. If it is
not fitted, no configuration is loaded into the FPGA and allows therefore the user to
program the FPGA via JTAG with no possible conflict.
Ten control registers are implemented into this FPGA to set up converters, their data
format, clock synthesizers, CommPort, SHB and memory transfers. Some more
details are given in the next parts of this document.
The FPGA is serially programmed using the dedicated pins. The PROM is originally
programmed with a default bit stream, which implements all features mentioned in
this document.
Communication Ports (CommPorts).
The SMT370 provides 2 CommPorts: 0 and 3. The default bit stream provided
implements CommPort 3 (Input at reset) to load control registers. A physical
connection to a CommPort 0, 1 or 2 (Output at reset) is therefore necessary, to an

Version 1.0 Page 10 of 44 SMT370v2 User Manual
SMT365 for instance. Please report to the part dealing with CommPorts in this
document for more details.
SHB.
The SMT370 provides 2 full SHB (Sundance High-speed Bus) connectors, labelled
SHBA (J3) and SHBB (J4) – see Figure 9 - Connector Location..
SHBA is set as transmitter only to transfer data coming from the Analogue-to-Digital
Converters to an external SHB module, for instance SMT365, SMT365E or SMT374.
SHBB is set as a receiver only and is dedicated to receive data for the Digital-to-
Analogue converter. Transfers at up to 100 MHz are supported on these two SHB
connectors.
SHBA – ADCs.
The FPGA routes the data lines coming from the ADCs to SHBA. Data lines go
through 7 latch stages inside the FPGA, which means that it takes 7 sampling clock
cycles for a sample to go from the ADC to SHBA. The board offers to possibility to
output data in either two’s complement or binary format. The option of outputting a
counter is also available for system testing purpose.
As the SMT370 is populated with two ADCS, two data stream are theoretically
available on SHBA. Each of them can be synchronised to either an external sampling
clock or an on-board clock. In the FPGA, each data stream goes through a
Decimator, which value (0 to 31) can be set in a control register. Both decimators are
independent. If both decimators are set with the same values and if the sampling
clocks (for Channel A and Channel B) are the same, i.e. both ADCs are using either
the external or the on-board clock, both data streams are synchronised with each
other and therefore the two 16-bit data streams can be considered as a single 32-bit
data stream.
It is possible to control (start/stop) the data flow by the way of an external trigger, for
which the active level (high or low) can be set in a control register. It is recommended
to have external trigger signal synchronised to the sampling clock. This external
trigger also goes thought 7 latch stages.
SHBB – DAC.
Data received from SHBB are samples routed to the DAC. Data from both SHBB
channels are first stored into a FIFO. As they are not necessarily synchronised, the
two FIFOs are read out at the same time as soon as there is a least one data in each
FIFO. This is what happens when using two independent 16-bit interfaces. To avoid
synchronisation problems, SHBB can be configured as a single 32-bit interface.
Memory.
The SMT370 is populated with 32Mbits of ZBTRAM (32 bits x 1Meg). It is connected
to the FPGA, which controls read and write operations. The default FPGA bit stream
implements a pattern generator which consists in storing a pattern into the memory,

Version 1.0 Page 11 of 44 SMT370v2 User Manual
reading it back continuously and sending data out to the DAC. This generator is
controlled via bits in the control registers. It can be loaded, started and stopped by
setting bits. For more details, see further in the documentation, the part dealing with
control registers.
Clock management.
The SMT370 has two identical on-board low-jitter clock synthesizers, one for the
ADCs and one for the DAC. Both have a Serial Port Interface. The FPGA is
responsible for setting them to the correct values loaded into a control register. A
wide range of frequencies can be set this way. They are low-jitter devices.
Clock multiplexers are also available on the board to route the appropriate clock
signal (from external or on-board source) to the converters. It is usual to have both
ADCs fed with the same sampling clock but it is possible to have an ADC receiving
the external clock and the second one receiving the on-board clock. In this particular
case, two 16-bit interfaces are necessary to transfer samples to an external TIM. The
DAC is fed either with an on-board/DAC or external clock coming from connector
J14. The clock selection is made via the control register.
TTL I/Os.
Four TTL I/Os (J6 – see Figure 9 - Connector Location.) are connected directly to the
FPGA. They support LVTTL signals. It is recommended to make sure the lines
connected to these pins are LVTTL compatible in order not to damage the FPGA
pads, as lines are not clamped.
External triggering.
Two external trigger connectors (J15 and J16 – see Figure 9 - Connector Location.)
are available on the board to trigger converters from an external source. The
selection is made via a control register, where channel selection can also be set.
Triggering consists in enabling or stopping the converters (ADCs and/or DAC). This
is available and accurate as long as the triggering signals are synchronised on the
sampling clock. Triggering signals can be set as active high or low in via the control
register.
Each trigger input is clamped to 3.3 and Ground to avoid damaging the FPGA I/Os.
This is achieved by using single diodes (BAV99). These diodes can support as
maximum, 200mA of forward current and 70 Volts of reverse voltage. It is to the
customer to consider this when building a system using an SMT370.
ADCs and DAC.
The SMT370 is populated with two AD6645s and one AD9777. For mode details
about these converters (inner characteristics), please refer to the manufacturer
(Analog Devices) datasheets.
Data and control lines of the converters are all connected to the.

Version 1.0 Page 12 of 44 SMT370v2 User Manual
LEDs.
Seven LEDs (Figure 9 - Connector Location.)are available on the board. Four
(denoted 1, 2, 3 and 4 on the PCB – top left) of them, green, are driven by the FPGA.
In the default bitstream, they indicate what follows:
1 -> Flashing under the ADC sampling clock (it can be useful to check that the
LED is flashing when using an external sampling clock signal),
2 -> Flashing under the DAC sampling clock,
3 -> Direct To DAC mode selected when ON,
4 -> ON when a data is being read out of the DAC FIFO.
Two green LEDs, located at the bottom left and right of the board indicate the status
of the power supplies. Both should be on when the board is under power.
A red LED located on the top right of the board indicated when the FPGA is not
programme. In normal operation, i.e. J8 fitted (Figure 9 - Connector Location.), it
flashes once at power-up and after a module reset.
Sundance Standards.
Communication Ports.
CommPorts (Communication ports) links follow Texas Instrument C4x standard. They
are 8-bit parallel inter-processor ports of the ‘C4x processors.
The CommPorts drive at 3.3v signal levels.
The FPGA can implement up to two FIFO buffered CommPort interfaces fully
compliant with the TIM standard. They are guaranteed for a transfer rate of 20MB/s.
The FIFOs are useful to maintain a maximum bandwidth and to enable parallel
transfers.
Therefore, as an example, each CommPort can be associated with two 15x32-bit
unidirectional FIFOs implemented into the FPGA; one for input and one for output.
An additional one-word buffer makes them appear as 16x32-bit FIFOs.
DATA D[0..31] FIFO
16 x 32 x 2
D[0..7]
Control Logic and Status
STRB RDY REQ ACK
Port x

Version 1.0 Page 13 of 44 SMT370v2 User Manual
Figure 2 - CommPort interface data path.
Sundance High-speed Bus.
Both SHB buses are identical and 60-bit wide.
SHBs are parallel communication links for synchronous transmissions. Each SHB
can be divided into two independent 8-bit buses. Each 8-bit bus includes a clock and
three control signals: write enable, request and acknowledge. An SHB bus can also
be divided into two 16-bit buses and one 8-bit bus.
Here is the architecture of the SHB interface implemented into the FPGA:
D[0..31] FIFO
256 x 32 x 2
D[0..15]
Control Logic and Status
CLK WEN REQ ACK
SHB A
DATA
Figure 3 - SHB interface structure.
SMT370 communication links.
The SMT370 provides 2 CommPort links. They are given the numbers 0 and 3. The
default firmware provided with the board implements CommPort3 as a control
register communication port, which means that every control register word has to be
sent to CommPort3 on the SMT370 to be received.
The board also connects two full SHB connectors (60 bits) to the FPGA. The FPGA
implements two 16-bit (or one 32-bit) unidirectional interfaces per SHB connector:
output only for SHBA – used to send out samples coming from both ADCs - and input
only for SHBB – used to suck samples in to the DAC.

Version 1.0 Page 14 of 44 SMT370v2 User Manual
ADC Performance.
Description Specification
Analogue inputs
Maximum voltage 1.1 Volts peak-to-peak (AC coupling)
2.2 Volts peak-to-peak (DC coupling)
Impedance 50 Ω
Bandwidth 0-250 MHz - (No anti-aliasing filter)
External Clock
Minimum voltage 0.2 Volt peak to peak minimum
Impedance 50 Ω
Frequency range 30-105 MHz – low jitter
External Trigger
Frequency Range 30-105 MHz
Signal format LVTTL (3.3 Volts) format – connected to
3.3V FPGA – Clamp diodes to 3.3V and
Ground.
Characteristics
Resolution 14 bits
Output format Binary or two’s complement
Maximum sampling frequency 105 MHz
SFDR Up to 81dB.
SNR Up to 60dB.
Figure 4 - ADC Performance.

Version 1.0 Page 15 of 44 SMT370v2 User Manual
The following graphs gives the average FFT of sixteen 16K-FFTs processed after
capturing data from Channel B – The on-board sampling frequency set to 100 MHz –
A 20MHz sine signal is fed to the board. The test has been performed without any
input filter (which explains the second peak due to harmonics) at all and with a 35dBc
harmonic performance signal generator.
Figure 5 - FFT ADC Channel - On-board clock.
Similar results are obtained when using an external clock. It is recommended to use
a low-jitter clock and a filter on the ADC inputs. They indeed have a large input
bandwidth and therefore allow a high level of harmonics in.

Version 1.0 Page 16 of 44 SMT370v2 User Manual
DAC Performance.
Description Specification
Analogue outputs
Maximum voltage 1 Volt peak-to-peak
Impedance 50 Ω
Bandwidth
External Clock
Minimum voltage 0.2 Volt peak to peak minimum
Impedance 50 Ω
Frequency range 20-160 MHz – low jitter
External Trigger
Frequency Range 30-160 MHz
Signal format LVTTL (3.3 Volts) format – connected to
3.3V FPGA
Characteristics
Resolution 16 bits
Output format Two’s complement or Binary
Maximum sampling frequency 160 MHz – 400 MHz by interpolation
SFDR Up to 50 dB.
SNR
Figure 6 - DAC Performance.

Version 1.0 Page 17 of 44 SMT370v2 User Manual
The following capture shows a 5MHz signal generated by the DAC under an on-
board sampling clock of 160MHz. Note that no output filter was used during the
capture.
Figure 7 - FFT DAC Channel.

Version 1.0 Page 18 of 44 SMT370v2 User Manual
SHB pinout.
Pin Signal Pin Signal Pin Signal
1 CLK0 21 D19 41 D39
2 D0 22 D20/ WEN1 42 D40
3 D1 23 D21/ REQ1 43 D41
4 D2 24 D22/ ACK1 44 D42
5 D3 25 D23/ CLK2 45 D43
6 D4 26 D24 46 D44/ WEN3
7 D5 27 D25 47 D45 REQ23
8 D6 28 D26 48 D46/ ACQ3
9 D7 29 D27 49 D47/ CLK3
10 D8/ WEN0 30 D28 50 D48
11 D9/ REQ0 31 D29 51 D49
12 D10/ ACK0 32 D30 52 D50
13 D11/CLK1 33 D31 53 D51
14 D12 34 D32/WEN2 54 D52
15 D13 35 D33/REQ2 55 D53
16 D14 36 D34/ ACK2 56 D54
17 D15 37 D35/ CLK3 57 D55
18 D16 38 D36 58 D56/ WEN4
19 D17 39 D37 59 D57/ REQ4
20 D18 40 D38 60 D58/ ACK4
Figure 8 - SHB Pinout.
32-bit Interface
16-bit interface
This standard is implemented using SAMTEC QSTRIP 0.50mm Hi-speed connectors.
To improve electrical performances, a ground plane is embedded in each QSTRIP
connector.
For long distances micro-coax ribbon cable is used to connect 2 QSTRIP connectors.
An SHB interface can be 8,16 or 32-bit wide.

Version 1.0 Page 19 of 44 SMT370v2 User Manual
The default FPGA firmware implements 2 16-bit interfaces.
FPGA Pinout.
###########################################
###
# #
# Constraint File Virtex II for SMT370
#
#
#
#Author:Philippe ROBERT
#
NET "ADCA_DATA<2>" LOC = "AA7" ;
#$Date:23.07.2002
#
#$Version:1.0-Original draft
#
NET "ADCA_DATA<5>" LOC = "Y8" ;
#$Date:09.09.2002
#
#$Version:1.1-CP1 removed+Clock synth.
changed#
#$Date:23.07.2002
#
#$Version:1.0 generated with FloorPlanner
#
#$Version:1.1 generated with FloorPlanner
#
#$Version:1.2 IIOFs added on V11, W12 and
C11# #Version 1.3 ADCA and ADCB data lines
swapped #
#been put back in the right order
#
NET "ADCB_DATA<1>" LOC = "AA11" ;
# (c) Sundance Multiprocessor Technology
#
###########################################
########
CONFIG PART=XC2V1000-FG456-6 ;
# Start of Constraints extracted by
Floorplanner from the Design
NET "FREQ_MASTER_RESET" LOC="C16";
NET "FREQ_CLK_SEL_ADCs<0>" LOC = "D21" ;
NET "FREQ_CLK_SEL_ADCs<1>" LOC = "F18" ;
NET "FREQ_CLK_SEL_DAC<0>" LOC = "E16" ;
NET "FREQ_CLK_SEL_DAC<1>" LOC = "E17" ;
NET "FREQ_CLK_SEL<0>" LOC = "D21" ;
NET "FREQ_nP_LOAD_ADCs" LOC = "B18" ;
NET "FREQ_nP_LOAD_DAC" LOC = "D17" ;
NET "FREQ_S_CLOCK_ADCs" LOC = "A19" ;
NET "FREQ_S_CLOCK_DAC" LOC = "A17" ;
NET "FREQ_S_DATA_ADCs" LOC = "B19" ;
NET "FREQ_S_DATA_DAC" LOC = "B17" ;
NET "FREQ_S_LOAD_ADCs" LOC = "A18" ;
NET "FREQ_S_LOAD_DAC" LOC = "C17" ;
NET "ADCA_DATA<0>" LOC = "W9" ;
NET "ADCA_DATA<1>" LOC = "AB9" ;
NET "ADCA_DATA<3>" LOC = "U9" ;
NET "ADCA_DATA<4>" LOC = "V8" ;
NET "ADCA_DATA<6>" LOC = "AA6" ;
NET "ADCA_DATA<7>" LOC = "Y7" ;
NET "ADCA_DATA<8>" LOC = "W7" ;
NET "ADCA_DATA<9>" LOC = "AB7" ;
NET "ADCA_DATA<10>" LOC = "AA5" ;
NET "ADCA_DATA<11>" LOC = "Y6" ;
NET "ADCA_DATA<12>" LOC = "W6" ;
NET "ADCA_DATA<13>" LOC = "AB6" ;
NET "ADCA_OVR" LOC = "W8" ;
NET "ADCA_RDY" LOC = "V7" ;
NET "ADCB_DATA<0>" LOC = "U10" ;
NET "ADCB_DATA<2>" LOC = "V6" ;
NET "ADCB_DATA<3>" LOC = "AB5" ;
NET "ADCB_DATA<4>" LOC = "V9" ;
NET "ADCB_DATA<5>" LOC = "AB10" ;
NET "ADCB_DATA<6>" LOC = "AA10" ;
NET "ADCB_DATA<7>" LOC = "U11" ;
NET "ADCB_DATA<8>" LOC = "AA9" ;
NET "ADCB_DATA<9>" LOC = "Y10" ;
NET "ADCB_DATA<10>" LOC = "W10" ;
NET "ADCB_DATA<11>" LOC = "V10" ;
NET "ADCB_DATA<12>" LOC = "AA8" ;
NET "ADCB_DATA<13>" LOC = "Y9" ;
NET "ADCB_OVR" LOC = "Y11" ;
NET "ADCB_RDY" LOC = "AB8" ;
NET "IIOF_1" LOC = "W12" ;
NET "IIOF_2" LOC = "C11" ;
NET "ADCB_RDY_GCLK" LOC = "Y12" ;

Version 1.0 Page 20 of 44 SMT370v2 User Manual
NET "ADC_TRIG" LOC = "T21" ;
NET "IIOF_0" LOC = "V11" ;
NET "ADCA_RDY_GCLK" LOC = "W11" ;
NET "ZBT_nOE" LOC = "D14" ;
NET "ZBT_nLBO" LOC = "B12" ;
NET "ZBT_nCS2" LOC = "C13" ;
NET "ZBT_nCS1" LOC = "C12" ;
NET "ZBT_nCKE" LOC = "A14" ;
NET "ZBT_nBWd" LOC = "A13" ;
NET "ZBT_nBWc" LOC = "E14" ;
NET "ZBT_nBWb" LOC = "E13" ;
NET "ZBT_nBWa" LOC = "D13" ;
NET "ZBT_ZZ" LOC = "B15" ;
NET "ZBT_nWE" LOC = "B14" ;
NET "ZBT_DQd<7>" LOC = "E11" ;
NET "ZBT_DQd<6>" LOC = "F11" ;
NET "ZBT_DQd<5>" LOC = "B10" ;
NET "ZBT_DQd<4>" LOC = "A10" ;
NET "ZBT_DQd<3>" LOC = "E10" ;
NET "ZBT_DQd<2>" LOC = "F10" ;
NET "ZBT_DQd<1>" LOC = "D10" ;
NET "ZBT_DQd<0>" LOC = "C10" ;
NET "ZBT_DQc<7>" LOC = "D8" ;
NET "ZBT_DQc<6>" LOC = "C8" ;
NET "ZBT_DQc<5>" LOC = "B7" ;
NET "ZBT_DQc<4>" LOC = "A7" ;
NET "ZBT_DQc<3>" LOC = "D7" ;
NET "ZBT_DQc<2>" LOC = "C7" ;
NET "ZBT_DQc<1>" LOC = "E7" ;
NET "ZBT_DQc<0>" LOC = "E8" ;
NET "ZBT_DQb<7>" LOC = "A4" ;
NET "ZBT_DQb<6>" LOC = "B4" ;
NET "ZBT_DQb<5>" LOC = "A5" ;
NET "ZBT_DQb<4>" LOC = "B5" ;
NET "ZBT_DQb<3>" LOC = "A6" ;
NET "ZBT_DQb<2>" LOC = "B6" ;
NET "ZBT_DQb<1>" LOC = "C6" ;
NET "ZBT_DQb<0>" LOC = "D6" ;
NET "ZBT_DQa<7>" LOC = "A8" ;
NET "ZBT_DQa<6>" LOC = "B8" ;
NET "ZBT_DQa<5>" LOC = "F9" ;
NET "ZBT_DQa<4>" LOC = "E9" ;
NET "ZBT_DQa<3>" LOC = "C9" ;
NET "ZBT_DQa<2>" LOC = "D9" ;
NET "ZBT_DQa<1>" LOC = "A9" ;
NET "ZBT_DQa<0>" LOC = "B9" ;
NET "ZBT_CS2" LOC = "B13" ;
NET "ZBT_CLK" LOC = "B11" ;
NET "ZBT_ADV" LOC = "C14" ;
NET "ZBT_ADDR<19>" LOC = "C4" ;
NET "ZBT_ADDR<18>" LOC = "C5" ;
NET "ZBT_ADDR<17>" LOC = "E6" ;
NET "ZBT_ADDR<16>" LOC = "E5" ;
NET "ZBT_ADDR<15>" LOC = "C2" ;
NET "ZBT_ADDR<14>" LOC = "C1" ;
NET "ZBT_ADDR<13>" LOC = "D2" ;
NET "ZBT_ADDR<12>" LOC = "D1" ;
NET "ZBT_ADDR<11>" LOC = "E4" ;
NET "ZBT_ADDR<10>" LOC = "E3" ;
NET "ZBT_ADDR<9>" LOC = "E2" ;
NET "ZBT_ADDR<8>" LOC = "E1" ;
NET "ZBT_ADDR<7>" LOC = "F5" ;
NET "ZBT_ADDR<6>" LOC = "G5" ;
NET "ZBT_ADDR<5>" LOC = "F4" ;
NET "ZBT_ADDR<4>" LOC = "F3" ;
NET "ZBT_ADDR<3>" LOC = "F2" ;
NET "ZBT_ADDR<2>" LOC = "F1" ;
NET "ZBT_ADDR<1>" LOC = "G4" ;
NET "ZBT_ADDR<0>" LOC = "G3" ;
NET "ZBT_CLK_FB" LOC = "A11" ;
NET "PXI_CLK" LOC = "C18" ;
NET "PXI_TRIG1" LOC = "E18" ;
NET "PXI_TRIG2" LOC = "C22" ;
NET "PXI_TRIG3" LOC = "C21" ;
NET "PXI_TRIG4" LOC = "D18" ;
NET "SHBA_CLK0" LOC = "E12" ;
NET "SHBA_CLK1" LOC = "D12" ;
NET "SHBB_CLK0" LOC = "F12" ;
NET "SHBB_CLK1" LOC = "F13" ;
NET "TTLs<3>" LOC = "A15" ;
NET "TTLs<2>" LOC = "D15" ;
NET "TTLs<1>" LOC = "C15" ;
NET "TTLs<0>" LOC = "E15" ;
NET "nRESET" LOC = "V12" ;
NET "LEDs<3>" LOC = "F14" ;
NET "LEDs<2>" LOC = "B16" ;
NET "LEDs<1>" LOC = "A16" ;
NET "LEDs<0>" LOC = "D16" ;