Sundance Spas SMT332 User manual

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
SMT332/372
User Manual

Version 1.3 Page 2of 36 SMT332/372 User Manual
Revision History
Date Comments Engineer Version
7/3/00 Original Revision GP 1.1
9/3/00 General reorganisation GP 1.2
14/08/00 Comport data rate (safe mode not working)
and samples code using DMA AN 1.3
23/2/01 Corrected FIFO status memory space. GP 1.4

Version 1.3 Page 3of 36 SMT332/372 User Manual
Outline Description
The SMT332/372 is a size 1 TIM offering the following features:
?? SMT332: TMS320C6201 processor running at 200MHz
?? SMT372: TMS320C6701 processor running at 166MHz
?? Four communications ports (approx 15M bytes/s)
?? 512k bytes of fast SBSRAM, 16M bytes SDRAM
?? 256k byte Flash ROM for boot code
?? Global expansion connector
?? High bandwidth data input via 2 x 16-bit x 32K synchronous FIFOs (SDB)

Version 1.3 Page 4of 36 SMT332/372 User Manual
Table of Contents
Revision History...................................................................................................2
Outline Description...............................................................................................3
Table of Contents.................................................................................................4
Block Diagram.....................................................................................................6
Architecture Description........................................................................................6
TMS320C6201/6701 (‘C6x01)...............................................................................7
Boot Mode .......................................................................................................7
EMIF Control Registers.....................................................................................8
SBSRAM.............................................................................................................8
SDRAM...............................................................................................................8
Flash...................................................................................................................9
Comm ports.........................................................................................................9
Interrupts........................................................................................................... 11
NMI ............................................................................................................... 15
IACK.............................................................................................................. 15
CONFIG............................................................................................................ 15
FIFO Data Input/Output ...................................................................................... 16
Global Expansion............................................................................................... 18
Clock Speed...................................................................................................... 19
Memory Map (MAP 1)........................................................................................ 20
Example Code................................................................................................... 21
Code Composer................................................................................................. 29
Application Development .................................................................................... 29
Mechanical Configuration................................................................................... 30
Operating Conditions.......................................................................................... 31
Safety............................................................................................................ 31
EMC.............................................................................................................. 31
Power Requirements ...................................................................................... 31
Power Consumption........................................................................................ 31
Connectors........................................................................................................ 32
Tim Connector Position................................................................................... 32

Version 1.3 Page 5of 36 SMT332/372 User Manual
Serial Ports .................................................................................................... 35
FPGA Configuration........................................................................................... 36

Version 1.3 Page 6of 36 SMT332/372 User Manual
Block Diagram
SBSRAM
512k bytes
SDRAM
16Mbytes
FLASH
256Kbytes
Global
Access
Logic
0
3
1 2
5
4
J2 Secondary Connector
J1 Primary Connector
JTAG Port
J3 Global Connector
Clock
Synth
TMS320C6201/
TMS320C6701
DMA/FIFO
Comm-ports
32Kx16 FIFO
32Kx16 FIFO
40
WAY
40
WAY
16
16
Serial Port
Architecture Description
The SMT332 TIM consists of a Texas Instruments TMS320C6201 running at
200MHz and the SMT372 has a TMS320C6701 running at 166MHz. The TIM is
populated with 512k bytes of SBSRAM (synchronous burst SRAM) and 16M bytes of
SDRAM (synchronous DRAM) offering a total memory capacity of 16.5M bytes.
Additionally there are several programmable logic devices controlling such functions
as communications ports and global bus access.
256k bytes of in-circuit re-programmable Flash ROM is provided to store boot code.

Version 1.3 Page 7of 36 SMT332/372 User Manual
TMS320C6201/6701 (‘C6x01)
The TMS320C6201 (‘C6201) will run at 200MHz with zero wait-states from internal
SRAM. The TMS320C6701 (‘C6701) will run at 166MHz with zero wait-states from
internal SRAM.
The clock used for the ‘C6x01 is provided from an on-board source only, unlike other
‘C4x (TMS320C4x) TIMs which can select the CPU speed from an external source
via the TIM motherboard. The on-board source is a clock synthesiser from
MicroClock, and its clock output is user selectable (via jumpers) from between 118
and 200MHz.
The configuration (config) feature is fully implemented and provides a single open
collector line which can be held low until the module has been configured. This is
provided by a control register accessible by the ‘C6x01.
Boot Mode
The ‘C6x01 is capable of booting in several different modes. On the
SMT332/372, the boot mode is defined such that the ‘C6x01, after reset, will
copy the first 64kb of flash data into internal program RAM, and then execute
that code.
The second stage (code execution), sets up all necessary ‘C6x01 internal
registers, and then configures the FPGA (communications port {comm port}
controller) from other data held within the flash memory.
The final stage is to execute a ‘C4x type boot loader. This process continually
examines the state of the comm port status register and will, when it
determines which port data is present, then load a ‘C6x01 boot file which is
then executed. Refer to the Application Development section for more
information.
Whilst this stage of booting is in progress, all of the other comm ports will be
ignored

Version 1.3 Page 8of 36 SMT332/372 User Manual
EMIF Control Registers
The ‘C6x01 contains several registers which control the operation of the
external memory interface (EMIF). Each memory space (CE0 to 3) has an
independent register, and in addition, there is a global control register.
A full description of these registers is within the ‘C6x01 Peripherals Reference
Guide.
Briefly, these registers should contain the following values:
GC (global
control) 0x00003779
0x0000377D For ½ speed SBSRAM For full speed SBSRAM
CE0 0x00000040 Indicates SBSRAM
CE1 0x8238C823 Defines async memory timings
CE2 0x00000030 Indicates SDRAM
CE3 0x00000030
0xFFFF3F23
Defines SDRAM timings for access to
the FIFO data.
Defines async memory timings
for access to FIFO flag programming.
SBSRAM
Connected to the ‘C6x01 external memory interface (EMI), using memory space
CE0, are 512k byte of zero wait state SRAM.
The SBSRAM can be set (via an internal ‘C6x01 register) to operate at either the
‘C6x01 core clock, or ½ the core clock speed. This requirement has to be considered
in conjunction with the ‘C6x01 core speed and external memory speed refer to clock
speed for further details), but normally the SBSRAM would be set to run at the core
speed.
SDRAM
Connected to the ‘C6x01 external memory interface, using memory space CE2, is a
16M byte bank of SDRAM.
The SDRAM operates at ½ the core clock speed.

Version 1.3 Page 9of 36 SMT332/372 User Manual
Flash
A 256k byte Flash ROM device is fitted to the ‘C6x01 EMI. This device is byte
accessed using strobe CE1 (from 0x0140 0000 to 0x0143 ffff)
This device contains boot code for the ‘C6x01 and configuration data for the FPGA.
A software protection algorithm is in place to protect erroneous altering of the
device’s contents. Please contact Sundance for further information with regard to re-
programming this device.
Comm ports
The ‘C6x01 does not include, within the device itself, any means of communicating
high speed data to other processors. For operation in a TIM 40 environment, 4
communication (comm) ports are provided.
The comm ports on the SMT332/372 will interface to any standard ‘C4x comm port.
The comm ports can operate in two modes. The first mode is for the ‘C6x01 to
transfer data to the port directly using a polling technique. The second mode is for
the ‘C6x01’s DMA controller to be set to event triggered and select the appropriate
trigger (INT4..7) for the transfer.
The minimum comport data rate is about 9.2MB/s.
The following table shows the ‘C6x01 address map for the comm port interface.
Address (hex) Function
0160 0000 Comm port data register –Comm Port 0
0160 0004 Comm port data register –Comm Port 3
0160 0008 Comm port data register –Comm Port 1
0160 000c Comm port data register –Comm Port 4
0160 0010 Comm port status register (read only)
0160 0014 Comm port interrupt control register -ICRA
(write only)
0160 0018 Generate TIM IACK signal (read or write)
0160 001c Reset register (read or write)

Version 1.3 Page 10 of 36 SMT332/372 User Manual
The following table defines the bit functions within the status register.
Status Register Bit Function
0Comm port 0 rx data available
1Comm port 0 tx buffer empty
2Comm port 3 rx data available
3Comm port 3 tx buffer empty
4Comm port 1 rx data available
5Comm port 1 tx buffer empty
6Comm port 4 rx data available
7Comm port 4 tx buffer empty
The comm ports are implemented within a Xilinx FPGA.
The normal Sundance boot procedure will automatically configure this device. It is
not recommended that the user attempts to re-program this FPGA.

Version 1.3 Page 11 of 36 SMT332/372 User Manual
Interrupts
The interrupts to the ‘C6x01 can be produced by
?? comm port status change
?? DMA completion
?? FIFO flag status change
?? external IIOF and TCLK signals present on the TIM connector
There are two registers that control the interrupt enabling. Interrupt Control register A
(ICRA) provides the first stage of interrupt selection, followed by Interrupt Control
Register B (ICRB).
When interrupts are enabled, they will be generated for every comm port word
received or transmitted (as appropriate). The selection of fast or slow interrupts
requires understanding of the timings between the STRB and RDY signals on the
comm port. Slow interrupts are generated when the fourth STRB of a word transfer
goes high. At some point after this the ‘C6x01 External Memory Interface strobe
(nCE1) becomes active. However, to allow the comm port data transfer to be
speeded up, the fast interrupts are generated on the second STRB going high. This
assumes the fourth STRB and RDY arrive before the ‘C6x01 has reacted to the early
interrupt. This is normally the case, but if the comm port is being connected to a slow
peripheral which does not guarantee the arrival of the last two comm port strobes,
then data errors may result. These enable signals can be delayed by writing to the
EMIF CE1 space control register. Warning -if fast interrupts are used and the enable
signal goes low too early this could result in the transfer hanging or incorrect data
transfer.

Version 1.3 Page 12 of 36 SMT332/372 User Manual
Address (hex) Function
0160 0014 Interrupt control register A
Interrupt Control Register Bit Function
1 & 0 00: Enable Comm Port 0 rx data available to INT4
01: Enable Comm Port 0 tx data available to INT4
10: Enable IIOF0 to INT4
11: Enable TCLK0 to INT4
3 & 2 00: Enable Comm Port 3 rx data available to INT5
01: Enable Comm Port 3 tx data available to INT5
10: Enable IIOF1 to INT5
11: Enable TCLK1 to INT5
5 & 4 00: Enable Comm Port 1 rx data available to INT6
01: Enable Comm Port 1 tx data available to INT6
10: Enable IIOF2 to INT6
11: Enable IIOF1 to INT6
7 & 6 00: Enable Comm Port 4 rx data available to INT7
01: Enable Comm Port 4 tx data available to INT7
10: Enable IIOF0 to INT7
11: Enable IIOF2 to INT7
80: Comm Port 0 rx slow 1: Comm Port 0 rx fast
90: Comm Port 0 tx slow 1: Comm Port 0 tx fast
10 0: Comm Port 3 rx slow 1: Comm Port 3 rx fast
11 0: Comm Port 3 tx slow 1: Comm Port 3 tx fast
12 0: Comm Port 1 rx slow 1: Comm Port 1 rx fast
13 0: Comm Port 1 tx slow 1: Comm Port 1 tx fast
14 0: Comm Port 4 rx slow 1: Comm Port 4 rx fast
15 0: Comm Port 4 tx slow 1: Comm Port 4 tx fast
16 Enable Comm Port 0 rx to INT7
17 Enable Comm Port 0 tx to INT7
18 Enable Comm Port 3 rx to INT7
19 Enable Comm Port 3 tx to INT7
20 Enable Comm Port 1 rx to INT7
21 Enable Comm Port 1 tx to INT7
22 Enable Comm Port 4 rx to INT7
23 Enable Comm Port 4 tx to INT7
IMPORTANT: Comport Fast mode is not supported for the moment.

Version 1.3 Page 13 of 36 SMT332/372 User Manual
Address (hex) Function
0158 0000 Interrupt control register B -ICRB (write only)
Interrupt Control Register Bit Function
8Clear to enable FIFO Channel A, flag to INT4.
Set to enable CINT4 to INT4.
9Clear to enable FIFO Channel A, flag to INT5.
Set to enable CINT5 to INT5.
10 Clear to enable FIFO Channel B, flag to INT6.
Set to enable CINT6 to INT6.
11 Clear to enable FIFO Channel B, flag to INT7.
Set to enable CINT7 to INT7.
13 & 12 Channel A FIFO flag control.
00: select empty flag
01: select almost empty flag
10: select almost full flag
11: select full flag
15 & 14 Channel B FIFO flag control.
00: select empty flag
01: select almost empty flag
10: select almost full flag
11: select full flag
Note: Channel A/B relates to the 2 FIFO devices. Refer to the FIFO section for further
details.

Version 1.3 Page 14 of 36 SMT332/372 User Manual
The functions of ICRA and ICRB are shown diagrammatically below:
0
1
1
0
1
0
0
1
ICRB8
ICRB9
ICRB10
ICRB11
ICRB13:12
ICRB15:14

Version 1.3 Page 15 of 36 SMT332/372 User Manual
NMI
The NMI pin is routed to the TIM connector.
IACK
On a standard ‘C4x TIM, the processors IACK (interrupt acknowledge) signal
is connected to the TIM connector.
On the SMT332/372, this IACK signal is generated by the ‘C6x01 writing to
address 0x01600018. The length of the pulse will be determined by the
External Memory Interface register settings for memory space CE1. With the
default timings, this pulse will be 40ns.
CONFIG
The TIM specification describes the operation of an open-collector type signal
(CONFIG) which is asserted (low) after reset.
This signal, on a standard ‘C4x based TIM, is connected to the processor’s IIOF3 pin.
On the SMT332/372, the CONFIG signal is asserted after power on, and can be
released by writing to the interrupt control register A (address 0x0160 0014) with bit 8
set. Conversely, CONFIG may be re-asserted by writing this bit with a 0.

Version 1.3 Page 16 of 36 SMT332/372 User Manual
FIFO Data Input/Output
The SMT332/372 provides a high bandwidth data input facility for up to 32-bit data.
The inputs are split in two 16-bit channels. Both channels are identical and may be
referred to as Channel A & B with Channel A representing the least significant 16-bits
and B the most significant 16-bits of the 32-bit word.
Each data source is connected to the SMT332/372 via a 40-way connector allowing
for signal and return paths. The 40 way connectors are mounted on the topside of the
PCB for direct cable connection. Alternatively an 80-way connector may be mounted
on the underside of the PCB for connection to customised TIM carriers, etc. The
default option is for connectors on the TOP of the PCB.
Each input channel is provided with a separate clock (WCLK*), enable (WEN*), FIFO
reset (Reset*) and flag (programmable almost full flag) signals in the event that
independent data sources are required.
Data is routed from the connectors to FIFOs which provide 32K x 16 storage of Input
data at rates up to 100MHz. The FIFOs are interfaced to the ‘C6x EMIF which
enables them to be address as a 32-bit word. The ‘C6x can be programmed to
receive an interrupt when the FIFO has reached a certain level (see Interrupts).
The pin allocation for the I/O connectors is shown in Appendix.
The control signals are derived from the FIFO requirements that may be seen in the
appropriate data sheet. The device used is an IDT72284 a copy of which is available
in PDF format from Sundance.
Channel B’s control signals will be used by default in a 32-bit application
WCLK Data is written in to the FIFO on every rising edge when WEN
is valid.
/WEN WEN enables WCLK for writing data into the FIFO memory
/Reset FIFO Reset resets the pointer to the first FIFO location
/FLAG Programmable FIFO Almost Full Flag
For the ‘C6x01 to read the FIFO, the EMIF needs to have the CE3 memory space
defined as SDRAM (see EMIF Control Register section). This is the only method by
which a 100MHz data rate can be sustained. The FIFO must be read using address
0x03000000 for port A (bottom 16 bits active), address 0x03400000 for port B (top 16
bits active) or address 0x03800000 for both ports (all data bits active).
In addition to an external device writing to the FIFO, it is necessary for the ‘C6x01 to
be able to have a limited write capability. This is required in order that the
programmable FIFO flags can be programmed. To set this access mode, the CE3
memory space must be defined as an asynchronous space, with maximum strobe
widths. Next the WEN and WCLK multiplexer needs to be switched. To enable
‘C6x01 access, it is necessary to write to address 0x03800000. Notice that this is the

Version 1.3 Page 17 of 36 SMT332/372 User Manual
same address as that needed for ‘both ports read’ function, but as we have switched
memory types (SDRAM to ASYNC) then the FIFOs are not actually accessed at all.
The FIFO flag positions need to be serially loaded. Data bit D19 is used for port A
FIFO, and data bit D23 for port B. Both FIFOs are programmed at the same time.
D17, D18, D21 and D22 must be set to 0s during the serial load. The serial load
address is 0x03000000. Upon completion of programming, the multiplexer needs to
be set to normal operating mode. This is done by writing to address 0x0300C000.
And finally, the memory needs to be defined as SDRAM.
For convenience, C source code routines for performing these function are included
on the distribution disc.
FIFO Status
The FIFO status can be read from address 0x01580000. The EMIF CE1 memory
space register must be set for asynchronous access. Note that the status is returned
on data bits 8-15 (not 0-7). Note also that the flag status bits are active when read as
a ‘0’.
Address (hex) Function
0158 0000 FIFO Status register (Read)
FIFO status Bit Function
8FIFO Channel A not empty flag.
9FIFO Channel A not almost empty flag.
10 FIFO Channel A not almost full flag.
11 FIFO Channel A not full flag.
12 FIFO Channel B not empty flag.
13 FIFO Channel B not almost empty flag.
14 FIFO Channel B not almost full flag.
15 FIFO Channel B not full flag.

Version 1.3 Page 18 of 36 SMT332/372 User Manual
Global Expansion
Part of the TIM4x specification defines an optional global expansion connector (J3).
This expansion connector allows the TIM’s CPU access to host motherboard
resources, where available.
The ‘C6x01’s EMIF is not directly compatible with the TIM global connector standard.
This is due primarily to the ‘C6x01 bus speed and bus voltage levels.
The SMT332/372 does implement a fully compatible TIM global connector through
the use of an EPLD.
The global bus transactions are synchronised to the ‘C6x01 clock speed.
The global bus may be accessed directly by the ‘C6x01 (via this EPLD) where it may
perform reads or writes.
A maximum block size of 64k words can be accessed at any one time due to the
limited number of address bits from the ‘C6x01. So to access the whole global
memory range, a page register is used which holds the value of the upper 15
address bits.
Address (hex) Function
0170 0000 –0173 FFFC Global access (4 byte boundaries)
0178 0000 Global address page register
The global address page register must have the bottom 15 bits loaded with the top
15 bits of the global address.
An example of how to use this interface is given in the Example Code section.

Version 1.3 Page 19 of 36 SMT332/372 User Manual
Clock Speed
The ‘C6x01 clock speed must be set in conjunction with consideration to EMIF device
speeds. Under most circumstances, the ‘C6201 would be set to 200MHz and have
an SBSRAM speed equal to the core speed. The ‘C6701 would be set to 166MHz.
The following table shows all available possibilities:
Device Comment
‘C6x01 SBSRAM SDRAM
133 133 67 Zero wait state SBSRAM
166 166 83 Zero wait state SBSRAM
200 100 100 One wait state SBSRAM
200 200 100 Zero wait state SBSRAM
The following table defines the link positions of JP1 and the resultant clock speed.
S2 S1 S0 CLK (MHz)
000200
001182
010167
011154
100143
101133
110125
111118
S0, S1 and S2 refer to the following link positions on JP1. Link in to force a ‘0’.
S2 S1 S0

Version 1.3 Page 20 of 36 SMT332/372 User Manual
Memory Map (MAP 1)
Starting Address RESOURCE Refer to
0000 0000 Internal Program RAM
0001 0000 Reserved
0040 0000 External Memory Space CE0
512kb SBSRAM SBSRAM
0140 0000 External Memory Space CE1
256kb Flash Flash
0150 0000 External Memory Space CE1
FPGA program pin control Comm Ports
0158 0000 External Memory Space CE1
WR: Interrupt Control Register B –ICRB
RD: FIFO Flag Status
Comm Ports
0160 0000 External Memory Space CE1
FPGA internal registers (Comm ports) Comm Ports
0170 0000 External Memory Space CE1
Global bus access Global
Expansion
0178 0000 External Memory Space CE1
Global bus page register Global
Expansion
0180 0000 Internal Peripherals
01C0 0000 Reserved
0200 0000 External Memory Space CE2
16Mb SDRAM SDRAM
0300 0000 External Memory Space CE3
FIFO A:0x03000000, FIFO B:0x03400000
FIFO A+B:0x03800000
FIFO
0400 0000 Reserved
8000 0000 Internal Data RAM
8001 0000 Reserved
8040 0000 Reserved