Sundance Spas SMT332 User manual

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
SMT332/372
User Manual

Version 1.3 Page 2of 36 SMT332/372 User Manual
Revision History
Date Comments Engineer Version
7/3/00 Original Revision GP 1.1
9/3/00 General reorganisation GP 1.2
14/08/00 Comport data rate (safe mode not working)
and samples code using DMA AN 1.3
23/2/01 Corrected FIFO status memory space. GP 1.4

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Outline Description
The SMT332/372 is a size 1 TIM offering the following features:
?? SMT332: TMS320C6201 processor running at 200MHz
?? SMT372: TMS320C6701 processor running at 166MHz
?? Four communications ports (approx 15M bytes/s)
?? 512k bytes of fast SBSRAM, 16M bytes SDRAM
?? 256k byte Flash ROM for boot code
?? Global expansion connector
?? High bandwidth data input via 2 x 16-bit x 32K synchronous FIFOs (SDB)

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Table of Contents
Revision History...................................................................................................2
Outline Description...............................................................................................3
Table of Contents.................................................................................................4
Block Diagram.....................................................................................................6
Architecture Description........................................................................................6
TMS320C6201/6701 (‘C6x01)...............................................................................7
Boot Mode .......................................................................................................7
EMIF Control Registers.....................................................................................8
SBSRAM.............................................................................................................8
SDRAM...............................................................................................................8
Flash...................................................................................................................9
Comm ports.........................................................................................................9
Interrupts........................................................................................................... 11
NMI ............................................................................................................... 15
IACK.............................................................................................................. 15
CONFIG............................................................................................................ 15
FIFO Data Input/Output ...................................................................................... 16
Global Expansion............................................................................................... 18
Clock Speed...................................................................................................... 19
Memory Map (MAP 1)........................................................................................ 20
Example Code................................................................................................... 21
Code Composer................................................................................................. 29
Application Development .................................................................................... 29
Mechanical Configuration................................................................................... 30
Operating Conditions.......................................................................................... 31
Safety............................................................................................................ 31
EMC.............................................................................................................. 31
Power Requirements ...................................................................................... 31
Power Consumption........................................................................................ 31
Connectors........................................................................................................ 32
Tim Connector Position................................................................................... 32

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Serial Ports .................................................................................................... 35
FPGA Configuration........................................................................................... 36

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Block Diagram
SBSRAM
512k bytes
SDRAM
16Mbytes
FLASH
256Kbytes
Global
Access
Logic
0
3
1 2
5
4
J2 Secondary Connector
J1 Primary Connector
JTAG Port
J3 Global Connector
Clock
Synth
TMS320C6201/
TMS320C6701
DMA/FIFO
Comm-ports
32Kx16 FIFO
32Kx16 FIFO
40
WAY
40
WAY
16
16
Serial Port
Architecture Description
The SMT332 TIM consists of a Texas Instruments TMS320C6201 running at
200MHz and the SMT372 has a TMS320C6701 running at 166MHz. The TIM is
populated with 512k bytes of SBSRAM (synchronous burst SRAM) and 16M bytes of
SDRAM (synchronous DRAM) offering a total memory capacity of 16.5M bytes.
Additionally there are several programmable logic devices controlling such functions
as communications ports and global bus access.
256k bytes of in-circuit re-programmable Flash ROM is provided to store boot code.

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TMS320C6201/6701 (‘C6x01)
The TMS320C6201 (‘C6201) will run at 200MHz with zero wait-states from internal
SRAM. The TMS320C6701 (‘C6701) will run at 166MHz with zero wait-states from
internal SRAM.
The clock used for the ‘C6x01 is provided from an on-board source only, unlike other
‘C4x (TMS320C4x) TIMs which can select the CPU speed from an external source
via the TIM motherboard. The on-board source is a clock synthesiser from
MicroClock, and its clock output is user selectable (via jumpers) from between 118
and 200MHz.
The configuration (config) feature is fully implemented and provides a single open
collector line which can be held low until the module has been configured. This is
provided by a control register accessible by the ‘C6x01.
Boot Mode
The ‘C6x01 is capable of booting in several different modes. On the
SMT332/372, the boot mode is defined such that the ‘C6x01, after reset, will
copy the first 64kb of flash data into internal program RAM, and then execute
that code.
The second stage (code execution), sets up all necessary ‘C6x01 internal
registers, and then configures the FPGA (communications port {comm port}
controller) from other data held within the flash memory.
The final stage is to execute a ‘C4x type boot loader. This process continually
examines the state of the comm port status register and will, when it
determines which port data is present, then load a ‘C6x01 boot file which is
then executed. Refer to the Application Development section for more
information.
Whilst this stage of booting is in progress, all of the other comm ports will be
ignored

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EMIF Control Registers
The ‘C6x01 contains several registers which control the operation of the
external memory interface (EMIF). Each memory space (CE0 to 3) has an
independent register, and in addition, there is a global control register.
A full description of these registers is within the ‘C6x01 Peripherals Reference
Guide.
Briefly, these registers should contain the following values:
GC (global
control) 0x00003779
0x0000377D For ½ speed SBSRAM For full speed SBSRAM
CE0 0x00000040 Indicates SBSRAM
CE1 0x8238C823 Defines async memory timings
CE2 0x00000030 Indicates SDRAM
CE3 0x00000030
0xFFFF3F23
Defines SDRAM timings for access to
the FIFO data.
Defines async memory timings
for access to FIFO flag programming.
SBSRAM
Connected to the ‘C6x01 external memory interface (EMI), using memory space
CE0, are 512k byte of zero wait state SRAM.
The SBSRAM can be set (via an internal ‘C6x01 register) to operate at either the
‘C6x01 core clock, or ½ the core clock speed. This requirement has to be considered
in conjunction with the ‘C6x01 core speed and external memory speed refer to clock
speed for further details), but normally the SBSRAM would be set to run at the core
speed.
SDRAM
Connected to the ‘C6x01 external memory interface, using memory space CE2, is a
16M byte bank of SDRAM.
The SDRAM operates at ½ the core clock speed.

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Flash
A 256k byte Flash ROM device is fitted to the ‘C6x01 EMI. This device is byte
accessed using strobe CE1 (from 0x0140 0000 to 0x0143 ffff)
This device contains boot code for the ‘C6x01 and configuration data for the FPGA.
A software protection algorithm is in place to protect erroneous altering of the
device’s contents. Please contact Sundance for further information with regard to re-
programming this device.
Comm ports
The ‘C6x01 does not include, within the device itself, any means of communicating
high speed data to other processors. For operation in a TIM 40 environment, 4
communication (comm) ports are provided.
The comm ports on the SMT332/372 will interface to any standard ‘C4x comm port.
The comm ports can operate in two modes. The first mode is for the ‘C6x01 to
transfer data to the port directly using a polling technique. The second mode is for
the ‘C6x01’s DMA controller to be set to event triggered and select the appropriate
trigger (INT4..7) for the transfer.
The minimum comport data rate is about 9.2MB/s.
The following table shows the ‘C6x01 address map for the comm port interface.
Address (hex) Function
0160 0000 Comm port data register –Comm Port 0
0160 0004 Comm port data register –Comm Port 3
0160 0008 Comm port data register –Comm Port 1
0160 000c Comm port data register –Comm Port 4
0160 0010 Comm port status register (read only)
0160 0014 Comm port interrupt control register -ICRA
(write only)
0160 0018 Generate TIM IACK signal (read or write)
0160 001c Reset register (read or write)

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The following table defines the bit functions within the status register.
Status Register Bit Function
0Comm port 0 rx data available
1Comm port 0 tx buffer empty
2Comm port 3 rx data available
3Comm port 3 tx buffer empty
4Comm port 1 rx data available
5Comm port 1 tx buffer empty
6Comm port 4 rx data available
7Comm port 4 tx buffer empty
The comm ports are implemented within a Xilinx FPGA.
The normal Sundance boot procedure will automatically configure this device. It is
not recommended that the user attempts to re-program this FPGA.