Sundance Spas SMT351 User manual

SMT351
User Manual

Version 1.1 Page 2 of 24 SMT351 User Manual
Revision History
Date Comments Engineer Version
28/07/04 First revision JPA 1.1

Version 1.1 Page 3 of 24 SMT351 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Introduction................................................................................................................. 7
Description .............................................................................................................. 7
Features.................................................................................................................. 7
Additional resources ............................................................................................... 7
Architecture description .............................................................................................. 8
SMT351 block diagram ........................................................................................... 8
Block description..................................................................................................... 9
FPGA ...................................................................................................................... 9
Memory................................................................................................................... 9
CPLD ...................................................................................................................... 9
Sundance High Speed Bus ..................................................................................... 9
Comports ................................................................................................................ 9
TTL I/Os. ................................................................................................................. 9
LEDs ..................................................................................................................... 10
JTAG..................................................................................................................... 10
Switch ................................................................................................................... 10
Using the SMT351.................................................................................................... 11
FPGA Configuration ................................................................................................. 12
Reset ........................................................................................................................ 13
Functional description............................................................................................... 14
FPGA design overview.......................................................................................... 14
Memory banks ...................................................................................................... 14
Sundance High Speed Bus (SHB) ........................................................................ 15
Registers............................................................................................................... 15
Clock structure ...................................................................................................... 16
FPGA implementation .............................................................................................. 17
Language .............................................................................................................. 17
Synthesis and Implementation tool ....................................................................... 17
FPGA resource usage .......................................................................................... 17

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Register definition..................................................................................................... 18
FPGA reset register (0x00) ................................................................................... 18
Control register (0x02) .......................................................................................... 18
Software ................................................................................................................... 19
SMT351_Config .................................................................................................... 19
Definition ........................................................................................................... 19
Prototype ........................................................................................................... 19
Parameters........................................................................................................ 19
SMT351_Capture.................................................................................................. 19
Definition ........................................................................................................... 19
Prototype ........................................................................................................... 19
Parameters........................................................................................................ 19
SMT351_PlayBack ............................................................................................... 19
Definition ........................................................................................................... 19
Prototype ........................................................................................................... 19
Connector Locations................................................................................................. 20
JP2 pinout................................................................................................................. 21
JP1 pinout................................................................................................................. 23
Physical Properties................................................................................................... 24

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Table of Figures
Figure 1: SMT351 board block diagram ..................................................................... 8
Figure 2: SMT351 FPGA data flow........................................................................... 14
Figure 3: DDR SDRAM components bank organization. .......................................... 15
Figure 4: FPGA’s clock domains .............................................................................. 16
Figure 5: SMT351 connector locations ..................................................................... 20
Figure 6: TTL I/Os (JP2) pinout ................................................................................ 22
Figure 7: JTAG header (JP1) pinout......................................................................... 23

Tables of Tables
Table 1: LED description .......................................................................................... 10
Table 2: configuration comport selection. ................................................................. 12
Table 3: TIM CONFIG feature: SW1 settings ........................................................... 13
Table 4: FPGA’s clock domains description ............................................................. 16

Introduction
Description
The SMT351 card is a TIM format memory module that is able to store up to 1GB of
data at 400MB/s.
SMT351 modules can be cascaded to extend storage capability.
The module is based on DDR SDRAM memory components running at up to 133
MHz.
DDR (Double Data Rate) SDRAM activates the data outputs on both the rising and
falling edges of the system clock rather than on just the rising edge, potentially
doubling the output.
A Xilinx Virtex-II Pro FPGA (or XC2VP20, or XC2VP30) controls input and output
data flows on two Sundance High-speed Bus (SHB) connectors. This bus is
compatible with a wide range of Sundance processor, converter and I/O modules
Features
2 x Sundance High-speed Bus (SHB) connectors
6 x comport connectors
Xilinx VirtexII Pro FPGA XC2VP7 (or XC2VP20, or XC2VP30)
1GB Double Data Rate (DDR) SDRAM 133 MHz
Additional resources
SUNDANCE SHB specification
TI TIM specification & user’s guide.
Samtec QSH Catalogue page
Micron DDR SDRAM webpage

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Architecture description
SMT351 block diagram
Figure 1 shows a block diagram of the SMT351 board. Refer to the following section
for additional information on the major blocks.
2 x RSL Connectors
(8 RSL Interfaces)
Xilinx FPGA
VirtexII-Pro, FF896
XC2VP7,20,30
1.5V Core
2.5/3.3V I/O
6-pin JTAG
header
J2 Bottom Secondary TIM
Connector
4x ComPorts/SDLs
J1 Top Primary TIM
Connector
2x ComPorts/SDLs
FPGA
configuration via
one of six
comports
40 I/O pins (D+@)
Clock + Feedback
2 x Sundance High-speed
Bus Connectors
40 I/O pins (D+@)
Clock + Feedback
128 (256) Mbytes DDR
RAM - MT46V16M16
40 I/O pins (D+@)
Clock + Feedback
128 (256) Mbytes DDR
RAM - MT46V16M16
40 I/O pins (D+@)
Clock + Feedback
4 LEDs + 4 TTL IOs
On-board Oscillator
50 MHz
External 5-Volt
Power Supply
converted to
2.5 Volts by a
DC-DC converter
128 (256) Mbytes DDR
RAM - MT46V16M16
128 (256) Mbytes DDR
RAM - MT46V16M16
3 Power
Supply
LEDs
‘FPGA configured’
LED
Figure 1: SMT351 board block diagram

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Block description
This section describes the major blocks of the SMT351 board.
FPGA
The SMT351 board uses a Xilinx Virtex II Pro (XC2VP7, XC2VP20 or XC2VP30) to
control the data flow between the SMT351 board and external devices. The FPGA is
also used to implement the SHB, comport and DDR SDRAM interfaces.
The FPGA is configured via a 6-pin JTAG header or from a user-selectable ComPort.
Memory
The SMT351 board contains sixteen 133 MHz DDR SDRAM components (from
Micron or Samsung) that provide 1 GB of storage capacity.
The DDR SDRAM is a high-speed CMOS, dynamic random-access memory.
CPLD
A Xilinx CPLD is used to manage configuring the FPGA. It connects to the six
comports available on the module.
Sundance High Speed Bus
Unidirectional 32-bit SHB interfaces are implemented on SHB connectors. They run
at 100 MHz, giving a 400MB/s data rate thru the SMT351.
SHB A implements a receiver-only interface while SHB B implements a transmitter-
only interface.
Please refer to the SUNDANCE SHB specification for more details.
Comports
The SMT351 provides up to 6 comports, which are used to receive the configuration
bitstream and commands to the FPGA. Once configured, the SMT351 is controlled
via comport 3.
The number of comports provided depends on the type of FPGA fitted on the board:
• XC2VP7 provides 3 comports: 0, 1 and 3.
• XC2VP20 or XC2VP30s provides 6 comports.
TTL I/Os.
Four TTL I/Os supporting LVTTL signals are connected directly to the FPGA (JP2).
These I/Os are not used by Sundance firmware and are available for customer use.
You must ensure that any lines you connect to these pins are LVTTL compatible in
order to protect the FPGA pads, as lines are not clamped.
See JP2 pinout section for more details.

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LEDs
Five LEDs are available on the board. They are all driven by the FPGA.
Table 1: LED description
LED # Description
D1 FPGA Done pin. The LED is on when FPAG is
NOT configured.
D2 Image of DDR SDRAM clock (board “heart
beat”).
D3 On when first half of memory is being written.
D4 On when Control Register bit 15 is high.
D5 On when memory is being read back.
JTAG
The SMT351 includes a 6-pin JTAG header (2mm DIL header), which allows re-
programming the FPGA using a cable such as Xilinx Parallel III or Parallel IV cables.
See connector location section for its location on board.
Refer to the following section for the pinout of this connector.
Switch
SMT351 provides two switches: SW1 and SW2.
SW1 is connected to CPLD and SW2 is connected to FPGA. SW2 is unused by the
default firmware.