Sundance Spas SMT351 User manual

SMT351
User Manual

Version 1.1 Page 2 of 24 SMT351 User Manual
Revision History
Date Comments Engineer Version
28/07/04 First revision JPA 1.1

Version 1.1 Page 3 of 24 SMT351 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Introduction................................................................................................................. 7
Description .............................................................................................................. 7
Features.................................................................................................................. 7
Additional resources ............................................................................................... 7
Architecture description .............................................................................................. 8
SMT351 block diagram ........................................................................................... 8
Block description..................................................................................................... 9
FPGA ...................................................................................................................... 9
Memory................................................................................................................... 9
CPLD ...................................................................................................................... 9
Sundance High Speed Bus ..................................................................................... 9
Comports ................................................................................................................ 9
TTL I/Os. ................................................................................................................. 9
LEDs ..................................................................................................................... 10
JTAG..................................................................................................................... 10
Switch ................................................................................................................... 10
Using the SMT351.................................................................................................... 11
FPGA Configuration ................................................................................................. 12
Reset ........................................................................................................................ 13
Functional description............................................................................................... 14
FPGA design overview.......................................................................................... 14
Memory banks ...................................................................................................... 14
Sundance High Speed Bus (SHB) ........................................................................ 15
Registers............................................................................................................... 15
Clock structure ...................................................................................................... 16
FPGA implementation .............................................................................................. 17
Language .............................................................................................................. 17
Synthesis and Implementation tool ....................................................................... 17
FPGA resource usage .......................................................................................... 17

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Register definition..................................................................................................... 18
FPGA reset register (0x00) ................................................................................... 18
Control register (0x02) .......................................................................................... 18
Software ................................................................................................................... 19
SMT351_Config .................................................................................................... 19
Definition ........................................................................................................... 19
Prototype ........................................................................................................... 19
Parameters........................................................................................................ 19
SMT351_Capture.................................................................................................. 19
Definition ........................................................................................................... 19
Prototype ........................................................................................................... 19
Parameters........................................................................................................ 19
SMT351_PlayBack ............................................................................................... 19
Definition ........................................................................................................... 19
Prototype ........................................................................................................... 19
Connector Locations................................................................................................. 20
JP2 pinout................................................................................................................. 21
JP1 pinout................................................................................................................. 23
Physical Properties................................................................................................... 24

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Table of Figures
Figure 1: SMT351 board block diagram ..................................................................... 8
Figure 2: SMT351 FPGA data flow........................................................................... 14
Figure 3: DDR SDRAM components bank organization. .......................................... 15
Figure 4: FPGA’s clock domains .............................................................................. 16
Figure 5: SMT351 connector locations ..................................................................... 20
Figure 6: TTL I/Os (JP2) pinout ................................................................................ 22
Figure 7: JTAG header (JP1) pinout......................................................................... 23

Tables of Tables
Table 1: LED description .......................................................................................... 10
Table 2: configuration comport selection. ................................................................. 12
Table 3: TIM CONFIG feature: SW1 settings ........................................................... 13
Table 4: FPGA’s clock domains description ............................................................. 16

Introduction
Description
The SMT351 card is a TIM format memory module that is able to store up to 1GB of
data at 400MB/s.
SMT351 modules can be cascaded to extend storage capability.
The module is based on DDR SDRAM memory components running at up to 133
MHz.
DDR (Double Data Rate) SDRAM activates the data outputs on both the rising and
falling edges of the system clock rather than on just the rising edge, potentially
doubling the output.
A Xilinx Virtex-II Pro FPGA (or XC2VP20, or XC2VP30) controls input and output
data flows on two Sundance High-speed Bus (SHB) connectors. This bus is
compatible with a wide range of Sundance processor, converter and I/O modules
Features
2 x Sundance High-speed Bus (SHB) connectors
6 x comport connectors
Xilinx VirtexII Pro FPGA XC2VP7 (or XC2VP20, or XC2VP30)
1GB Double Data Rate (DDR) SDRAM 133 MHz
Additional resources
SUNDANCE SHB specification
TI TIM specification & user’s guide.
Samtec QSH Catalogue page
Micron DDR SDRAM webpage

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Architecture description
SMT351 block diagram
Figure 1 shows a block diagram of the SMT351 board. Refer to the following section
for additional information on the major blocks.
2 x RSL Connectors
(8 RSL Interfaces)
Xilinx FPGA
VirtexII-Pro, FF896
XC2VP7,20,30
1.5V Core
2.5/3.3V I/O
6-pin JTAG
header
J2 Bottom Secondary TIM
Connector
4x ComPorts/SDLs
J1 Top Primary TIM
Connector
2x ComPorts/SDLs
FPGA
configuration via
one of six
comports
40 I/O pins (D+@)
Clock + Feedback
2 x Sundance High-speed
Bus Connectors
40 I/O pins (D+@)
Clock + Feedback
128 (256) Mbytes DDR
RAM - MT46V16M16
40 I/O pins (D+@)
Clock + Feedback
128 (256) Mbytes DDR
RAM - MT46V16M16
40 I/O pins (D+@)
Clock + Feedback
4 LEDs + 4 TTL IOs
On-board Oscillator
50 MHz
External 5-Volt
Power Supply
converted to
2.5 Volts by a
DC-DC converter
128 (256) Mbytes DDR
RAM - MT46V16M16
128 (256) Mbytes DDR
RAM - MT46V16M16
3 Power
Supply
LEDs
‘FPGA configured’
LED
Figure 1: SMT351 board block diagram

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Block description
This section describes the major blocks of the SMT351 board.
FPGA
The SMT351 board uses a Xilinx Virtex II Pro (XC2VP7, XC2VP20 or XC2VP30) to
control the data flow between the SMT351 board and external devices. The FPGA is
also used to implement the SHB, comport and DDR SDRAM interfaces.
The FPGA is configured via a 6-pin JTAG header or from a user-selectable ComPort.
Memory
The SMT351 board contains sixteen 133 MHz DDR SDRAM components (from
Micron or Samsung) that provide 1 GB of storage capacity.
The DDR SDRAM is a high-speed CMOS, dynamic random-access memory.
CPLD
A Xilinx CPLD is used to manage configuring the FPGA. It connects to the six
comports available on the module.
Sundance High Speed Bus
Unidirectional 32-bit SHB interfaces are implemented on SHB connectors. They run
at 100 MHz, giving a 400MB/s data rate thru the SMT351.
SHB A implements a receiver-only interface while SHB B implements a transmitter-
only interface.
Please refer to the SUNDANCE SHB specification for more details.
Comports
The SMT351 provides up to 6 comports, which are used to receive the configuration
bitstream and commands to the FPGA. Once configured, the SMT351 is controlled
via comport 3.
The number of comports provided depends on the type of FPGA fitted on the board:
• XC2VP7 provides 3 comports: 0, 1 and 3.
• XC2VP20 or XC2VP30s provides 6 comports.
TTL I/Os.
Four TTL I/Os supporting LVTTL signals are connected directly to the FPGA (JP2).
These I/Os are not used by Sundance firmware and are available for customer use.
You must ensure that any lines you connect to these pins are LVTTL compatible in
order to protect the FPGA pads, as lines are not clamped.
See JP2 pinout section for more details.

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LEDs
Five LEDs are available on the board. They are all driven by the FPGA.
Table 1: LED description
LED # Description
D1 FPGA Done pin. The LED is on when FPAG is
NOT configured.
D2 Image of DDR SDRAM clock (board “heart
beat”).
D3 On when first half of memory is being written.
D4 On when Control Register bit 15 is high.
D5 On when memory is being read back.
JTAG
The SMT351 includes a 6-pin JTAG header (2mm DIL header), which allows re-
programming the FPGA using a cable such as Xilinx Parallel III or Parallel IV cables.
See connector location section for its location on board.
Refer to the following section for the pinout of this connector.
Switch
SMT351 provides two switches: SW1 and SW2.
SW1 is connected to CPLD and SW2 is connected to FPGA. SW2 is unused by the
default firmware.

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Using the SMT351
The SMT351 will normally store up to 1 GB of data in memory. It’s possible to change
this setting using the SMT351_Capture function.
Following are described the main features that user should keep in mind when using
SMT351:
- SMT351 will start outputting data after half of the total amount of data to store
will have been provided to it.
- SMT351 must store at the minimum 16 KB data must. The module is not able
to store less that 16KB data.
- There must be a 1s delay after a reset command before any further
commands are sent to the SMT351.

FPGA Configuration
There are two ways to configure the FPGA:
1. Use the on-board JTAG header and Xilinx JTAG programming tools.
2. Send the configuration bitstream down the comport selected by SW1. The
Sundance library for the SMT351 includes a function to configure the FPGA in
this way.
The table below gives the possible settings for SW1:
Table 2: configuration comport selection.
Comport
number
Switch
number 1
Switch
number 2
Switch
number 3
Switch
number 4
0 ON ON ON X
1 ON ON OFF X
2 ON OFF ON X
3 OFF OFF OFF X
4 OFF ON ON X
5 OFF ON OFF X
X: irrelevant
The factory setting selects comport 3 to configure the FPGA.
At power up the FPGA is not configured.
LED D1 will be lit upon FPGA configuration.

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Reset
The SMT351 is reset by the TIM global reset.
There is also a TIM CONFIG signal provided on the TIM connector J4 pin 74. This
provides a means of reprogramming the FPGA without having to drive the TIM Global
Reset signal. CONFIG falling will reset the SMT351 in the same way that a TIM
global Reset pulse will. Other modules in the system that are sensitive to the TIM
global Reset signal will not be affected by CONFIG.
CONFIG is driven from another TIM site on the carrier board, for instance, from a
DSP module running an application. (See General Firmware Description for
information on the DSP TIM CONFIG signal).
After a Global Reset pulse, a DSP module drives CONFIG low and keeps it low by
default.
Setting SW1 switch number 2 will enable or disable TIM CONFIG:
Table 3: TIM CONFIG feature: SW1 settings
TIM CONFIG Switch
number 4
Enabled ON
Disabled OFF
Once a DSP application has been loaded, CONFIG can be driven the following way:
#include “SMT3xx.h”
#define CONFIG_BIT (1<<6)
int main()
{
*CONFIG &= (UINT32)~CONFIG_BIT;
timer_delay (100);
*CONFIG |= CONFIG_BIT;
timer_delay (100);
}

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Functional description
FPGA design overview
The following diagram shows the data path of SMT351:
SHB
A
SHB
B
Memory bank 0
Memory bank 1
Mux
400
MBytes/
sec
400
MBytes/
sec
Registers
Com
port
Control
words
Figure 2: SMT351 FPGA data flow.
Data input on SHB A are stored into memory and then sent to SHB B.
Memory is organised in two independent banks: bank 0 and bank 1.
Both banks are accessed at the same time so that data can be stored in one bank
while data are being read back from the other.
This mechanism allows a maximum data rate of 400MB/s.
Memory banks
This section describes the details of the memory banks.
The following diagram shows how the DDR SDRAM components are organized
within a memory bank:

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DDR SDRAM
32 Meg x 16 bits
16-bits data bus
DDR SDRAM
32 Meg x 16 bits
16-bits data bus
4x
components
4x
components
32-bits data bus
Chip Enable 3
Chip Enable 2
Chip Enable 1
Chip Enable 0
Figure 3: DDR SDRAM components bank organization.
One bank is made from eight 32M x 16-bits DDR SDRAM components, each of them
having a 16-bit data bus. Memory components are accessed in pairs.
Sundance High Speed Bus (SHB)
Data are input and output from SMT351 using the SHB protocol. See SUNDANCE
SHB specification for more details.
The SHB interfaces implemented in SMT351 are unidirectional full word (32-bits).
SHB A is a receiver-only interface and SHB B is a transmitter-only interface; both are
clocked at 100 MHz, giving a maximum data rate of 400 MB/s.
Registers
Command words can be sent over comport 3 to control the SMT351. Words received
will be written into registers in the FPGA. See Register definition section for more
details.

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Clock structure
This section describes the various clock domains in the FPGA.
The figure below shows the four clock domains of the SMT351 design and their
interrelation.
SHB
A
SHB
B
Memory bank 0
Memory bank 1
Mux
400
MBytes/
sec
400
MBytes/
sec
Registers
Com
port
Control
words
Input
buffer
Output
buffer
Input clock
domain
DDR SDRAM
clock domain
Output clock
domain
Figure 4: FPGA’s clock domains
Table 4: FPGA’s clock domains description
Clock domain Colour Frequency Description
ComPort 50 MHz Comport and registers clock
Data input < 100 MHz SHB A clock.
Data output 100 MHz SHB B clock.
DDR SDRAM 100 MHz DDR SDRAM clock.

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FPGA implementation
This section gives some technical details about the FPGA firmware.
Language
Sundance uses Aldec Active-HDL tool for the design entry and the simulation.
The FPGA is fully designed in VHDL.
Synthesis and Implementation tool
The design is implemented using Xilinx ISE 6.1 SP3 and synthesized with XST.
FPGA resource usage
Follow is the device utilization summary after Place and Route:
Resource XC2VP7
Number of
External IOBs
68% (272 / 396)
Number of
RAMB16s
27% (12 / 44)
Number of
SLICEs
56% (2784 / 4928)
Number of
BUFGMUXs
68% (11 / 16)
Number of
DCMs
100% (4 / 4)
Power PC 0% (1 / 1)

Register definition
FPGA reset register (0x00)
Writing to this address will reset the DDR SDRAM memory control. You must wait
one second after writing to this register to allow the reset to complete.
Control register (0x02)
15 14-5 4 3 2 1 0
LED - START
ACQ
- - RDBK
EN
CLR
SHB
R/W, 0 - R/W, 0 - - W,1 R/W,0
Field Description (flags are active when 1)
CLR Writing ‘1’ to this register will reset both input and output SHBs.
RDBKEN Read back enable. When this bit is set read back of memory is
enabled and SMT351 starts outputting data.
STARTACQ When this bit is set to 1, data coming from SHB A are stored in DDR
SDRAM.
LED LED register. Writing ‘1’ to this register will light LED 4.

Software
SMT351 comes with a software package that provides basic functions for using the
board. The library is called Smt351.lib.
SMT351_Config
Definition
Load a bitstream into the SMT351’s FPGA.
Prototype
void SMT351_Config (int Cp, const char *Bitstream)
Parameters
Cp: Number of the comport used to configure the SMT351
Bitstream: pointer to the bitstream file name
SMT351_Capture
Definition
Triggers capture of data into the SMT351 memory.
Prototype
void SMT351_Capture (int Cp, int Words)
Parameters
Cp: Number of the comport used to communicate with the SMT351
Words: number of 32-bis words to capture.
SMT351_PlayBack
Definition
Triggers playback of data previously stored in SMT351 memory.
Prototype
void SMT351_Playback (int Cp)
Parameters
Cp: Number of the comport used to communicate with the SMT351

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Connector Locations
Figure 5: SMT351 connector locations