Sundance Spas SMT398 User manual

SMT398
User Manual

Version 1.1.1 Page 2 of 38 SMT398 User Manual
Revision History
Date Comments Engineer Version
18.07.03 First released version E.P 1.0.0
22.08.03 TIM CONFIG signal feature described E.P 1.1.0
27.08.03 Minor corrections E.P 1.1.1

Version 1.1.1 Page 3 of 38 SMT398 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Table of Figures.......................................................................................................... 5
Table of Tables........................................................................................................... 5
Physical Properties..................................................................................................... 6
Introduction................................................................................................................. 7
Related Documents ................................................................................................ 7
Block Diagram ............................................................................................................ 7
Mechanical Interface: TIM Standard........................................................................... 8
SMT398 Installation.................................................................................................... 8
SMT398 Alone ........................................................................................................ 8
SMT398 + DSP TIM................................................................................................ 9
FPGA Configuration ................................................................................................. 10
Electrical Interface .................................................................................................... 10
The service CPLD................................................................................................. 10
CPLD Functions ................................................................................................ 11
Virtex II Bitstream Format.................................................................................. 14
Bitstream Re-formatting..................................................................................... 15
CPLD code versions.......................................................................................... 15
FPGA .................................................................................................................... 15
FPGA in system programming .......................................................................... 17
JTAG/Boundary Scan........................................................................................ 18
Configuring with MultiLINX ................................................................................ 19
FPGA Readback and Partial reconfiguration..................................................... 19
Memory................................................................................................................. 20
Pipelined ZBTRAM............................................................................................ 20
QDR (Quad Data Rate) ..................................................................................... 21
ComPorts .............................................................................................................. 23
SHB ...................................................................................................................... 24
SHB Connector ................................................................................................. 24
SHB Cable Assembly ........................................................................................ 25

Version 1.1.1 Page 4 of 38 SMT398 User Manual
SHB Inter Modules solutions ............................................................................. 25
SHB 16-bit Interface .......................................................................................... 25
Global bus............................................................................................................. 26
Clocks ................................................................................................................... 26
Power Supplies ..................................................................................................... 27
DC/DC Converter .............................................................................................. 28
Linear Voltage regulator .................................................................................... 28
Fan .................................................................................................................... 28
Power Consumption.............................................................................................. 28
Verification Procedures ............................................................................................ 29
Review Procedures .................................................................................................. 29
Validation Procedures .............................................................................................. 29
Circuit Diagrams ....................................................................................................... 29
Ordering information:................................................................................................ 29
Full configuration................................................................................................... 30
Basic configuration................................................................................................ 31
Memories........................................................................................................... 31
SHBs ................................................................................................................. 31
ComPorts .......................................................................................................... 31
Global Bus......................................................................................................... 31
External Clock ................................................................................................... 31
PCB Layout Details .................................................................................................. 32
Components placement ........................................................................................ 32
Headers Pinout......................................................................................................... 34
SHB Header.......................................................................................................... 34
SHB Pinout (LVTTL only).(J8-J9-J10-11) .......................................................... 35
JTAG/Multilinx headers ......................................................................................... 36
JTAG/Boundary scan pinout (J13) .................................................................... 36
MultiLINX SelectMap Pin Descriptions (J12-J13) .............................................. 37
Safety ....................................................................................................................... 38
EMC ......................................................................................................................... 38

Version 1.1.1 Page 5 of 38 SMT398 User Manual
Table of Figures
Figure 1:SMT398 Block Diagram .............................................................................................7
Figure 2: FPGA configuration in SelectMap mode using CPLD.............................................11
Figure 3: ComPort word Byte order........................................................................................12
Figure 4: V II Configuration Bitstream Word Format ..............................................................15
Figure 5: JTAG Chain on the SMT398 ...................................................................................18
Figure 6:SMT398 ZBT Memory Banks arrangement .............................................................21
Figure 7:SMT398 QDR Width expansion arrangement..........................................................22
Figure 8:SMT398 ComPorts connections ..............................................................................23
Figure 9: DC/DC converter dimensions (in inches) ................................................................28
Figure 10:SMT398 Components placement-Top view ...........................................................32
Figure 11: SMT398 Components placement-Bottom view.....................................................33
Figure 12: Top View QSH 30 .................................................................................................34
Figure 13: Top View of JTAG/Multilinx headers .....................................................................36
Table of Tables
Table 1: FPGA Choices..........................................................................................................16
Table 2: ZBTRAM sizes .........................................................................................................20
Table 3: QDR RAM sizes .......................................................................................................22
Table 4: External clock specification ......................................................................................26
Table 5: powering the devices................................................................................................27
Table 6: Virtex II, ZBT/QDR combinations in FULL configuration ..........................................30
Table 7: Virtex II, ZBT combinations in BASIC configuration .................................................31
Table 8: SHB interfaces table.................................................................................................35
Table 9: Connector J13-JTAG Header...................................................................................36
Table 10: Connector J13-Flying Lead Set #1.........................................................................37
Table 11: Connector J12 Flying Lead Sets 3&4.....................................................................38

Version 1.1.1 Page 6 of 38 SMT398 User Manual
Physical Properties
Dimensions See Physical specifications of TI TIM specification &
user’s guide
Weight Varies in function of board configuration
Supply Voltages See Power Supplies
Supply Current See Power Supplies

Version 1.1.1 Page 7 of 38 SMT398 User Manual
Introduction
Related Documents
SUNDANCE SHB specification
Sundance SDB specification.
TI TIM specification & user’s guide.
Samtec QSH Catalogue page
Block Diagram
Sundance Digital Bus
or Sundance High-speed Bus
connector x4
2x Comm-Ports/SDL
24 I/O pins
Interrupts&Reset
5 I/O pins
4x Comm-Port/SDL
48 I/O pins
Global Bus
78 I/O pins
183 I/O pins; 16-bit data
FPGA
Virtex-II FF896/1152
XC2V1000 - XC2V8000
432 to 824 I/O Pins
1.5V Core
1.5V/3.3V I/O
2,4,8 or 16Mbytes ZBT-
RAM as SMT358
Xilinx XC95288 CS280 CPLD
on Comm-Port #0 and #3
and Config&Timer&control
JTAG Header
SelectMAP Header
J1 Top Primary TIM
Connector
Comm-Port 0 & 3
J3 Global Expansion
Connector
J2 Bottom Primary TIM
Connector
4xComm-Port/SDL 1;2;4 & 5
On-board
Oscillator
4 LEDs or
4 I/O pins
External Clock
120 I/O pins; 16-bit data 2, 4 Mbytes QDR-SRAM
2x (1 or 2Mx18)
16 I/O pins
240 I/O Pins
Clk
Figure 1:SMT398 Block Diagram

Version 1.1.1 Page 8 of 38 SMT398 User Manual
Mechanical Interface: TIM Standard
This module conforms to the TIM standard (Texas Instrument Module, See TI TIM
specification & user’s guide.) for single width modules.
It sits on a carrier board.
The carrier board provides power, Ground, communication links (ComPort links)
between all the modules fitted and a pathway to the host, for a non stand-alone
system.
The SMT398 requires an additional 3.3V power supply (as present on all Sundance
TIM carrier boards) which must be provided by the two diagonally opposite mounting
holes.
SMT398 Installation
Two types of configuration are described here, nevertheless, you shouldn’t be
restricted and should consult Sundance if your system architecture differs.
SMT398 Alone
You can fit the SMT398 on its own, on the first TIM site of one of Sundance’s 3.3v
compatible carrier boards plugged in a host computer (PC, PCI, VME carrier etc…),
like SMT310Q, SMT328, SMT300 etc…)
Please, follow these steps to install the SMT398 module on a Host system:
1. Remove the carrier board from the host system.
2. Place the SMT398 module on the first TIM site. This TIM site communicates
with the host. (See your carrier board User Manual.) This allows you to use
Global Bus and ComPort 3 to communicate with the host.
3. Make sure that the board is firmly seated, and then provide the 3.3V to the
board by screwing the SMT398 on the two main mounting holes with the bolts
and screws provided with the board.
4. Connect the SHB links if required by your application.
5. Replace the carrier board in the host system or power on for a stand-alone
carrier.
Do NOT connect any external TTL (5v) signals to the SMT398 I/Os as the FPGA
is NOT 5v compliant. This implies that the ComPorts and global bus lines of
the carrier board MUST be LVTTL and that any device driving signals on the
SHB connectors must drive at LVTTL (3.3v).

Version 1.1.1 Page 9 of 38 SMT398 User Manual
SMT398 + DSP TIM
You can fit the SMT398 coupled with a DSP module on any of Sundance carrier
boards: Stand alones or plugged in a Host.
The DSP module can then be used to provide the SMT398 FPGA configuration
bistream and to communicate with the host.
Please, follow these steps to install the SMT398 module and the DSP TIM on a
carrier:
1. Remove the carrier board from the host system or turn the power off for a stand-
alone carrier.
2. Place the SMT398 module onto one of the TIM sites on the carrier board.
• Preferably, fit the DSP TIM on the first TIM site. This TIM site
communicates with the host. (See your carrier board User Manual.).
This allows the processor board to handle the interactions with the Host
by software instead of having to implement a communication interface
in the SMT398 FPGA. (Global Bus interface or ComPort interface on
ComPort 3).
• Fit the ComPort communication links between the DSP TIM and the
SMT398 respecting the rules on polarity at reset. (See your carrier
board User Manual.)
• To configure the SMT398 FPGA using the DSP TIM, then you need a
link between the 2 modules: ComPort 3 of the SMT398 MUST be
connected to one of the transmit ComPort at Reset(ComPort 0,1 or 2)
available on the DSP TIM.
3. Make sure that the board is firmly seated, and then provide the 3.3V to the board
by screwing the SMT398 on the two main mounting holes with the bolts and
screws provided with the board.
4. Connect the SHB links if required by your application.
5. Replace the carrier board in the host system or power on for a stand-alone
carrier.

Version 1.1.1 Page 10 of 38 SMT398 User Manual
FPGA Configuration
The FPGA can be configured 2 different ways:
• Using ComPort 3 to provide the bitstream. (See The service CPLD)
• Using the on-board JTAG header and Xilinx JTAG programming tools. (See
FPGA in system programming)
•
Electrical Interface
The service CPLD
The CPLD allows for FPGA configuration in slave SelectMap mode.
The CPLD is connected to ComPort number 3 of the SMT398 TIM connector.
Consequently, the ComPort on the other end of the link must be configured as
transmitter at power-up or after reset, i.e. ComPort channels 0, 1, or 2.
The typical SMT398 user does not need an in depth understanding of the
configuration sequence and of the Virtex II. However, for the purpose of debugging
and designing for the SMT398 an overview of the necessary configuration protocol
and bitstream formatting is recommended.
Therefore, this section describes the CPLD functions, the Virtex II bitstream format
and the necessary bitstream re-formatting when downloading the bitstream to the
FPGA via CPLD + ComPort 3.
Figure 2: FPGA configuration in SelectMap mode using CPLD provides waveforms to
illustrate the descriptions below.
At power up the FPGA is not configured.
LED L5 (See Figure 10:SMT398 Components placement-Top view, bottom right
hand corner of the picture) will be lit upon FPGA configuration.
At power up or after a Reset of the SMT398, the CPLD is configured and
implements a ComPort link receiver on ComPort 3.

Version 1.1.1 Page 11 of 38 SMT398 User Manual
Figure 2: FPGA configuration in SelectMap mode using CPLD
CPLD Functions
• Decode Commands coming on ComPort 3.
• To Implement a ComPort Receiver on ComPort 3 after Reset or at Power up.
• Configure FPGA.
• Reset FPGA.

Version 1.1.1 Page 12 of 38 SMT398 User Manual
Decode Commands
At power up, after a TIM global Reset, or once the FPGA configuration process is
over, the CPLD reads any word coming on its ComPort.
If a received word cannot be recognized as a command, the word is read completely
but ignored. The CPLD recognizes the following two commands:
• STARTKEY
• ENDKEY
ComPort Receiver
At power up or after a TIM global Reset, the CPLD takes control of ComPort 3.
Once the ENDKEY command is received, the CPLD releases ComPort 3.
The ComPort communication is performed in 32-bit words, where each word consists
of four consecutive bytes. The ComPort protocol transmits words starting with the
least-significant byte (LSByte), i.e. byte0, as shown in Figure 3: ComPort word Byte
order, and 1 byte at a time.
Byte3 Byte2 Byte1 Byte0
31 24 23 16 15 8 7 0
D31 D30 D29 D28 D27D26 D25 D24D23D22D21D20D19D18 D17 D16 D15 D14D13 D12D11D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3: ComPort word Byte order
Configure FPGA
The signals INITn and DONE are CPLD inputs, the other one are CPLD outputs that
the CPLD drives to configure the FPGA.
On reception of the STARTKEY command the CPLD clears the FPGA configuration
memory by asserting the PROGRAMn pin low. On INITn going low, the CPLD brings
PROGRAMn high and waits for INITn to come back high before starting the FPGA
configuration.
Afterwards, the CPLD asserts CSn and WRITEn low for the rest of the configuration
process.
The CPLD pulses high CCLK to loads in the FPGA any new byte present on the
ComPort by.

Version 1.1.1 Page 13 of 38 SMT398 User Manual
The CPLD does not implement any operation on the bitstream and passes it straight
through to the FPGA once the STARTKEY has been decoded and until the ENDKEY
is decoded.
Once the FPGA DONE pin has gone high, LED L5 (See Figure 10:SMT398
Components placement-Top view, bottom right hand corner of the picture) becomes
on, indicating that the FPGA configured.
The CPLD disables the SelectMap interface and waits for the ENDKEY command on
ComPort3.
Once the ENDKEY command is received, the CPLD releases ComPort 3.
Reset Control
TIM Global Reset
The CPLD is connected to a TIM global Reset signal provided to the SMT398 via its
TIM connector J4 pin 30. (See Figure 10:SMT398 Components placement-Top view).
The TIM global Reset signal is also available for the FPGA but the CPLD provides
another signal called FPGAResetn that offers a better Reset control over the FPGA.
At power up or on reception of a low TIM global Reset pulse, the CPLD drives the
FPGAResetn signal low and keeps it low.
When the ENDKEY has been received, the CPLD drives FPGAResetn high.
I recommend that you use FPGAResetn for the Global Reset signal of your FPGA
designs.
In this manner, you can control your FPGA design Reset activity and you will also
avoid possible conflicts on ComPort 3 if your FPGA design implements it.
TIM CONFIG
On The CPLD is connected a TIM CONFIG signal provided to the SMT398 via its
TIM connector J4 pin 74. (See Figure 10:SMT398 Components placement-Top view
and Figure 8:SMT398 ComPorts connections).
CONFIG falling has the same effect on the SMT398 CPLD as a TIM global Reset
pulse.
On detection of a falling edge on the CONFIG line, the CPLD drives the FPGAResetn
signal low and keeps it low.
CONFIG provides a means of reprogramming the FPGA without having to drive the
TIM Global Reset signal.
Therefore any other modules sensitive to the TIM global Reset signal will not be
affected and can keep running their application.

Version 1.1.1 Page 14 of 38 SMT398 User Manual
CONFIG is driven from another TIM site on the carrier board, for instance, from a
DSP module running an application. (See General Firmware Description for
information on the DSP TIM CONFIG signal.)
After a Global Reset pulse, a DSP module drives CONFIG low and keeps it low by
default.
After Reset and loading of the DSP application, CONFIG can be driven the following
way:
#include “SMT3xx.h”
#define CONFIG_BIT 1<<6
int main()
{
*CONFIG |= CONFIG_BIT; //tristates CONFIG (Pull-ups on the carrier board pull CONFIG high)
*CONFIG &= (UINT32)~CONFIG_BIT;//CONFIG is driven low
//delay while the FPGA is configured
*CONFIG |= CONFIG_BIT;
}
This feature can be interesting in systems where:
• The FPGA needs to implement multiple functions spread in different
bitstreams that are needed at different stages of the application.
• The system needs to keep running and can’t be interrupted by a global Reset
pulse when the FPGA needs to be configured with a new bitstream.
Notes:
• TIM CONFIG is only available on SMT398 v3. The SMT398 version is written
on TOP of the board (See Figure 10:SMT398 Components placement-Top
view).
• TIM CONFIG needs CPLD code version 2.1 or above (Written on a sticker on
the CPLD. (See Figure 10:SMT398 Components placement-Top view).
• The ComPort3 is reserved for the CPLD and cannot be made available to the
FPGA.
• CONFIG needs switch SW1 position 8 to be ON. (See Figure 11: SMT398
Components placement-Bottom view)
Virtex II Bitstream Format
The Virtex II SelectMap interface is an 8-bit interface on the device with data pins
labeled D[7:0]. The configuration bitstreams can be written eight bits per clock cycle.
The Virtex II configuration bitstreams generated by BitGen (.bit files) contain a mix of
commands and data on 32 bit word boundaries, shown in Xilinx application note 138
page 20. This format assumes D0 is considered the MSBit as shown Figure 4: V II
Configuration Bitstream Word Format.

Version 1.1.1 Page 15 of 38 SMT398 User Manual
Byte0 Byte1 Byte2 Byte3
31 24 23 16 15 8 7 0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27D28 D29 D30 D31
Figure 4: V II Configuration Bitstream Word Format
As a result, to be able to download the bitstream to the FPGA using ComPort3 +
CPLD, the Virtex II configuration bitstream must be re-formatted to match the
ComPort word standard.
Bitstream Re-formatting
The re-formatting consists in inverting the bits in a byte and the bytes in a 32-bit
word.
Further, the .bit files contain a header section before the pad word and
synchronization word. The download function FPGAFullConfiguration() from the
SMT6500 package searches for the synchronization sequence and skips the header.
CPLD code versions
• V1.0: Initial release that only receives the bitstream and configures the FPGA.
FPGAResetn is NOT implemented and ComPort 3 is NOT released once the
FPGA is configured.
• V2.0 Indicated on a sticker on the CPLD. The CPLD implements the functions
described above except TIM CONFIG.
• V2.1 Indicated on a sticker on the CPLD. V2.0 + the CPLD implements the
reconfiguration feature described in TIM CONFIG.
FPGA
The module can be fitted with a XC2V1000, XC2V1500, XC2V2000, XC2V3000,
XC2V4000, XC2V6000 or XC2V8000.
The FPGA comes in two pinout/footprint compatible packages: flip-chip FF896 and
FF1152.
The choice of FPGA will be price/performance driven. The following table shows the
main FPGA characteristics.
The choice of the FPGA also determines which board architecture you will get
(amount of logic available, speed, number and type of I/Os, on-board Memory size
and type). For a complete list of the different board architectures, please consult: 0
Ordering information:

Version 1.1.1 Page 16 of 38 SMT398 User Manual
This Xilinx Virtex II, is responsible for the provision of up to 4 SHBs, up to 6
ComPorts, the global bus and QDR/ZBT memory banks (In FULL configuration, see
0 Ordering information:)
CLB(1 CLB = 4 slices = Max 128
bits) SelectRAM Blocks
Device Syste
m
gates Array
Row x
Col
Slices
Maximum
distribute
d RAM
Kbits
Multiplie
r
blocks
18-Kbit
Block
Max RAM
(Kbits)
DCM
s
XC2V1000 1M 40x32 5,120 160 40 40 720 8
XC2V1500 1.5M 48x40 7,680 240 48 48 864 8
XC2V2000 2M 56x48 10,752 336 56 56 1,008 8
XC2V3000 3M 64x56 14,336 448 96 96 1,728 12
XC2V4000 4M 80x72 23,040 720 120 120 2,160 12
XC2V6000 6M 96x88 33,792 1,056 144 144 2,592 12
XC2V8000 8M 112x104 46,592 1,456 168 168 3,024 12
Table 1: FPGA Choices
The Xilinx FPGA is configured from one of several modes:
 Slave SelectMAP.
 JTAG/Boundary scan
And from one of several sources:
 ComPort 3 (Using Slave SelectMAP)
 Parallel cable III-IV (Using JTAG)
 MultiLINX cable. (Using JTAG or Slave SelectMAP)
At power up the FPGA is not configured.
LED L5 (See Figure 10:SMT398 Components placement-Top view, bottom right
hand corner of the picture) will be lit upon FPGA configuration.

Version 1.1.1 Page 17 of 38 SMT398 User Manual
FPGA in system programming
The factory default for the FPGA configuration mode is using Slave SelectMAP mode
and the ComPort3.
Configuring the FPGA from ComPort 3 allows NOT USING any JTAG cables.
Having a direct link enhances debugging and testing, and therefore reduces the
product’s time to market.
Once the design is complete, the configuration data can be stored on disk and then
loaded each time the system powers up or is reset. The configuration cycle can be
transparent to the end user.
The bitstream is presented on Commport3 and the CPLD provides the mechanism to
deliver it quickly to the Virtex-II device using the Slave SelectMAP mode.
After configuration the Commport3 can be available to the FPGA for data transfers if
the Virtex II is XC2V3000 or above and if your CPLD design version allows it.
SMT398 Alone
Host software can be developed to communicate with the SMT398.
See SMT6025 User Manual on Sundance Web site for more information on how to
develop Host applications for Sundance Hardware.
The host Software application BitstreamLd.exe provided is compiled for Windows
NT/2000.
It allows downloading a bitstream to the SMT398 FPGA.
SMT398 + DSP TIM
The DSP software routines provided are the download functions LoadBitstream() and
FPGAFullConfiguration().
• LoadBitstream():This function reads a bit file from your local HD and stores it
on the DSP board.
• FPGAFullConfiguration(): The FPGA is configured with data from a .bit file
stored on your DSP board.
This code can be recompiled for any C6x-processor-board you want to use under
Code Composer Studio and/or 3L Diamond.
• Bit2Asm.exe. This stand alone executable formats a bit file into a Texas
instrument’s asm file. Then you can embed it in your application’s object file at
linking time. As a result, the FPGA bitstream is downloaded with the
application into the DSP module’s memory which provides a faster FPGA
configuration process than the standard way.

Version 1.1.1 Page 18 of 38 SMT398 User Manual
JTAG/Boundary Scan
JTAG Programmer (iMPACT)
The JTAG Programmer software is a standard feature of the Alliance Series ™ and
Foundation Series ™ software packages. JTAG Programmer is a part of Web Pack,
which can be downloaded from the following site:
Xilinx JTAG programmer
 Configuring with the parallel cable III or IV
The JTAG chain is composed of the CPLD and the FPGA.
The CPLD is pre-programmed by Sundance.
Do NOT try to reprogram the CPLD without SUNDANCE approval
Figure 5: JTAG Chain on the SMT398
When accessing the board using JTAG, the CPLD can be bypassed and you can
configure the FPGA only.
Xilinx describe how to connect both download cables at: Parallel cables
Xilinx describe how to configure their devices using these cables at: Configuration
Mode General Information.
For complementary and more detailed information please go to: Xilinx 5 software
Manuals and Help.
See board header pinout in Table 9: Connector J13-JTAG Header

Version 1.1.1 Page 19 of 38 SMT398 User Manual
Configuring with MultiLINX
The Mutilinx cable can be used to configure the FPGA via JTAG or SelectMap mode.
See board header pinout in Table 9: Connector J13-JTAG Header, Table 10:
Connector J13-Flying Lead Set #1 and Table 11: Connector J12 Flying Lead Sets
3&4.
The MultiLINX cable set is a peripheral hardware product from Xilinx.
For additional information on the MultiLINX cable set, go to the following site:
Xilinx MultiLINX cable
FPGA Readback and Partial reconfiguration
Using Comm-port3
Readback and partial reconfiguration are enabled by a specific design for the CPLD,
not provided as a standard feature of the CPLD but that can be purchased from
Sundance. Contrary to the original design, the CPLD is dedicated to control the
FPGA and does not provide a communication channel to user logic residing on the
FPGA anymore. The CPLD is connected to ComPort number 3 of the SMT398
connector, which cannot be used anymore by the FPGA to transfer data.
Therefore, the CPLD controller can configure, readback, partially reconfigure the
Virtex II and capture.
Using MultiLINX /Parallel cable III or IV
The JTAG and the MultiLINX SelectMAP headers are also provided to enable
application debugging via suitable software. Typically, this will be Xilinx ChipScope
ILA (Integrated Logic Analyzer).
The ChipScope Analyzer supports both the Xilinx MultiLINX™ and Parallel Cable III
download cables for communication between the PC and FPGA(s). The MultiLINX
cable supports both USB (Windows 98 and Windows 2000) and RS-232 serial
communication from the PC. The Parallel Cable III supports only parallel port
communication from the PC to the Boundary Scan chain.

Version 1.1.1 Page 20 of 38 SMT398 User Manual
Memory
Pipelined ZBTRAM
Up to 16Mbytes of pipeline ZBT memory is provided with direct access by the FPGA.
The ZBTRAM is designed to sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice versa.
This device is well suited for SDR applications that experience frequent bus
turnarounds, need to operate on small data chunks (especially one-word chunks),
and need to operate at higher frequencies than permitted by the flow-through
version.
The memory is split into 4 independent 16-bit-wide Banks.
All three chip enables are available on each bank for simple depth expansion with no
data contention.
Each bank is composed of one chip, available in 4 different sizes as presented in
Table 2: ZBTRAM sizes:
For more complete information, please read:
General Information on how to choose your memory type according to your
application
For the parts datasheet, please read:
ZBTRAM datasheets
Chips parts and densities are shown in the table below.
ZBTRAM part
number
Size in
bits
Size in
Bytes
Actual
Memory
size
Amount
of
memory
per board
K7N401801A 4Mb 512kBytes 256kx18 2 MBytes
K7N801801M 8Mb 1MBytes 512kx18 4 MBytes
K7N161801A 16Mb 2MBytes 1Mx18 8 MBytes
K7N321801M 32Mb 4MBytes 2Mx18 16
MBytes
Table 2: ZBTRAM sizes
The total available ZBT RAM on the board is therefore 2 MBytes, 4 MBytes, 8
MBytes, or 16 MBytes