Sundance Spas SMT398 User manual

SMT398
User Manual

Version 1.1.1 Page 2 of 38 SMT398 User Manual
Revision History
Date Comments Engineer Version
18.07.03 First released version E.P 1.0.0
22.08.03 TIM CONFIG signal feature described E.P 1.1.0
27.08.03 Minor corrections E.P 1.1.1

Version 1.1.1 Page 3 of 38 SMT398 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Table of Figures.......................................................................................................... 5
Table of Tables........................................................................................................... 5
Physical Properties..................................................................................................... 6
Introduction................................................................................................................. 7
Related Documents ................................................................................................ 7
Block Diagram ............................................................................................................ 7
Mechanical Interface: TIM Standard........................................................................... 8
SMT398 Installation.................................................................................................... 8
SMT398 Alone ........................................................................................................ 8
SMT398 + DSP TIM................................................................................................ 9
FPGA Configuration ................................................................................................. 10
Electrical Interface .................................................................................................... 10
The service CPLD................................................................................................. 10
CPLD Functions ................................................................................................ 11
Virtex II Bitstream Format.................................................................................. 14
Bitstream Re-formatting..................................................................................... 15
CPLD code versions.......................................................................................... 15
FPGA .................................................................................................................... 15
FPGA in system programming .......................................................................... 17
JTAG/Boundary Scan........................................................................................ 18
Configuring with MultiLINX ................................................................................ 19
FPGA Readback and Partial reconfiguration..................................................... 19
Memory................................................................................................................. 20
Pipelined ZBTRAM............................................................................................ 20
QDR (Quad Data Rate) ..................................................................................... 21
ComPorts .............................................................................................................. 23
SHB ...................................................................................................................... 24
SHB Connector ................................................................................................. 24
SHB Cable Assembly ........................................................................................ 25

Version 1.1.1 Page 4 of 38 SMT398 User Manual
SHB Inter Modules solutions ............................................................................. 25
SHB 16-bit Interface .......................................................................................... 25
Global bus............................................................................................................. 26
Clocks ................................................................................................................... 26
Power Supplies ..................................................................................................... 27
DC/DC Converter .............................................................................................. 28
Linear Voltage regulator .................................................................................... 28
Fan .................................................................................................................... 28
Power Consumption.............................................................................................. 28
Verification Procedures ............................................................................................ 29
Review Procedures .................................................................................................. 29
Validation Procedures .............................................................................................. 29
Circuit Diagrams ....................................................................................................... 29
Ordering information:................................................................................................ 29
Full configuration................................................................................................... 30
Basic configuration................................................................................................ 31
Memories........................................................................................................... 31
SHBs ................................................................................................................. 31
ComPorts .......................................................................................................... 31
Global Bus......................................................................................................... 31
External Clock ................................................................................................... 31
PCB Layout Details .................................................................................................. 32
Components placement ........................................................................................ 32
Headers Pinout......................................................................................................... 34
SHB Header.......................................................................................................... 34
SHB Pinout (LVTTL only).(J8-J9-J10-11) .......................................................... 35
JTAG/Multilinx headers ......................................................................................... 36
JTAG/Boundary scan pinout (J13) .................................................................... 36
MultiLINX SelectMap Pin Descriptions (J12-J13) .............................................. 37
Safety ....................................................................................................................... 38
EMC ......................................................................................................................... 38

Version 1.1.1 Page 5 of 38 SMT398 User Manual
Table of Figures
Figure 1:SMT398 Block Diagram .............................................................................................7
Figure 2: FPGA configuration in SelectMap mode using CPLD.............................................11
Figure 3: ComPort word Byte order........................................................................................12
Figure 4: V II Configuration Bitstream Word Format ..............................................................15
Figure 5: JTAG Chain on the SMT398 ...................................................................................18
Figure 6:SMT398 ZBT Memory Banks arrangement .............................................................21
Figure 7:SMT398 QDR Width expansion arrangement..........................................................22
Figure 8:SMT398 ComPorts connections ..............................................................................23
Figure 9: DC/DC converter dimensions (in inches) ................................................................28
Figure 10:SMT398 Components placement-Top view ...........................................................32
Figure 11: SMT398 Components placement-Bottom view.....................................................33
Figure 12: Top View QSH 30 .................................................................................................34
Figure 13: Top View of JTAG/Multilinx headers .....................................................................36
Table of Tables
Table 1: FPGA Choices..........................................................................................................16
Table 2: ZBTRAM sizes .........................................................................................................20
Table 3: QDR RAM sizes .......................................................................................................22
Table 4: External clock specification ......................................................................................26
Table 5: powering the devices................................................................................................27
Table 6: Virtex II, ZBT/QDR combinations in FULL configuration ..........................................30
Table 7: Virtex II, ZBT combinations in BASIC configuration .................................................31
Table 8: SHB interfaces table.................................................................................................35
Table 9: Connector J13-JTAG Header...................................................................................36
Table 10: Connector J13-Flying Lead Set #1.........................................................................37
Table 11: Connector J12 Flying Lead Sets 3&4.....................................................................38

Version 1.1.1 Page 6 of 38 SMT398 User Manual
Physical Properties
Dimensions See Physical specifications of TI TIM specification &
user’s guide
Weight Varies in function of board configuration
Supply Voltages See Power Supplies
Supply Current See Power Supplies

Version 1.1.1 Page 7 of 38 SMT398 User Manual
Introduction
Related Documents
SUNDANCE SHB specification
Sundance SDB specification.
TI TIM specification & user’s guide.
Samtec QSH Catalogue page
Block Diagram
Sundance Digital Bus
or Sundance High-speed Bus
connector x4
2x Comm-Ports/SDL
24 I/O pins
Interrupts&Reset
5 I/O pins
4x Comm-Port/SDL
48 I/O pins
Global Bus
78 I/O pins
183 I/O pins; 16-bit data
FPGA
Virtex-II FF896/1152
XC2V1000 - XC2V8000
432 to 824 I/O Pins
1.5V Core
1.5V/3.3V I/O
2,4,8 or 16Mbytes ZBT-
RAM as SMT358
Xilinx XC95288 CS280 CPLD
on Comm-Port #0 and #3
and Config&Timer&control
JTAG Header
SelectMAP Header
J1 Top Primary TIM
Connector
Comm-Port 0 & 3
J3 Global Expansion
Connector
J2 Bottom Primary TIM
Connector
4xComm-Port/SDL 1;2;4 & 5
On-board
Oscillator
4 LEDs or
4 I/O pins
External Clock
120 I/O pins; 16-bit data 2, 4 Mbytes QDR-SRAM
2x (1 or 2Mx18)
16 I/O pins
240 I/O Pins
Clk
Figure 1:SMT398 Block Diagram

Version 1.1.1 Page 8 of 38 SMT398 User Manual
Mechanical Interface: TIM Standard
This module conforms to the TIM standard (Texas Instrument Module, See TI TIM
specification & user’s guide.) for single width modules.
It sits on a carrier board.
The carrier board provides power, Ground, communication links (ComPort links)
between all the modules fitted and a pathway to the host, for a non stand-alone
system.
The SMT398 requires an additional 3.3V power supply (as present on all Sundance
TIM carrier boards) which must be provided by the two diagonally opposite mounting
holes.
SMT398 Installation
Two types of configuration are described here, nevertheless, you shouldn’t be
restricted and should consult Sundance if your system architecture differs.
SMT398 Alone
You can fit the SMT398 on its own, on the first TIM site of one of Sundance’s 3.3v
compatible carrier boards plugged in a host computer (PC, PCI, VME carrier etc…),
like SMT310Q, SMT328, SMT300 etc…)
Please, follow these steps to install the SMT398 module on a Host system:
1. Remove the carrier board from the host system.
2. Place the SMT398 module on the first TIM site. This TIM site communicates
with the host. (See your carrier board User Manual.) This allows you to use
Global Bus and ComPort 3 to communicate with the host.
3. Make sure that the board is firmly seated, and then provide the 3.3V to the
board by screwing the SMT398 on the two main mounting holes with the bolts
and screws provided with the board.
4. Connect the SHB links if required by your application.
5. Replace the carrier board in the host system or power on for a stand-alone
carrier.
Do NOT connect any external TTL (5v) signals to the SMT398 I/Os as the FPGA
is NOT 5v compliant. This implies that the ComPorts and global bus lines of
the carrier board MUST be LVTTL and that any device driving signals on the
SHB connectors must drive at LVTTL (3.3v).

Version 1.1.1 Page 9 of 38 SMT398 User Manual
SMT398 + DSP TIM
You can fit the SMT398 coupled with a DSP module on any of Sundance carrier
boards: Stand alones or plugged in a Host.
The DSP module can then be used to provide the SMT398 FPGA configuration
bistream and to communicate with the host.
Please, follow these steps to install the SMT398 module and the DSP TIM on a
carrier:
1. Remove the carrier board from the host system or turn the power off for a stand-
alone carrier.
2. Place the SMT398 module onto one of the TIM sites on the carrier board.
• Preferably, fit the DSP TIM on the first TIM site. This TIM site
communicates with the host. (See your carrier board User Manual.).
This allows the processor board to handle the interactions with the Host
by software instead of having to implement a communication interface
in the SMT398 FPGA. (Global Bus interface or ComPort interface on
ComPort 3).
• Fit the ComPort communication links between the DSP TIM and the
SMT398 respecting the rules on polarity at reset. (See your carrier
board User Manual.)
• To configure the SMT398 FPGA using the DSP TIM, then you need a
link between the 2 modules: ComPort 3 of the SMT398 MUST be
connected to one of the transmit ComPort at Reset(ComPort 0,1 or 2)
available on the DSP TIM.
3. Make sure that the board is firmly seated, and then provide the 3.3V to the board
by screwing the SMT398 on the two main mounting holes with the bolts and
screws provided with the board.
4. Connect the SHB links if required by your application.
5. Replace the carrier board in the host system or power on for a stand-alone
carrier.

Version 1.1.1 Page 10 of 38 SMT398 User Manual
FPGA Configuration
The FPGA can be configured 2 different ways:
• Using ComPort 3 to provide the bitstream. (See The service CPLD)
• Using the on-board JTAG header and Xilinx JTAG programming tools. (See
FPGA in system programming)
•
Electrical Interface
The service CPLD
The CPLD allows for FPGA configuration in slave SelectMap mode.
The CPLD is connected to ComPort number 3 of the SMT398 TIM connector.
Consequently, the ComPort on the other end of the link must be configured as
transmitter at power-up or after reset, i.e. ComPort channels 0, 1, or 2.
The typical SMT398 user does not need an in depth understanding of the
configuration sequence and of the Virtex II. However, for the purpose of debugging
and designing for the SMT398 an overview of the necessary configuration protocol
and bitstream formatting is recommended.
Therefore, this section describes the CPLD functions, the Virtex II bitstream format
and the necessary bitstream re-formatting when downloading the bitstream to the
FPGA via CPLD + ComPort 3.
Figure 2: FPGA configuration in SelectMap mode using CPLD provides waveforms to
illustrate the descriptions below.
At power up the FPGA is not configured.
LED L5 (See Figure 10:SMT398 Components placement-Top view, bottom right
hand corner of the picture) will be lit upon FPGA configuration.
At power up or after a Reset of the SMT398, the CPLD is configured and
implements a ComPort link receiver on ComPort 3.