Synopsys DesignWare 826-0 User manual

5.60a
March 2020
DesignWare®PCIe IP Prototyping Kit
Installation Guide
dw_ipk_dwipk_pcie – Product Codes: E826-0
E825-0
C368-0
C369-0
C046-0
E025-0
E026-0
E027-0
E827-0
E828-0

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Copyright Notice and Proprietary Information
© 2020 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Trademarks
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https://www.synopsys.com/company/legal/trademarks-brands.html
All other product or company names may be trademarks of their respective owners.
Free and Open-Source Software Licensing Notices
If applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.
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responsible for such websites and their practices, including privacy practices, availability, and content.
Synopsys, Inc.
www.synopsys.com

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PCIe IP Prototyping Kit Installation Guide Contents
Contents
Chapter 1
Setting Up Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1 Contents of PCIe IP Prototyping Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.2.1 Setting Up HAPS-80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.2.2 Setting Up PCIe Root Complex IP Prototyping Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2.3 Setting Up PCIe Endpoint IP Prototyping Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Chapter 2
Setting Up Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.1 Licensing and Tool Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.2 Setting License File Environment Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.3 Installing dw_ipk_dwipk_pcie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.3.1 Setting Up Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.3.2 Extracting the Release Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.4 Creating a Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.5 PCIe IP Prototyping Kit Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Chapter 3
Installing Software Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.1 Connecting to ARC SDP/ARC HSDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.1.1 Installing the Adept Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.2 Starting ARC SDP/ARC HSDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3 Where to Go Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Appendix A
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
A.1 HAPS-80 Supervision LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
A.2 HAPS-80 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
A.3 ARC SDP Board LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
A.4 ARC HSDK Development Kit Board LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

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Contents PCIe IP Prototyping Kit Installation Guide

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1
Setting Up Hardware Components
The PCIe IP Prototyping Kit provide hardware and software elements required to assemble a PCIe Root
Complex, and PCIe Endpoint prototyping platforms. Designers can rapidly develop, test, and debug IP
software before SoC availability. The kit is a complete and stand-alone solution that requires minimal
configuration.
This document provides the necessary information to set up the PCIe IP Prototyping Kit.
This document is divided in the following sections:
■“Contents of PCIe IP Prototyping Kit” on page 7
■“Hardware Setup” on page 16
Note
NoteNoteNote
Before setting up the hardware components, make sure you read the DesignWare PCIe IP
Prototyping Kit Release Notes.

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Product Codes
Table 1-1 lists the products and product codes for the DesignWare PCIe IP Prototyping Kit.
Table 1-1 Product Codes for DesignWare PCIe IP Prototyping Kit
Base Product Product Code
DesignWare PCIe Gen2 Root Complex Controller on HAPS-80, Xilinx Gen2 PHY, AXI tunnel to
ARC SDP
C368-0
DesignWare PCIe Gen2 Endpoint Controller on HAPS-80, Xilinx Gen2 PHY, with PCIe connection
for PC
C369-0
DesignWare PCIe Gen3 Root Complex Controller on HAPS-80, C10 PHY, AXI tunnel to ARC SDP E026-0
DesignWare PCIe Gen3 Root Complex Controller on HAPS-80, Xilinx Gen3 PHY, AXI tunnel to
ARC SDP
E027-0
DesignWare PCIe Gen3 Endpoint Controller on HAPS-80, C10 PHY, with PCIe connection for PC E025-0
DesignWare PCIe Gen3 Endpoint Controller on HAPS-80, Xilinx Gen3 PHY, with PCIe connection
for PC
C046-0
DesignWare PCIe Gen4 Root Complex Controller on HAPS-80, E16 PHY, AXI tunnel to
ARC SDP
E826-0
DesignWare PCIe Gen4 Endpoint Controller on HAPS-80, E16 PHY, PCIe connection for PC E825-0
DesignWare PCIe Gen5 Root Complex Controller on HAPS-80, E32 PHY, AXI tunnel to ARC HS E828-0
DesignWare PCIe Gen5 Endpoint Controller on HAPS-80, E32 PHY, with PCIe connection to PC E827-0

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1.1 Contents of PCIe IP Prototyping Kit
This section provides details about the contents of the prototyping kits.
Figure 1-1 shows PCIe Root Complex IP Prototyping Kit recommended components for the kits using
Synopsys PHY on HAPS-80
Figure 1-1 PCIe Root Complex IP Prototyping Kit Components with Synopsys PHY on HAPS-80
Attention
All PCIe IP Prototyping Kits were developed for use with HAPS FPGA board.
The HAPS, ARC SDP Mainboard and the PHY Daughter Card contain static sensitive
devices. Handle with care.
Electrostatic discharge (ESD) can damage the IP Prototyping Kit components. Perform
the procedures described in this section at an ESD workstation using an anti-static wrist
strap and a conductive foam pad.

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Figure 1-2 shows the PCIe Endpoint IP Prototyping Kit recommended components for the kits using
Synopsys PHY on HAPS-80.
Figure 1-3 shows the PCIe Root Complex IP Prototyping Kit recommended components for the kits using
the Xilinx PHY on HAPS-80.
Figure 1-2 PCIe Endpoint IP Prototyping Kit Components with Synopsys PHY on HAPS-80
Note
NoteNoteNote
The Synopsys PCIe PHY can be a Synopsys C10 PHY, a Synopsys E16 PHY or a E32 PHY
board.
See Table 1-2 for more details.

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Figure 1-3 PCIe Root Complex IP Prototyping Kit Components with Xilinx PHY on HAPS-80
Figure 1-4 shows the PCIe Endpoint IP Prototyping Kit recommended components for the kits using the
Xilinx PHY on HAPS-80.

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Figure 1-4 PCIe Endpoint IP Prototyping Kit Components with Xilinx PHY on HAPS-80
HAPS-80
SD
Card
PCIE-8_PDL_MGB
PCIe x8 Extender Cable
RISER1_MGB

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Figure 1-5 PCIe Endpoint IP Prototyping Kit Components with E32 PHY on HAPS-80

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Figure 1-6 PCIe Root Complex IP Prototyping Kit Components with E32 PHY on HAPS-80
Table 1-2 provides a description of the recommended items and part numbers used in the hardware setup.
There are specific components for the PCIe Gen3 and Gen4 setups, see “Hardware Setup” on page 16 for the
set up instructions.
Table 1-2 PCIe IP Prototyping Kit Recommended Components and Part Numbers
Quantity Part Number Item Description
DesignWare PCIe Gen4 Root Complex Controller on HAPS-80, E16 PHY, AXI tunnel to ARC SDP (E826-0)
1 HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80
1 DWC_PHY_E16_P
CIe_Gen4
PHY Board Synopsys E16 PHY Board (PCIe Gen4 PHY)
1 8KH2-0723-0250a3MTM PCIe x8
Extender
Twin Axial Cable Assembly or PCIe x8 extender card
applications
1 HW0071-0 ARC AXS101 SDP DesignWare ARC AXS 101 Software Development Platform
2 HW0039-0 CON_CABLE_25_HT3 HT3 Cables
1 N/A PCIe Backplane Rev. C PCIe Root Complex - Endpoint Backplane
23052113 TS2GSDC TRANSCEND TS2GSDC CARD

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DesignWare PCIe Gen4 Endpoint Controller on HAPS-80, E16 PHY, PCIe connection for PC (E825-0)
1 HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80
1 DWC_PHY_E16_P
CIe_Gen4
PHY Board Synopsys E16 PHY Board (PCIe Gen4 PHY)
1 8KH2-0723-0250a3MTM PCIe x8
Extender
Twin Axial Cable Assembly or PCIe x8 extender card
applications
1 3052113 SD Card TRANSCEND TS2GSDC CARD
DesignWare PCIe Endpoint Controller on HAPS-80, C10 PHY, PCIe connection for PC (E025-0)
1 8KH2-0723-0250a3MTM PCIe x8 Extender Twin Axial Cable Assembly or PCIe x8 extender card
applications
1 HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80
1 DWC_PHY_C10_P
Cle_Gen3
PHY Board Synopsys C10 PHY Board (PCIe Gen3 PHY)
1 3052113 SD Card TRANSCEND TS2GSDC CARD
DesignWare PCIe Root Complex Controller on HAPS-80, C10 PHY, AXI tunnel to ARC SDP (E026-0)
1 HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80
1 DWC_PHY_C10_P
Cle_Gen3
PHY Board Synopsys C10 PHY Board (PCIe Gen3 PHY)
1 8KH2-0723-0250a3MTM PCIe x8 Extender Twin Axial Cable Assembly or PCIe x8 extender card
applications
1 HW0071-0 ARC AXS101 SDP DesignWare ARC AXS 101 Software Development Platform
2 HW0039-0 CON_CABLE_25_HT3 HT3 Cables
1 N/A PCIe Backplane Rev. C PCIe Root Complex - Endpoint Backplane
2 3052113 SD Card TRANSCEND TS2GSDC CARD
DesignWare PCIe Gen3 Endpoint Controller on HAPS-80, Xilinx Gen3 PHY, with PCIe connection for PC (C046-0)
1 HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80
1 3052113 SD Card TRANSCEND TS2GSDC CARD
Table 1-2 PCIe IP Prototyping Kit Recommended Components and Part Numbers (Continued)
Quantity Part Number Item Description

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1 HW0270-0 PCIE x4 Gen3 kitbThe PCIE x4 Gen3 kit includes the following components:
■PCIE-4 MGB – Four lane PCI Express card with MGB
connection
■PCIE-4 PC – Four lane PCI Express card with PC
connection
■PCIE-4 Cable – Four lane connection cable
DesignWare PCIe Gen3 Root Complex Controller on HAPS-80, Xilinx Gen3 PHY, AXI tunnel to ARC SDP (E027-0)
1 HW0071-0 ARC AXS101 SDP DesignWare ARC AXS 101 Software Development Platform
1 HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80
2 3052113 SD Card TRANSCEND TS2GSDC CARD
1 HW0270-0 PCIE x4 Gen3 kit The PCIE x4 Gen3 kit includes the following components:
■PCIE-4 MGB – Four lane PCI Express card with MGB
connection
■PCIE-4 PC – Four lane PCI Express card with PC
connection
■PCIE-4 Cable – Four lane connection cable
2 HW0039-0 CON_CABLE_25_HT3 HT3 Cables
1 N/A PCIe Backplane Rev. C PCIe Root Complex - Endpoint Backplane
DesignWare PCIe Gen5 Root Complex Controller on HAPS-80, E32 PHY, AXI tunnel to ARC HS (E828-0)
1 HW0352-000 HAPS-80 S26 (-2) High Performance ASIC Prototyping System (HAPS-80)
1 DWC_PHY_E32_P
CIe_Gen5
PHY Board Synopsys E32 PHY Board (PCIe Gen5 PHY)
1 HW0469-000 ARC HSDK DW ARC HSDK Development Kit
1 3052113 SD card TRANSCEND TS2GSDC CARD
1 SDSQUAR-064G-
GN
Micro SD Micro SD card
DesignWare PCIe Gen5 Endpoint on HAPS-80, E32 PHY, with PCIe connection to PC (E827-0)
1 HW0352-000 HAPS-80 S26 (-2) High Performance ASIC Prototyping System (HAPS-80)
1 DWC_PHY_E32_P
CIe_Gen5
PHY Board Synopsys E32 PHY Board (PCIe Gen5 PHY)
8 HW0240-000 H_EXT_CABLE40_HT
3
HT3 cables
1 3052113 SD card TRANSCEND TS2GSDC CARD
Table 1-2 PCIe IP Prototyping Kit Recommended Components and Part Numbers (Continued)
Quantity Part Number Item Description

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a. 3MTM Part Number
b. To perform Precision Time Measurement (PTM) tests, use the PCIE-8_PDL_MGB card to connect the HAPS board to the
Motherboard or PTC card. The PCIE-4 MGB Kit has an embedded PCIe bridge chip, that influences test results.
Note
NoteNoteNote
To power the PCIe Backplane you need an ATX power supply.

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1.2 Hardware Setup
This section provides instructions for the following:
■Setting Up HAPS-80
■Setting Up PCIe Root Complex IP Prototyping Kits
■Setting Up PCIe Endpoint IP Prototyping Kits
1.2.1 Setting Up HAPS-80
To set up the HAPS-80, perform the following tasks.
1. Insert the SD card containing the FPGA build files in the HAPS-80 board. The SD card slot is located
in the Front Panel, see Figure 1-7.
Figure 1-7 Detail of the HAPS-80 Front Panel
2. Use the HAPS-80 Conf. Sel. wheel to select the project you want to load. Conf. Sel. wheel position 0
targets the project within the autorun file on the SD card.
Note
NoteNoteNote
■If you are using the IP Prototyping Kit with the Xilinx PHY, follow the steps 3to 7.
■If you are using the IP Prototyping Kit with the Synopsys PHY (E16, C10 or E32 PHY),
jump to step 8.

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3. Remove the locker pin, and the four screws holding the MGB shelves, see Figure 1-8.
Figure 1-8 Detail of the HAPS-80 MGB Shelves
4. Remove the MGB Shelves from the HAPS-80 and insert the RISER1_MGB card in the MGB Shelves,
as shown in Figure 1-9.
Figure 1-9 Detail of the RISER1_MGB and HAPS-80

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5. Insert the MGB Shelves in the HAPS-80, and tighten the four screws removed in Step 3.
6. In an upward movement, push the RISER1_MGB card into the MGB1 port. Make sure the
RISER1_MGB card is completely inserted.
7. Connect the PCIE-4 MGB to the RISER1_MGB card J2 port. Use the grooves in the MGB shelves to
guide the PCIE-8 paddle board (See Figure 1-7).
8. Connect the Synopsys PCIe PHY Board to the HAPS-80 board.
If you're using a C10 PHY, use HT3 ports J5-J10 on the HAPS-80 and ports P1-P6 on the C10 PHY to
mechanically connect the boards.
If you're using a E16 PHY, use HT3 ports J5-J10 on the HAPS-80 and ports P1-P6 on the E16 PHY.
Figure 1-10 illustrates this connection using a C10 PHY board as an example.
Figure 1-10 Connection of C10 PHY to HAPS-80
If you are using E32 PHY, use HT3 ports 20, 21, 22 and 23 on the HAPS-80 and HT3 ports 4 ,3 ,2 and 1
respectively, on the E32 PHY. And also ports 8, 9, 10 and 11 on the HAPS-80 and ports 5, 6 ,7 and 8,
respectively, on the E32 PHY to mechanically connect the boards.
Figure 1-16 and Figure 1-22 illustrates this connection using a E32 PHY board.
Attention
To avoid damaging the HAPS-80 and RISER1_MGB card, make sure you disconnect the
RISER1_MGB card from the HAPS-80 before removing the MGB Shelves.

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1.2.2 Setting Up PCIe Root Complex IP Prototyping Kits
This section provides instructions for setting up a PCIe Root Complex IP Prototyping Kit hardware, using
the Xilinx, or a Synopsys PCIe PHY board.
1. Connect the HAPS-80 and ARC SDP AXS101. These connections depend on the used PHY.
Figure 1-11 shows the connection for setups that use Xilinx PHY.
a. First HT3 cable to the HAPS-80 board on the HT3 track 6 (Xilinx PHY) or track 23 (C10 or E16)
b. Other end of the first HT3 cable to the ARC SDP HT3 track J3.
c. Second HT3 cable to the HAPS-80 board on the HT3 track 7 (Xilinx PHY) or track 24 (C10 or E16).
d. Other end of the second HT3 to the ARC SDP HT3 track J4.
2. Insert the SD card containing the Linux image in the ARC AXS101 SDP system board. You can find
an uImage file in the <workspace>/software/PCI/Linux/main/images/axs101-rc folder
Figure 1-11 HAPS-80 to ARC SDP HT3 Connection
3. To set up the PCIe Root Complex and Endpoint device, make the next connections:
a. Connect the ATX 4 Pin peripheral power connector to the backplane.
b. Make the Root Complex connection:
Note
NoteNoteNote
■To power the PCIe Backplane you need an ATX power supply.
■The PCIe Root Complex IPK with E32 PHY uses an ARC HSDK instead of an ARC SDP.
The connection between HAPS-80 and ARC HSDK is different. For instructions follow
“Using ARC HS Development kit” on page 25

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■If you are using the Xilinx PHY, connect the Paddle board PCIe end to the PCIe Root Complex
slot.
■If you are using a Synopsys PCIe PHY1, connect the PCIe PHY board to the PCIe Root
Complex slot.
c. Connect the PCIe endpoint device to the PCIe Endpoint slot.
d. If you are using the Xilinx PHY, connect the Paddle board MGB end to the HAPS-80 MGB1 port.
Flip the PCIe Backplane board over the HAPS-80 board and align the Paddle board with the MGB
Brackets, see Figure 1-13 on page 22.
1. The Synopsys PCIe PHY can be a Synopsys C10, E16 or E32 PHY board.