Synopsys TSMC180 Product guide

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 1-30
DWC ADC 12b5M SAR, TSMC180
Databook
3640tg -12-bit, 5MSPS SAR ADC with differential 19:1 InputMux
Version 1.9
April 2012

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 2-30
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DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 3-30
Contents
1Features............................................................................................................................... 4
2General Description............................................................................................................ 4
3Functional Diagram............................................................................................................ 4
4Specifications...................................................................................................................... 5
5Pin Description................................................................................................................... 8
6Operating Modes.............................................................................................................. 10
Start-Up Sequence................................................................................................................ 10
Deep power down mode ..................................................................................................... 11
Power-down Mode .............................................................................................................. 11
Standby Mode...................................................................................................................... 12
Normal Operation................................................................................................................ 12
Current Consumption during Normal Operation............................................................... 12
Internal Voltage Regulator................................................................................................... 13
7Timing Diagrams.............................................................................................................. 14
8Digital Offset Calibration ................................................................................................. 19
10 Application Notes......................................................................................................... 23
Cell Placement...................................................................................................................... 23
Power Supplies .................................................................................................................... 23
System Level Clock Issues ................................................................................................... 24
Routing of Analog and Reference Signals ........................................................................... 24
ESD / Latch-Up................................................................................................................... 24
11 Cell Routing Constrains................................................................................................ 25
12 Connections to the IO PAD ring................................................................................... 26
13 PCB Guidelines............................................................................................................. 29
Appendix A –Minimum Sampling Time –(Worst case conditions)...................................... 30

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 4-30
1Features
2General Description
TSMC 180nm G CMOS technology
Selectable 12 bit, down to 6 bit Resolution
5 MSPS Conversion Rate
Single-Ended or Differential Input
19:1 Multiplexed Inputs
6 high speed inputs
13 low speed inputs
3.6V down to 1.8V Analog Power Supply
1.8V ± 10% Digital Power Supply
Current Consumption:
18uA at 10kSPS
240uA at 1MSPS
1.1mA at 5MSPS
Core Cell Area: 0.25 mm2
This macro-cell is a power and area optimized
Successive-Approximation ADC, having the
resolution selectable between 12, 10, 8 and 6 bit. It
is instantiated in a CMOS 180nm G process.
To maximize flexibility there are serial and parallel
data outputs, and input pins are provided to apply
an external reference voltage, which defines the full-
scale input range. This reference voltage can be the
analog power supply, for rail-to-rail operation.
An internal voltage regulator is included in order to
improve performance when the digital power supply
is connected to the digital core power supply.
A digital calibration algorithm is implemented to
reduce the offset voltage. Furthermore both
differential and single-ended signals can be
processed.
An analog multiplexer is added to enable selection
from a number of inputs.
This cell is suitable to serve as an auxiliary ADC of
a microprocessor, as a house-keeping converter for
digital applications and broadband wireless
communications.
3Functional Diagram
bvos
for test
vinp0
resetadc
sel
soc
clk
enadc
avdd
agnd
SAR
ADC
dvdd_ldo
b11..b0
19:1
MUX
eoc
dgnd
agndref
vrefp
sob
selres
dislvl
enctr
vinn0
vinp1
vinn1
…
vinp18
vinn18
calon
seldiff
dvdd
startcal
resetcal
bypasscal
loadcal
scan interface
atstbus
enldo
bvosi
LDO

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 5-30
4Specifications
Parameter
Conditions
MIN
TYP
MAX
Unit
Technology
No analog options
TSMC180nmG CMOS, with
3.3V IO devices
Minimum metal stack
supported
5m_3x1n
Metal stack available in
DWDL
5m_3x1n , 6m_4x1n
Area
-
0.25
796 x 314
mm2
µm*µm
Standard Cell Library
(TSMC) TCB018GBWP7T Rev. 270a
TSMC180nm Core Library
Resolution
selres=11
selres=10
selres=01
selres=00
12
10
8
6
Bit
Junction temperature
-
-40
+50
+125
ºC
Analog Input
Full-scale input range
seldiff=L
agndref
vrefp
V
seldiff=H
2*(vrefp –agndref)
Vppdiff
Input signal common mode
(only for differential mode)
seldiff=H
(vrefp + agndref)/2
V
Input sampling capacitance (CS)1
No parasitic
capacitances included
5
pF
Analog Biasing
Positive reference voltage(vrefp)
avdd>= 2V
2
avdd
avdd
V
avdd< 2V
avdd
avdd
avdd
V
Negative referencevoltage (agndref)
0
0
0.1
V
Digital Output
Logic Family
CMOS
-
Output Logic Coding
Unsigned Binary:
BottomScale: b11..b0=0h
Top Scale (selres=11): b11..b0=FFFh
Top Scale (selres=10): b11..b2=3FFh
Top Scale (selres=01): b11..b4=FFh
Top Scale (selres=00): b11..b6=3Fh
-
Timing Characteristics
Input clock frequency (fclk)
0.14
70
72
MHz
Sampling rate (fs)
selres=11
selres=10
selres=01
selres=00
0.01
0.012
0.014
0.0175
5
5.83
7
8.75
5.14
6
7.2
9
MSPS
Conversioncycle
selres=11
selres=10
selres=01
selres=00
14
12
10
8
CLK cycles
Clock duty cycle
-
45
50
55
%
Data latency
selres=11
selres=10
selres=01
selres=00
12.5
10.5
8.5
6.5
CLK cycles
Power up time
Fromenadc=L, enldo=L
To enadc=L, enldo=H
(LDO start-up –tup_ldo)
3
5
10
µs
Fromenadc=L,enldo=H
To enadc=H, enldo=H
(ADCstart-up –tup_adc)
1
Conversion
cycles

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 6-30
Parameter
Conditions
MIN
TYP
MAX
Unit
Timing Characteristics (Continued)
clk falling edge to sampling delay (tsd)
-
4.5
ns
socsetup time beforeclkrising edge (tsocst)
-
0
ns
soc hold time afterclkrising edge (tsochld)
-
5
ns
clk rising edge to eoc rising edge delay time
(teocr)
With a 250 fF load
3
ns
clk rising edge to eoc falling edge delay time
(teocf)
With a 250 fF load
3
ns
Valid data out delay after eoc rising edge
(tdata)
With a 250 fF load
1
ns
Valid serial data output delay after clk falling
edge (tdatas)
With a 250 fF load
5
ns
loadcal hold time after clk falling edge
(tloadcalhold)
-
2
ns
loadcal setup time before clk rising edge
(tloadcalsetup)
-
1.5
ns
Power Supply Requirements
Analog Supply Voltage
1.8
3.3
3.6
V
Digital Supply Voltage
1.62
1.8
1.98
V
Current Consumption, Fs=5MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=H
-
-
1100
100
-
-
µA
Current Consumption, Fs=1MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=H
-
-
240
20
-
-
µA
Current Consumption, Fs=10kSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=H
-
-
17
1
-
-
µA
Current Consumption, Fs=5MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=L
-
-
1000
100
-
-
µA
Current Consumption, Fs=1MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=L
-
-
220
20
-
-
µA
Current Consumption, Fs=10kSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=L
-
-
17
1
-
-
µA
Current Consumption, Fs=5MSPS 2,3 avdd
dvdd
enadc=H, soc=L,seldiff=x
-
-
180
70
-
-
µA
Current Consumption, Fs=1MSPS 2,3 avdd
dvdd
enadc=H soc=L,seldiff=x
-
-
50
13
-
-
µA
Current Consumption, Fs=10kSPS 2,3 avdd
dvdd
enadc=H soc=L,seldiff=x
-
-
17
1
-
-
µA
Power down Current Consumption3avdd
dvdd
enadc=L, enldo=L, dislvl=H
(deep power down mode)
-
-
1
0.5
-
-
µA
Power down Current Consumption3avdd
dvdd
enadc=L, enldo=L, dislvl=L
(power down mode)
-
-
1
1
-
-
µA
Power down Current Consumption3avdd
dvdd
enadc=L, enldo=H, dislvl=L
(standby mode)
-
-
15
1
-
-
µA
Note 1 –Successive conversion mode (soc signal always set to high, check section 7)
Note 2 –soc signal set to low, waiting f or a conv ersion (check section 7)
Note 3 –avdd current consumption includes current consumption through vrefp

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 7-30
avdd = 3.3V, dvdd = 1.8V, Tjunction= 50°C, fclk=70MHz, fin=50kHz, selres=11 (12-bit mode), seldiff=L (single-ended mode), vrefp=avdd,
agndref=0, enldo=H.
Parameter
Conditions
MIN
TYP
MAX
Unit
DNL
1.0
LSB
INL
2.0
LSB
SINAD4
68
dBFS
Offset error
Calibration enabled
Calibration disabled
2
64
LSB
LSB
Total unadjusted error
Calibration enabled
5
LSB
Note 4- Value measured with a –0.5dBFS input signal and then extrapolated tofull scale.

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 8-30
5Pin Description
Pin Name
I/O
Type
Function
vinp18 .. 0
I
Analog
Analog input signals
In differential input mode (seldiff=H), vinp18...vinp1are the positive inputs, vinn18...vinn1 are
the negative inputs.
vinp0 available only forsingle ended input mode.
vinn18 .. 0
I
Analog
Analog input signals
In single ended input mode (seldiff=L), the negative input vinn0 must beconnected to
ground.
vrefp
I
Analog
Positive ReferenceVoltage,
The reference voltage must be applied externally to the vrefp pin, in order to define theADC
full scale input range.
This pin presents aswitchedcapacitive load to its driver, that will be around 3pF inworst
case.The switching frequency is theclockfrequency. The vrefp input impedancewill vary
through theconversion cycle, between the described 3pF and a negligible capacitorvalue of
around 1fF.
agndref
I
Analog
Negative ReferenceVoltage
The reference groundvoltage must be applied externally to the agndref pin, in order to define
the ADCfull scale inputrange
atstbus
I/O
Analog
Internal voltage regulator analog probing testsignal.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
selres1 .. 0
I
Digital
Selects theADCresolution:
selres=006-bit mode
selres=01 8-bit mode
selres=10 10-bit mode
selres=1112-bit mode
seldiff
I
Digital
Selects theADCinput mode (18 selectable inputs are available in both configurations,
vinp0|n0 is available onlyfor single-ended mode):
seldiff=L single ended inputs
seldiff=H differential input
dislvl
I
Digital
(3.3V)
This digital input signalmust have 3.3 V levels (avdd).
This signal is usedfor two purposes:
1. When there is no digital supply (dvdd) but the analogsupply (avdd) it is powered on,
activating this signal (dislvl = H) prevents current consumption on analog supply (avdd)
during digital supply (dvdd) startup.
2. This signal is also used tocontrol the powerswitching of dvdd inside the IP, defining the
deep power down mode.
sel4..0
I
Digital
Input multiplexer control signals:
- vinp|n0selected when sel4..0=0H
- vinp|n18selectedwhensel4..0=12H;
Under ADC test mode itis mandatory to have access to this signal, directlyfrom chip pinout
or throughregisters.
resetadc
I
Digital
Reset of internal buffers and registers (Active H).
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
soc
I
Digital
Start-of-conversionsignal(Active H). Starts the conversioncycle on the nextclk rising edge.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
clk
I
Digital
Clock Input.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
enadc
I
Digital
Enable ADC(enadc=Hnormal operation).
enldo
I
Digital
Enable internal voltage regulator (enldo=Hnormal operation).
enctr2..0
I
Digital /
Test
Digital signals to enable internalanalog programmability modes used for test purposes. In
normal operation thesesignals should be connected in to gnd.
Under ADC test mode itis mandatory to have access to this signal, directlyfrom chip pinout
or throughregisters.

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 9-30
Pin Name
I/O
Type
Function
b11..0
O
Digital
Parallel Output Bits. The MSB is b11; the LSB is b0in 12-bit mode, b2in 10-bit mode,b4 in
8-bit mode and b6in 6-bit mode.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
sob
O
Digital
Serial Output Bit (startingfromthe MSB).
eoc
O
Digital
End-of-conversion. The rising edge indicates thatconversion terminated and output data is
valid.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
bvos6..0
O
Digital
Outputs of the digital offsetcalibration block.
bvosi6..0
I
Digital
Input of the digital offset calibration block
bypasscal
I
Digital
Signal that bypasses the offset calibration block (Active H). In this mode bvos6…0 is set to
1000000.
loadcal
I
Digital
Signal that loads the offsetcalibrationword into the internal registers (Active H)
startcal
I
Digital
Signal that starts the offset calibrationcycle (Active H).
resetcal
I
Digital
Reset of internal registers of the digital offsetcalibration block (Active H).
calon
O
Digital
Indicates if theADCis in calibration mode (Active H).
scanclk
I
Digital
Scan chain clocksignal. Used to capture the data andshift the patterns throughthe chain.
scanen
I
Digital
Selects between capture(scanen = L) and shift(scanen = H) modes.
scanmode
I
Digital
Configures digital offsetcalibration block toscan test mode (Active H).
scanreset
I
Digital
Scan chain reset.
scanin
I
Digital
Scan chain input.
scanout
O
Digital
Scan chain output.
avdd, agnd
I/O
Power
Top and BottomAnalog Power Supplies (3.3V).
dvdd, dgnd
I/O
Power
Top and Bottom Digital Power Supplies (1.8V).
dvdd_ldo
I/O
Analog
Internal voltage regulator output(enldo=H). With enldo=L (internal voltage regulator bypass)
the power signalmust be supplied externally(1.8V).

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 10-30
6Operating Modes
This section describes the power-up sequence and the various operating modes that the
DWC ADC 12b5MSAR, TSMC180
Table 2 –SAR ADC operating modes.
Mode
Configuration
selres1..0
seldiff
sel4..0
dislvl
enldo
enadc
resetadc
soc
bypasscal
startcal
loadcal
resetcal
Deep Pow er-down
X
X
X
1
0
0
X
X
X
X
X
X
Power-down
X
X
X
0
0
0
X
X
X
X
X
X
Standby
X
X
X
0
1
0
X
X
X
X
X
X
Normal Operation –Single-ended
X
0
X
0
1
1
0
X
X
0
0
0
Normal Operation –Differential
X
1
X
0
1
1
0
X
X
0
0
0
Calibration –Single-ended
X
0
X
0
1
1
0
0
0
0
0
0
Calibration –Differential
X
1
X
0
1
1
0
0
0
0
0
0
Bypass Calibration
X
X
X
0
1
1
0
X
1
0
0
0
Load Calibration
X
X
X
0
1
1
0
X
0
0
1
0
The following start-up sequence should be followed during system startup:
1. During the power up time of the supply voltages, ensure that enldo=L, enadc=L and
soc=L;
2. Power up both dvdd and avdd supplies;
3. Once the power supplies are stable set enldo=H and wait for the internal voltage
regulator start-up;
4. Set the resetcal signal to high during one clock cycle. There is no need to wait for the
internal voltage regulator start-up time to set resetcal to high. This signal can be set
to high right after the power supplies are stable. The only demand is to set it to high
during one clock cycle before the next step (enadc=H);
5. Set enadc=H;
6. Set the resetadc signal to high during one clock cycle;
7. For applications that require a low offset, trigger a calibration cycle using startcal, as
described in Section 8. After the calibration is complete the ADC is ready to receive
analog inputs.

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 11-30
If the offset is not a critical parameter, there is no need to run the calibration cycle.
However, there is the need to start a dummy conversion cycle (by setting soc=H, as
described in Section 7), before the ADC is ready to receive analog inputs;
8. In situations where the avdd supply is active and the dvdd supply is not active (not
supplied), the ADC may develop excessive leakage current. If the dvdd is left
unpowered for extended periods and this leakage power becomes a concern, it can
be eliminated by asserting dislvl=H until the dvdd supply is ramped up. Once the
dvdd supply goes to its nominal range, dislvl can be set to low.
Note that the dislvl digital input signal must have 3.3 Vlevels (avdd).
Deep power down mode
The deep power down mode enables the user to reduce the leakage current to the absolute
minimum, by switching off the supply of the digital calibration block (dvdd). In this mode all
digital outputs are set to low.
The deep power down mode is controlled by the signal dislvl=H, in addition to the enadc=L
and enldo=L already used in the normal power down mode. In this mode, all internal register
(calibration register) values will be lost. It is therefore advisable to store the calibration word
(available through bvos6…0bus before entering deep power down mode.
The startup sequence from deep power down should be as follows
0. Set dislvl=L;
1. Set enldo=Hand wait for the internal voltage regulator start-up;
2. Set the resetcal signal to high during one clock cycle. There is no need to wait for the
internal voltage regulator start-up time to set resetcal to high. This signal can be set
to high right after the power supplies are stable. The only demand is to set it to high
during one clock cycle before the next step (enadc=H);
3. Set enadc=H;
4. Set the resetadc signal to high during one clock cycle;
5. Ensure that the calibration word is valid at the inputs bvosi6…0during one clock
cycle after the release of reset signals, and set loadcal=H during one clock cycle, in
order to read back the calibration value into the internal registers (for a better
understanding please check Figure 5 and 12);
6. Run dummy conversion cycle, the ADC is ready to receive the analog signal.
If the ADC is in deep power down for extended periods, then it is recommended that a new
calibration cycle is run at power up time.
The dummy conversion cycle can be started simultaneously with the loading of the
calibration word (step 5 above).
Power-down Mode
The power down mode is obtained by setting enadc=L and enldo=L.
While the ADC is in power down mode, the calibration coefficients are kept in the internal
registers of the ADC. In this way, the ADC can be brought back from power down and a

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 12-30
“calibrated” conversion cycle started immediately after the Power Up Time has elapsed,
(Power Up time corresponds to one dummyconversion cycle).
This mode of operation is useful in cases where the power down and start-up sequence is
very quick. If the ADC is in power down for extended periods, then it is recommended that a
new calibration cycle is run at power up time.
Standby Mode
The usage of the internal voltage regulator also counts with a fast start-up mode. Instead of
waiting for the internal voltage regulator start-up every time the ADC is powered on, it is
possible to keep the internal voltage regulator always enabled (enldo=H). In this way, the
start-up time will be only one conversion cycle. In this operating mode (enldo=H and
enadc=L), the current consumption is reduced to minimum. This is relevant for higher
sampling frequencies, where the current consumption in normal operation is much higher
than in standby mode.
Normal Operation
The start of a conversion is controlled by the soc signal, and the eoc indicates that a
conversion has ended.
The ADC may be configured to receiver either single-ended or differential input signals, in
the following way:
1. By setting seldiff=H, vinp18-vinn18 ... vinp2-vinn2, vinp1-vinn1 are the positive-
negative pairs of differential input signals. There is no differential mode available for
vinp0-vinn0.
2. By setting seldiff=L, vinp18..vinp0 are single ended inputs.vinn0should be always
connected to the analog ground and used as negative input for all inputs in single
ended mode.
The input is selected by sel4..0. The full-scale input range is defined as:
1. vrefp –agndref, if seldiff=L
2. 2*(vrefp –agndref), with a commonmode voltage of (vrefp + agndref)/2, if seldif=H
seldiff and selres control signals must remain unchanged when a conversion is being done.
After changing seldiff, in applications where the offset is critical, a new calibration cycle must
be triggered (or loaded a calibration word using loadcal), before using the ADC to perform a
conversion. This is not necessary when simply changing selres.
Asserting resetcal will reset the internal calibration registers, therefore eliminating the
calibration coefficients.
Current Consumption during Normal Operation
This ADC is capable of very low power operation. Current consumption is determined by the
clock frequency with which the ADC is being used, scaling almost linearly with the clock
frequency, as it is shown in the above graphic.

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 13-30
Figure 1 –ADC current consumption (single ended mode).
The current consumption presented in the previous figure is for the situation where the ADC
is operating in successive conversion mode (soc always set to high, check section 7 for
more detail).
If the ADC is waiting for a new conversion to start (soc set to low and eoc set to high), the
current consumption during this period will be greatly reduced. This can be an interesting
feature if the ADC is operating in single conversion mode (check section 7 for more detail),
which means that soc signal will only be set to high from time to time. The effective current
consumption reduction will depend on the time period left between each conversion cycle.
Please check the current consumption while the ADC is waiting for a new conversion cycle
(soc set to lowand eoc set to high), in power supply requirements section in the
specifications table.
Internal Voltage Regulator
The IP includes an internal voltage regulator to generate a clean internal 1.8V power supply
(dvdd_ldo).
In case there is a clean external 1.8V power supply available for ADC use, the internal
voltage regulator can be bypassed by setting enldo=L and connecting dvdd_ldo pin to the
clean external 1.8Vpower supply.
10
100
1000
140 1400 14000
Current Consumption (uA)
ADC clock frequency (kHz)

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 14-30
7Timing Diagrams
The Timing Diagram below represents the synchronization between the signals clk, soc, eoc
and the output bits. After a conversion cycle eoc is placed at high. A new conversion only
begins when soc at high level is detected. In this way, if the soc signal is held at the high
logic value, the ADC makes successive conversion cycles, achieving the maximum sampling
rate, if soc is maintained low no conversion is started.
The output data can be read fromb11...b0 (parallel outputs) or from sob (serial output). The
output code is available at b11...b0, tdata nanosecond after the rising edge of eoc. The serial
output provides each bit after it has been obtained by the internal comparator.
In case of a single conversion, where the soc signal is asserted to high only from time to
time (see diagram below).
Taking as reference the clock rising edge when soc at high level is detected:
The input selection control signals (sel0…4) must be stable during both the clock
cycle immediately before, and the one immediately after that edge.
The resolution selection control signal (selres) can only be updated after the end of
the conversion (during eoc=H).
The input mode selection control signal (seldiff) must be already stable one clock
cycle immediately before that edge.
Figure 2 –Normal operation (single conversion).
In case of successive conversions (see diagram below):
The input selection control signals (sel0…4) must remain unchanged during the last
(14th) clock cycle of a conversion and the first clock cycle (1st) of the next. This is
guaranteed by selecting the input for the next conversion, between the 2nd and the
13th clock cycles of the current conversion.
The resolution selection control signal (selres) can only be updated after the end of
the conversion (during eoc=H).
The input mode selection control signal (seldiff) can only be updated during the half
clock cycle before the end of the conversion.
tsocst tsochld
teocf
tdata
Sample Vin
N+1 N+2 1
clk
sel4..0
soc
eoc
b11... b0
Internal
S/H
Select Vin channel
Hold Vin
selres Select ADC resolution
seldiff Select ADC input mode
teocr
tclk/2 teocr

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 15-30
Figure 3 –Normal operation (successive conversions).N: Resolution.
The timing Diagram below shows the startup sequence, in applications where the offset is
not a critical parameter (it is assumed that dislvl is already low). If the offset is critical, then a
calibration cycle should be triggered, as described in section 8. In this timing diagram is
described both the internal regulator and the ADC start-up.
Figure 4 - Startup Sequence from power down mode
The Sample-and-Hold (S/H) starts sampling the input voltage when eoc goes high until tsd
nanosecond after the clock falling edge in the 1st cycle. The input selection bits (sel4..0) and
the ADC input mode selection (seldiff) must remain unchanged during this period.
The timing Diagram below shows the start-up sequence from deep power down mode. It
assumes that calibration has been performed in a previous normal operation cycle and that
the calibration value has been stored outside the IP before entering deep power down mode.
If a new calibration cycle is to be run, please refer to the description of the calibration cycle
in section 8.
tsocst tsochld
teocr teocf
tdata
tsd
Hold Vin(j)Sample Vin(j+1)
Sample Vin(j)
1 2 N+1 N+2 1
clk
sel4..0
soc
eoc
b11... b0
Internal
S/H
x
Select Vin(j) channel Select Vin(j+1) channel
Hold Vin(j+1)
Output Data j
Output Data j-1
b11sob b11-N
tdatas
b8b12-N
tdatas
3
b10-N
selres Select ADC resolution Select ADC resolution
seldiff Select ADC input mode Select ADC input mode
tclk/2
tsocst tsochld
teocr teocf
tdata
tsd
Hold Vin(n)
Sample Vin(n+1)
Sample Vin(n)
1 2 11 12 1
clk
soc
eoc
b11...0
Internal
S/H
x
resetadc
x-1
enldo
enadc
tup_ldo
resetcal

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 16-30
Figure 5 - Startup Sequence from deep power down mode.
The figure below shows the (simplified) equivalent circuit of the S/H input network, where CS
is the storage capacitor, RSis the resistance of the sampling switch and RIis the output
impedance of the signal source (vI). The Figure 3 shows the situation where the conversion
cycle j+1 starts immediately after conversion cycle nends. In this case the duration of the
sampling phase is, approximately, 1.5/fclk. CSmust be charged in that phase, and it must be
ensured that the voltage at its terminals becomes sufficiently near vI. To guarantee this, RI
may not take arbitrarily large values.
Figure 6 - Model of the sampling network.
tsocst tsochld
teocr teocf
tdata
tsd
Hold Vin(n)
Sample Vin(n+1)
Sample Vin(n)
soc
eoc
b11... b0
Internal
S/H
reset
Dummy Conversion Cycle
dislvl
bvos6..bvos0
tloadcalsetup tloadcalhold
loadcal
1 2 11 12 1
clk
xx-1
enldo
enadc
...
tup_ldo
bvosi6..bvosi0
vI
RI
RS
CS
SAR ADC
sample

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 17-30
The Figure 7 shows how the sampling time can be increased, to allow the operation with
signal sources having a low driving capability: the soc signal is delayed during the number of
clock cycles necessary to guarantee the accurate input signal sampling. During this period
the input selection bits (sel4..0) must remain unchanged. Note that this operation reduces
the effective sampling rate.
This ADC has two types of inputs: vinp|n5…0 are fast inputs and vinp|n18…6 are slow
inputs. All inputs have the same functionality, but during the sampling period, vinp|n5…0
inputs are faster than vinp|n18…6 inputs.
For both types of inputs, it is possible to achieve the maximum sampling frequency, but
under certain conditions (depending either from the resolution mode (selres) and from the
output impedance of the signal source) the sampling period should be delayed during the
necessary clock cycles to guarantee the sampling precision (Figure 7).
Figure 7 - N: Resolution, that is selectable with selres.
The following graphics indicates the number of wait cycles (k), necessary for a wide range of
RI(signal source output resistance) values, for both fast and slow inputs and depending on
the resolution mode (selres).
Please note that these graphics refer to the additional sampling clock cycles. In the
situations where k=0, the sampling period is 1.5 × fclk.
A detailed overview of the sampling time needed for different source impedances and ADC
resolutions in shown in Appendix A table, for the worst case conditions (slow process corner,
avdd = 1.8V, dvdd = 1.62V, Tjunction= -40°C, fclk=70MHz, vrefp=avdd). The sampling time
presented in Appendix A refers to the minimum sampling time to ensure the sampling
precision for each resolution mode.
tsocst tsochld
tdata
Sample Vin(j)
clk
sel4..0
soc
eoc
b11... b0
Internal
S/H
Select Vin(j) channel
Output Data j-1
wait 1 wait k
N+2 1 2
Hold Vin(j)
sob b11-N
(sample j-1)
tdatas
teocr
LSB of sample j-1
b10-N
(sample j-1)

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 18-30
Figure 8 - Additional clock cycles (k) as a function of the signal source output resistance
RI(kΩ). The results presented in this graphic were measured under nominal conditions
(typical process corner, avdd = 3.3V, dvdd = 1.8V, Tjunction= 50°C, fclk=70MHz,
vrefp=avdd).
Figure 9 - Additional clock cycles (k) as a function of the signal source output resistance
RI(kΩ). The results presented in this graphic were measured under worst case conditions
(slow process corner, avdd = 1.8V, dvdd=1.62V, Tjunction=-40°C, fclk=70MHz, vrefp=avdd).
0
1
10
100
1000
0.1 1.0 10.0 100.0
Additional n' of clock cycles
Rin(kΩ)
6bit mode - SLOW input
6bit mode - FAST input
8 bit mode - SLOW input
8bit mode - FAST input
10bit mode - SLOW input
10bit mode - FAST input
12bit mode - SLOW input
12bit mode - FAST input
0
1
10
100
1,000
0.1 1.0 10.0 100.0
Additional n' of clock cycles
Rin (kΩ)
6bit mode - SLOW input
6bit mode - FAST input
8 bit mode - SLOW input
8bit mode - FAST input
10bit mode - SLOW input
10bit mode - FAST input
12bit mode - SLOW input
12bit mode - FAST input

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 19-30
8Digital Offset Calibration
Adigital block aids the measurement and correction the offset voltage of the ADC. The
calibration cycle is started as shown in the figure below. First it is necessary to reset the
digital calibration block, placing resetcal at high for, at least, one clock cycle (a clock falling
edge must occur when this signal is high). The startcal signal, whose minimum duration is
also one clock cycle (a clock falling edge must occur when this signal is high), should be
activated 3 clock cycles minimum after the resetcal signal has been deactivated. The calon
is placed at high when the calibration starts and returns to low, when it ends.
Figure 10 - Start of Calibration Cycle
The input of the ADC is reconfigured such that the inputs (after the input selection
multiplexer) are connected internally insuring that a voltage corresponding to the ideal code
„0‟ is sampled. This reconfiguration depends on the ADC input Mode. In this way, before the
calibration cycle, the ADC should be placed in single-ended or differential input mode (by
controlling seldiff signal) for single-ended (seldiff=L) or differential (seldiff=H), respectively.
Part of the input capacitor array is controlled by the successive approximation circuitry
(which is the same used to obtain the output code in normal operation) to measure and
cancel the offset voltage. Every offset voltage measurement/cancellation cycle is performed
using 7 bits (bvos0...bvos6),which allows to correct offset voltages up to +/- 64 LSBs, and
lasts for 8 clock cycles.
To decrease the effect of electrical random noise, the digital block performs an average of
results obtained in 8 consecutive offset measurement cycles: (bvos0...bvos6)avg. Afterwards,
in normal operation, the digital block applies (bvos0...bvos6)avg to the capacitor array, so that
the offset voltage is removed.
The figure below shows the timing diagram of the full calibration cycle. The result from the 1st
offset measurement cycle is ignored. A complete calibration cycle lasts 81 clock cycles.
If the startcal signal is still high when calon goes low (end of calibration), a new calibration
cycle is started.
Before and during calibration cycle, soc signal must remain low. After the calibration cycle is
finished (calon goes low), the soc signal can be held at the high logic value, at any time, to
begin a conversion cycle.
resetcal pulse length
1 clk cycle minimum
clk
1 2 3
resetcal
startcal
calon
resetcal-to-startcal time
3 clk cycles minimum startcal pulse length
1 clk cycle minimum

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 20-30
Figure 11 - Full calibration cycle timing diagram
The calibration value can be loaded externally when loadcal signal is high.
After setting loadcal to high, the offset calibration word is loaded into the internal registers
(bvosi6…0). In the next clock falling edge, bvos6…0 is updated with the external calibration
word.
The loadcal should be asserted for at least one clock cycle. Below is the timing diagram for
the loadcal operation. The minimum setup (tsetup) time is 1.5ns and hold (thold) time is 2ns
for loadcal signal. Taking this into account, loadcal can only be changed when clock is low.
The loadcal functionality is useful during Deep Power Down Mode but also if the user needs
to store different calibration values (e.g., for single-ended and differential input mode). By
ensuring the timing constrains between loadcal and soc (in the figure below bvos<6:0> are
updated in the first clock falling edge after soc detection) it is possible to perform the loadcal
operation for successive conversions cycles. This can be useful if the application demands
successive conversion cycles and at the same time changing between single-ended and
differential input mode.
Figure 12 –Loadcal operation.
1 2 . . . 8
. . .
. . .
9
1st offset
measurement cycle
10
. . .
2nd offset
measurement cycle
. . .
. . .
80 81
9th offset
measurement cycle
(bvos6...bvos0)avg
. . .. . .
. . . . . .
1000000
Calibration Cycle
. . .. . .
Output Datan
clk
resetcal
startcal
c
a
l
o
n
bvos6...bvos0
b11...b0
3
. . . . . .
eoc
17 18 19
. . .
. . .
. . .
. . .
. . .
. . .
. . .
72 73 74
. . .
. . .
. . .
. . .
. . .
. . .
. . .
calon
. . .
soc
loadcalcal pulse length
1 clk cycle minimum
clk
External calibration value
loadcal
bvosi<6:0>
bvos<6:0> Sampled external calibration value with the clock falling edge
tholdtsetup
eoc
soc