Synopsys TSMC180 Product guide

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 1-30
DWC ADC 12b5M SAR, TSMC180
Databook
3640tg -12-bit, 5MSPS SAR ADC with differential 19:1 InputMux
Version 1.9
April 2012

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 2-30
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DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 3-30
Contents
1Features............................................................................................................................... 4
2General Description............................................................................................................ 4
3Functional Diagram............................................................................................................ 4
4Specifications...................................................................................................................... 5
5Pin Description................................................................................................................... 8
6Operating Modes.............................................................................................................. 10
Start-Up Sequence................................................................................................................ 10
Deep power down mode ..................................................................................................... 11
Power-down Mode .............................................................................................................. 11
Standby Mode...................................................................................................................... 12
Normal Operation................................................................................................................ 12
Current Consumption during Normal Operation............................................................... 12
Internal Voltage Regulator................................................................................................... 13
7Timing Diagrams.............................................................................................................. 14
8Digital Offset Calibration ................................................................................................. 19
10 Application Notes......................................................................................................... 23
Cell Placement...................................................................................................................... 23
Power Supplies .................................................................................................................... 23
System Level Clock Issues ................................................................................................... 24
Routing of Analog and Reference Signals ........................................................................... 24
ESD / Latch-Up................................................................................................................... 24
11 Cell Routing Constrains................................................................................................ 25
12 Connections to the IO PAD ring................................................................................... 26
13 PCB Guidelines............................................................................................................. 29
Appendix A –Minimum Sampling Time –(Worst case conditions)...................................... 30

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 4-30
1Features
2General Description
TSMC 180nm G CMOS technology
Selectable 12 bit, down to 6 bit Resolution
5 MSPS Conversion Rate
Single-Ended or Differential Input
19:1 Multiplexed Inputs
6 high speed inputs
13 low speed inputs
3.6V down to 1.8V Analog Power Supply
1.8V ± 10% Digital Power Supply
Current Consumption:
18uA at 10kSPS
240uA at 1MSPS
1.1mA at 5MSPS
Core Cell Area: 0.25 mm2
This macro-cell is a power and area optimized
Successive-Approximation ADC, having the
resolution selectable between 12, 10, 8 and 6 bit. It
is instantiated in a CMOS 180nm G process.
To maximize flexibility there are serial and parallel
data outputs, and input pins are provided to apply
an external reference voltage, which defines the full-
scale input range. This reference voltage can be the
analog power supply, for rail-to-rail operation.
An internal voltage regulator is included in order to
improve performance when the digital power supply
is connected to the digital core power supply.
A digital calibration algorithm is implemented to
reduce the offset voltage. Furthermore both
differential and single-ended signals can be
processed.
An analog multiplexer is added to enable selection
from a number of inputs.
This cell is suitable to serve as an auxiliary ADC of
a microprocessor, as a house-keeping converter for
digital applications and broadband wireless
communications.
3Functional Diagram
bvos
for test
vinp0
resetadc
sel
soc
clk
enadc
avdd
agnd
SAR
ADC
dvdd_ldo
b11..b0
19:1
MUX
eoc
dgnd
agndref
vrefp
sob
selres
dislvl
enctr
vinn0
vinp1
vinn1
…
vinp18
vinn18
calon
seldiff
dvdd
startcal
resetcal
bypasscal
loadcal
scan interface
atstbus
enldo
bvosi
LDO

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 5-30
4Specifications
Parameter
Conditions
MIN
TYP
MAX
Unit
Technology
No analog options
TSMC180nmG CMOS, with
3.3V IO devices
Minimum metal stack
supported
5m_3x1n
Metal stack available in
DWDL
5m_3x1n , 6m_4x1n
Area
-
0.25
796 x 314
mm2
µm*µm
Standard Cell Library
(TSMC) TCB018GBWP7T Rev. 270a
TSMC180nm Core Library
Resolution
selres=11
selres=10
selres=01
selres=00
12
10
8
6
Bit
Junction temperature
-
-40
+50
+125
ºC
Analog Input
Full-scale input range
seldiff=L
agndref
vrefp
V
seldiff=H
2*(vrefp –agndref)
Vppdiff
Input signal common mode
(only for differential mode)
seldiff=H
(vrefp + agndref)/2
V
Input sampling capacitance (CS)1
No parasitic
capacitances included
5
pF
Analog Biasing
Positive reference voltage(vrefp)
avdd>= 2V
2
avdd
avdd
V
avdd< 2V
avdd
avdd
avdd
V
Negative referencevoltage (agndref)
0
0
0.1
V
Digital Output
Logic Family
CMOS
-
Output Logic Coding
Unsigned Binary:
BottomScale: b11..b0=0h
Top Scale (selres=11): b11..b0=FFFh
Top Scale (selres=10): b11..b2=3FFh
Top Scale (selres=01): b11..b4=FFh
Top Scale (selres=00): b11..b6=3Fh
-
Timing Characteristics
Input clock frequency (fclk)
0.14
70
72
MHz
Sampling rate (fs)
selres=11
selres=10
selres=01
selres=00
0.01
0.012
0.014
0.0175
5
5.83
7
8.75
5.14
6
7.2
9
MSPS
Conversioncycle
selres=11
selres=10
selres=01
selres=00
14
12
10
8
CLK cycles
Clock duty cycle
-
45
50
55
%
Data latency
selres=11
selres=10
selres=01
selres=00
12.5
10.5
8.5
6.5
CLK cycles
Power up time
Fromenadc=L, enldo=L
To enadc=L, enldo=H
(LDO start-up –tup_ldo)
3
5
10
µs
Fromenadc=L,enldo=H
To enadc=H, enldo=H
(ADCstart-up –tup_adc)
1
Conversion
cycles

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 6-30
Parameter
Conditions
MIN
TYP
MAX
Unit
Timing Characteristics (Continued)
clk falling edge to sampling delay (tsd)
-
4.5
ns
socsetup time beforeclkrising edge (tsocst)
-
0
ns
soc hold time afterclkrising edge (tsochld)
-
5
ns
clk rising edge to eoc rising edge delay time
(teocr)
With a 250 fF load
3
ns
clk rising edge to eoc falling edge delay time
(teocf)
With a 250 fF load
3
ns
Valid data out delay after eoc rising edge
(tdata)
With a 250 fF load
1
ns
Valid serial data output delay after clk falling
edge (tdatas)
With a 250 fF load
5
ns
loadcal hold time after clk falling edge
(tloadcalhold)
-
2
ns
loadcal setup time before clk rising edge
(tloadcalsetup)
-
1.5
ns
Power Supply Requirements
Analog Supply Voltage
1.8
3.3
3.6
V
Digital Supply Voltage
1.62
1.8
1.98
V
Current Consumption, Fs=5MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=H
-
-
1100
100
-
-
µA
Current Consumption, Fs=1MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=H
-
-
240
20
-
-
µA
Current Consumption, Fs=10kSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=H
-
-
17
1
-
-
µA
Current Consumption, Fs=5MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=L
-
-
1000
100
-
-
µA
Current Consumption, Fs=1MSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=L
-
-
220
20
-
-
µA
Current Consumption, Fs=10kSPS 1,3 avdd
dvdd
enadc=H, soc=H, seldiff=L
-
-
17
1
-
-
µA
Current Consumption, Fs=5MSPS 2,3 avdd
dvdd
enadc=H, soc=L,seldiff=x
-
-
180
70
-
-
µA
Current Consumption, Fs=1MSPS 2,3 avdd
dvdd
enadc=H soc=L,seldiff=x
-
-
50
13
-
-
µA
Current Consumption, Fs=10kSPS 2,3 avdd
dvdd
enadc=H soc=L,seldiff=x
-
-
17
1
-
-
µA
Power down Current Consumption3avdd
dvdd
enadc=L, enldo=L, dislvl=H
(deep power down mode)
-
-
1
0.5
-
-
µA
Power down Current Consumption3avdd
dvdd
enadc=L, enldo=L, dislvl=L
(power down mode)
-
-
1
1
-
-
µA
Power down Current Consumption3avdd
dvdd
enadc=L, enldo=H, dislvl=L
(standby mode)
-
-
15
1
-
-
µA
Note 1 –Successive conversion mode (soc signal always set to high, check section 7)
Note 2 –soc signal set to low, waiting f or a conv ersion (check section 7)
Note 3 –avdd current consumption includes current consumption through vrefp

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 7-30
avdd = 3.3V, dvdd = 1.8V, Tjunction= 50°C, fclk=70MHz, fin=50kHz, selres=11 (12-bit mode), seldiff=L (single-ended mode), vrefp=avdd,
agndref=0, enldo=H.
Parameter
Conditions
MIN
TYP
MAX
Unit
DNL
1.0
LSB
INL
2.0
LSB
SINAD4
68
dBFS
Offset error
Calibration enabled
Calibration disabled
2
64
LSB
LSB
Total unadjusted error
Calibration enabled
5
LSB
Note 4- Value measured with a –0.5dBFS input signal and then extrapolated tofull scale.

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 8-30
5Pin Description
Pin Name
I/O
Type
Function
vinp18 .. 0
I
Analog
Analog input signals
In differential input mode (seldiff=H), vinp18...vinp1are the positive inputs, vinn18...vinn1 are
the negative inputs.
vinp0 available only forsingle ended input mode.
vinn18 .. 0
I
Analog
Analog input signals
In single ended input mode (seldiff=L), the negative input vinn0 must beconnected to
ground.
vrefp
I
Analog
Positive ReferenceVoltage,
The reference voltage must be applied externally to the vrefp pin, in order to define theADC
full scale input range.
This pin presents aswitchedcapacitive load to its driver, that will be around 3pF inworst
case.The switching frequency is theclockfrequency. The vrefp input impedancewill vary
through theconversion cycle, between the described 3pF and a negligible capacitorvalue of
around 1fF.
agndref
I
Analog
Negative ReferenceVoltage
The reference groundvoltage must be applied externally to the agndref pin, in order to define
the ADCfull scale inputrange
atstbus
I/O
Analog
Internal voltage regulator analog probing testsignal.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
selres1 .. 0
I
Digital
Selects theADCresolution:
selres=006-bit mode
selres=01 8-bit mode
selres=10 10-bit mode
selres=1112-bit mode
seldiff
I
Digital
Selects theADCinput mode (18 selectable inputs are available in both configurations,
vinp0|n0 is available onlyfor single-ended mode):
seldiff=L single ended inputs
seldiff=H differential input
dislvl
I
Digital
(3.3V)
This digital input signalmust have 3.3 V levels (avdd).
This signal is usedfor two purposes:
1. When there is no digital supply (dvdd) but the analogsupply (avdd) it is powered on,
activating this signal (dislvl = H) prevents current consumption on analog supply (avdd)
during digital supply (dvdd) startup.
2. This signal is also used tocontrol the powerswitching of dvdd inside the IP, defining the
deep power down mode.
sel4..0
I
Digital
Input multiplexer control signals:
- vinp|n0selected when sel4..0=0H
- vinp|n18selectedwhensel4..0=12H;
Under ADC test mode itis mandatory to have access to this signal, directlyfrom chip pinout
or throughregisters.
resetadc
I
Digital
Reset of internal buffers and registers (Active H).
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
soc
I
Digital
Start-of-conversionsignal(Active H). Starts the conversioncycle on the nextclk rising edge.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
clk
I
Digital
Clock Input.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
enadc
I
Digital
Enable ADC(enadc=Hnormal operation).
enldo
I
Digital
Enable internal voltage regulator (enldo=Hnormal operation).
enctr2..0
I
Digital /
Test
Digital signals to enable internalanalog programmability modes used for test purposes. In
normal operation thesesignals should be connected in to gnd.
Under ADC test mode itis mandatory to have access to this signal, directlyfrom chip pinout
or throughregisters.

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 9-30
Pin Name
I/O
Type
Function
b11..0
O
Digital
Parallel Output Bits. The MSB is b11; the LSB is b0in 12-bit mode, b2in 10-bit mode,b4 in
8-bit mode and b6in 6-bit mode.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
sob
O
Digital
Serial Output Bit (startingfromthe MSB).
eoc
O
Digital
End-of-conversion. The rising edge indicates thatconversion terminated and output data is
valid.
Under ADC test mode itis mandatory to have direct access to this signal fromchip pinout or
through registers.
bvos6..0
O
Digital
Outputs of the digital offsetcalibration block.
bvosi6..0
I
Digital
Input of the digital offset calibration block
bypasscal
I
Digital
Signal that bypasses the offset calibration block (Active H). In this mode bvos6…0 is set to
1000000.
loadcal
I
Digital
Signal that loads the offsetcalibrationword into the internal registers (Active H)
startcal
I
Digital
Signal that starts the offset calibrationcycle (Active H).
resetcal
I
Digital
Reset of internal registers of the digital offsetcalibration block (Active H).
calon
O
Digital
Indicates if theADCis in calibration mode (Active H).
scanclk
I
Digital
Scan chain clocksignal. Used to capture the data andshift the patterns throughthe chain.
scanen
I
Digital
Selects between capture(scanen = L) and shift(scanen = H) modes.
scanmode
I
Digital
Configures digital offsetcalibration block toscan test mode (Active H).
scanreset
I
Digital
Scan chain reset.
scanin
I
Digital
Scan chain input.
scanout
O
Digital
Scan chain output.
avdd, agnd
I/O
Power
Top and BottomAnalog Power Supplies (3.3V).
dvdd, dgnd
I/O
Power
Top and Bottom Digital Power Supplies (1.8V).
dvdd_ldo
I/O
Analog
Internal voltage regulator output(enldo=H). With enldo=L (internal voltage regulator bypass)
the power signalmust be supplied externally(1.8V).

DWC ADC 12b5MSAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 10-30
6Operating Modes
This section describes the power-up sequence and the various operating modes that the
DWC ADC 12b5MSAR, TSMC180
Table 2 –SAR ADC operating modes.
Mode
Configuration
selres1..0
seldiff
sel4..0
dislvl
enldo
enadc
resetadc
soc
bypasscal
startcal
loadcal
resetcal
Deep Pow er-down
X
X
X
1
0
0
X
X
X
X
X
X
Power-down
X
X
X
0
0
0
X
X
X
X
X
X
Standby
X
X
X
0
1
0
X
X
X
X
X
X
Normal Operation –Single-ended
X
0
X
0
1
1
0
X
X
0
0
0
Normal Operation –Differential
X
1
X
0
1
1
0
X
X
0
0
0
Calibration –Single-ended
X
0
X
0
1
1
0
0
0
0
0
0
Calibration –Differential
X
1
X
0
1
1
0
0
0
0
0
0
Bypass Calibration
X
X
X
0
1
1
0
X
1
0
0
0
Load Calibration
X
X
X
0
1
1
0
X
0
0
1
0
The following start-up sequence should be followed during system startup:
1. During the power up time of the supply voltages, ensure that enldo=L, enadc=L and
soc=L;
2. Power up both dvdd and avdd supplies;
3. Once the power supplies are stable set enldo=H and wait for the internal voltage
regulator start-up;
4. Set the resetcal signal to high during one clock cycle. There is no need to wait for the
internal voltage regulator start-up time to set resetcal to high. This signal can be set
to high right after the power supplies are stable. The only demand is to set it to high
during one clock cycle before the next step (enadc=H);
5. Set enadc=H;
6. Set the resetadc signal to high during one clock cycle;
7. For applications that require a low offset, trigger a calibration cycle using startcal, as
described in Section 8. After the calibration is complete the ADC is ready to receive
analog inputs.