SYSTEMATICS GENERAL CORPORATION T-5101 User manual

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TABLE OF CONTENTS
Paragraph
Section I - Specification
Introduction ------------------------------------- 1-1
T-5l0l Specification ----------------------------- 1-3
Section II - Programming
Microcontroller Programming ----------------------
Instruction Set for T-5l0l Microcontroller -------
Flag Control -------------------------------------
Literal Control ----------------------------------
Asynchronous Receiver/Transmitter Control --------
Transmission Longitudinal Checking ---------------
Tri-State Bus Control ----------------------------
Display Control ----------------------------------
Utility Register Control -------------------------
Section III - Theory of Operation
Introduction -------------------------------------
Cathode Ray Tube Display -------------------------
Quick Reference Guide ----------------------------
Main Circuit Board -------------------------------
Power Supply -------------------------------------
Keyboard ----------------------------------.-------
Normal Keyboard Operation ------------------------
Escape Sequences ---------------------------------
Formatting Aids ----------------------------------
Data Editing Operation ---------------------------
Data Interface -----------------------------------
Data Transmission --------------------------------
Special Function Keys ----------------------------
Status Displays ----------------------------------
Section IV - Monitor Description
2-1
2-12
2-23
2-24
2-25
2-25
2-25
2-26
2-27
3-1
3-1
3-3
3-5
3-5
3-6
3-6
3-12
3-12
3-14
3-18
3-18
3-21
3-21
Monitor Electrical Specifications ---------------- 4-1
Data Display Specifications ---------------------- 4-2
Environmental Specifications --------------------- 4-3
Human Factors Specifications --------------------- 4-3
Controls ----------------------------------------- 4-3
Theory of Operation ------------------------------ 4-6
Section V - Maintenance and Failure Analysis
Care of the T-5l0l -------------------------------
External Adjustments --~--------------------------
Disassembly --------------------------------------
Internal Adjustments -----------------------------
Philosophy of Failure Analysis -------------------
Troubleshooting the Display ----------------------
Maintenance of Main Logic Board and Power Supply -
5-1
5-1
5-3
5-13
5-19
5-22
5-24

TABLE OF CONTENTS (cont)
Paragraph
Section VI - Scheduled Maintenance
Scheduled Maintenance ------------------------------ 6-1
Safety Precautions --------------------------------- 6-7
Section VII - Schematic Drawings and Diagrams ----------- 7-1
Section VIII - Renewal Parts Information ---------------- 8-1

Table
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
3-1
3-2
3-4
3-5
3-6
3-7
3-8
4-1
4-2
5-1
5-2
5-3
5-4
LIST OF TABLES
T-5l0l Functional Units ------------------------
Table of Register Usage ------------------------
T-5l0l Instruction Set -------------------------
Random Access Memory Control -------------------
RAM Address Control ----------------------------
ROM Instruction Execution Sequence Control -----
Table of Conditions ----------------------------
Table of Condition Significance ----------------
Table of Flags ---------------------------------
Asynchronous Transmitter/Receiver Control ------
Tri-State Bus Control --------------------------
Keyboard Operation -----------------------------
Binary Codes -----------------------------------
Formatting Aids --------------------------------
Absolute Cursor Positioning --------------------
Block Transmission Control ---------------------
Special Functions ------------------------------
Status Displays --------------------------------
Input Data Specifications ----------------------
CRT Display Specifications ---------------------
Baud Rate Selections --------------------- ------
T-5l01 Failure Analysis Guide ------------------
Logic Board Terminal Identification Chart ------
Tri-State Bus Location -------------------------
2-10
2-11
2-14
2-16
2-17
2-18
2-19
2-21
2-24
2-25
2-26
3-8
3-11
3-13
3-17
3-20
3-22
3-23
4-1
4-2
5-13
5-21
5-25
5-27

Figure
1-1
2-1
2-2
3-1
3-2
3-3
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
6-1
LIST OF FIGURES
T-5l0l Interactive Display Terminal ------------
T-5l0l Data Flow Block Diagram -----------------
T-5l0l Asynchronous Receiver/Transmitter -------
T-5l0l Functional Block Diagram ----------------
Character Format -------------------------------
Keyboard ---------------------------------------
Synchronization and Blanking Generator Waveforms
External Controls ------------------------------
Video Shield Retaining Screws ------------------
Rear Cover Retraining Screws -------------------
Logic Assembly Interconnections ----------------
Logic Power Supply Shields ---------------------
Logic Power Supply -----------------------------
Video Enclosure --------------------------------
Chassis Cabling --------------------------------
Internal Controls ------------------------------
CRT Mounting (Right Side) ----------------------
CRT Mounting (Left Side) -----------------------
Voltage Waveforms for Display ------------------
Video Circuit Board Component Location ---------
Main Logic Board Layout ------------------------
Program Display --------------------------------
7-1 thru
Page
1-2
2-1
2-3
3-2
3-4
3-7
4-5
5-2
5-4
5-5
5-6
5-8
5-9
5-10
5-11
5-14
5-15
5-16
5-12
5-24
5-30
6-6
7-21 Schematics -7 Configuration -------------------- 7-3
7-22 thru
7-44 Schematics -13 Configuration -------------------
7-45 thru
7-46 Keyboard Schematic -----------------------------
7-47
7-48
7-49
7-50
7-51
7-52
7-53
Keyboard Interface Assembly --------------------
Wiring Diagram ---------------------------------
Logic Power Supply -----------------------------
Wiring Pk1ll2 ----------------------------------
Video Schematic --------------------------------
Video Wiring -----------------------------------
Power Supply Layout ----------------------------
7-27
7-49
7-51
7-52
7-53
7-54
7-55
7-56
7-57

SECTION I
T-SIOI Specification
INTRODUCTION
The purpose of this manual is to provide operation and
maintenance information for the T-SIOI Interactive Display
Terminal.
The scope of the material provided is sufficient in all
aspects of operation and maintenance of the equipment.
The T-SIOI consists of cable-interconnected assemblies.
This unit is in turn connected to a computer by an additional
interface cable.
The T-5101 Interface Display Terminal is shown in
Figure 1-1.
1-1

(
(
I
FigUl:'e 1-1.

T-5l0l SPECIFICATIONS
Display
80 Character Lines 24
Character positions 1920
Character Set 96 ASCII {Upper Case}
Screen Phosphor White (P4)
Face Plate Etched
Refresh Rate 60 pages/Second
Protected Fields Reduced Intensity
Status Displays 8
Control Characters Display 31
Blinking Field Rate 4 per second
Security Fields Display Suppressed
Page Roll Up
Cursor
Format
Controls
Data Transmission
Code
Parity
Reverse Video Block
Forespace, Backspace
Upline, Downline, New
Line, Return, Home, Tab
Backtab, position
Addressing, Position
Reading
Asynchronous ASCII
10 unit code
Even
1-3

Data Transmission
Interface
Rates
Duplex
Modes
Keyboard
RS-232-C
110, 150, 300, 600, 1200,
2400, 4800, 9600 Baud
Full and Half
Conversational
Block
Line, Page or
Message (all or
foreground)
construction Separate
Character and Control Keys 68
Cursor and. Format Keys 14
Numeric Keys Pad 14
Function Keys 16
Transmission Send Control
Keys Page, Line, Message
Interlocking Two Key rollover
Key Operation 2 ounce
Lighted Mode Keys Shift Lock, Write Protect
Program, Conversation,
Page Edit
Memory
Storage Capacity
Security Locations
Control Character Storage
1920 Characters
Display Suppressed
Direct from Keyboard
or Computer
1-4

Memory
Protected Fields Character Protect Bit
Data Editing
Keyboard Editing
Character Type over, Insert, Delete
Line Insert, Delete, Erase to
End of line
Page Clear all or foreground
to NUlls or Spaces, Erase
to End of Page (Replace
Allor Foreground with
NUlls or Spaces)
Protected Fields Reduced Intensity
Computer Controlled Editing All of Above with Receipt
of ESC Sequences
Tempest
Complies with NACSEM
5100, As Modified By
AFNAG-9A
Physical Characteristics
Dimensions
Display
Keyboard
Weight
A-C Power Requirement
Environment
l4.12"H X 20.S"W x l8"L
4"H X 20.S"W x 9"L
55 Ibs.
115 Volt, 60 Hz
c 0
5-50 C; 41-122 F
5-95% Relative Humidity
without Condensation
1-5

SECTION II
MICROCONTROLLER PROGRAMMING
The organization of data transmission and control for the T-5101
interactive data display terminal is given in the data flow block
diagram, Figure 2-1 below. A detailed description of control
and programming for the microcontro11er follows. Specific details
of the terminal logic and control devices are contained in schematic
drawing 129361, sheets 7-1 through 7-22, contained in Section 7.
FROM: 1
KEYBOARDJ
MEMORY iDISPLAY
SECTION
1--------,- .. SECTION
(RAM)
CONTROL
SECTION
ROM ~----------
ASYNCHRONOUS
RECEIVER
TRANSMITTER
to:
1- ...... IDEO
ONITOR
INTERFACE
TO/FROM:
--t'COMPUTER
and/or
li,RINTER
Figure 2-1. T-5101 Main Circuit Board
Data Flow Block Diagram
T-5101 Data oraanization is based on random access memorv time sharina
between control section and display section, with the di~p1a·y
section given highest priority for the refresh function and the
control section given secondary priority. The display function
utilize random access memory 27% of the time leaving 73% for the
control functions. This sharing organization provid~s the T-5101
with greater reliability of terminal operations since fewer com-
ponents are required.
2-1

Data information and control commands
between the various logic sections and
(memory, control, timing) bus.
are transferred internally
components over a tri-state
Keystroke signals enter the main logic board as 8 bit parallel data
codes, along with strobe signals. However, data received from an
interfacing computer is received as ASCII seven bit serial data.
The logic board has a serial-parallel converter to translate serial
ASCII codes to parallel codes as well as a FIFO buffer to allow
time for operations which are longer than inter character intervals
in fast transmission rate environments.
The transmitter/receiver is an LSI/UART chip which (I) accepts
serial ASCII 10 or 11 unit codes (word structure option is strappable)
from an RS-232-C standard interface or 20 rna current loop optional
interface and (2) transmits an equivalent 8 bit parallel code as
a data word to the control section. Furthermore, the universal
asynchronous transmitter/receiver (UART) also decodes 8 bit words
received from the T-SlOl control section and transmits serial ASC II
over the data signal interface. See Figure 2-2 for additional
details of the UART.
Information transfer is controlled in the T-SlOl by the microcontrol
logic commanded by codes stored in a preprogrammed ROM. The standard
T-5l0l terminal functions are contained in four pages (256-8 bit
words/pages) of microcode, with printer extension option requiring
an additional page, and terminal polling option needing two pages.
The display memory section consists of 16 random access memory (RAM)
chips, providing storage capacity of 2048 8-bit words. This memory
provides useful character storage of 1920 characters, 24 lines of
80 characters each. The memory section also contains conversion
logic necessary to monitor display cursor position.
The display section consists of four main subsections, i.e.,
(1) Character Generator, (2) RoW Refresh Logic, (3) Cursor Display
Logic, and (4) Timing Control. In addition to the above functions,
display section also provides control for reduced luminance
(protected fields) and 8-status indicator displays.
Actual registers used in the T-5l01 micro controller code are s~
marized and listed in Table 2-2.
2-2

VSS l1i _
~
VOD 131
~
...
VGG 121
. ~
T"""'SAlIJl E" HOLDING
P,[GI:'if[R
'RC
1001
LOAD
THAl
1211
TIMtNG
THRI
l.O
1211
tOlHROl
SID
SHIFT
TR!
1141
~-+---------. ~?
PI
EPE
WORO LENGTH
SElECT
~s~ <>-----Mr---
I~JP!JT STRUCTURE
MOS DEVICE "Au ACTS AS AN
INTERW>.L PUU.·Up RESISTOR
TO V~;S ~ Vce WHICH SIASES
OFf THE CASCODE DEVICE OF
THE TTL OUTPUT IN THE
HIGH·l::VEL OUTPUT STATE.
IN TilE LO'N·LEVEL OUTPUT
ST t.TE THE TTL OUTPUT DE·
VICE SIN:<S THE CURHENT
SUF'?UED BY DEVICE "Au.
P!
lUI
FE
lUI
NOTE: ~ TRI·STAT-E OUTPUT
Vee
'---v----'
lnlCAl nL
OllT'eT
I
Vss (lVISTRATEl· vee
-----1-----
'_-y--J
T~t4~lA INPUT
I
~--..,_--J '---y--'
TR1telA OVT1UT TYriCAl nl
IN?UT
DATA
RECEIVED
DEUCl
DR
1191
Sf 0
ORR
1111
OUTPUT STR!JCTURE
DEVICES "s" (I, "c" COMPRISE
A PUSH·PUll OUTPUT '3UFFER.
IN THE lOW·lEVEL STATE,
OUTPUT TRANSISTOR "e" IS
"ON" AND CASCODE DEVICE
"S" IS OFF. iN T:-iE HIGH·
LEVEL STATE, THE OPPOSITE
IS TRUE. IN TH:: DISCON
NECTED
STATE, nOTH "S"
AND "e" ARE TUnNED OFF
CAUSING THE OUTPUT NODE
TO FLOAT.
Figure 2-2. T-5101 Asynchronous Receiver/Transmitter (UART)
2-3

PIN
NUMBER
1
2
3
4
5-12
13
NAME
VSS
POWER
VGG
POWER
VDD
POWER
RECEIVER
REGISTER
DISCONNECT
RECEIVER
HOLDING
REGISTER
DATA
SUPPLY
SUPPLY
SUPPLY
PARITY ERROR
SYMBOL
VSS
VGG
VDD
RRD
RRS
RRl
PE
FUNCTION
+5 volts Supply
-12 volts Supply
Ground
A high-level input voltage.
V
IH
applied to this line
disconnects the RECEIVER
HOLDING REGISTER
outputs from
the RRS-RRt data outputs
(pins 5-12 •
The contents of the RECEIVER
HOLDING REGISTER
appear on
these lines in parallel if
a low-level input voltage,
V
IL
, is applied to RRD.
Program control selection of
a word length less than eight
(S) bits will cause the most
significant bits of the
character to be forced to a
1ow-level output voltage, VOL.
The character will be right
justified. RRl (pin 12) is
the least significant bit of
the character.
The status of the parity
verification circuit appears
on this line, if a low-level
input voltage, V
IL
, is applied
to the STATUS FLAGS DISCONNECT
(pin 16) control line. Wired
OR capability is provided on
this line allowing PE lines
from other arrays to be OR
tied. A high level ou~put
voltage,VOHI on this line
(under the conditions above)
Figure 2-2. T-5l0l Asynchronous Receiver/Transmitter (UART) (Continued)
2-4

PIN
NUMBER
14
15
FRAMING
ERROR
OVERRUN
ERROR
SYMBOL
FE
OE
FUNCTION
indicates a PARITY ERROR
in the received parity bit
as programmed by the EVEN
PARITY ENABLE control line
(pin 39). The status is
updated each time a charac-
ter is transferred from the
RECEIVER REGISTER to the
RECEIVER HOLDING REGISTER.
The status of the STOP bit
detection circuit appears
on this line if a low-level
input voltage, VIL' is
applied to the STATUS FLAG
DISCONNECT (pin 16) control
line. Wired OR capability
is provided on this line
allowing FE lines from other
arrays to be OR tied. A high-
level output voltage, VOH'
indicates that the received
character has no valid STOP
bit, i.e., the bit following
the parity bit is not a high-
level input voltage, V
IH
•
The status of the DATA RECEIVED
circuit appears on this line of
a low-level input voltage, VIL'
is applied to the STATUS FLAG
DISCONNECT (pin 16) control
line. Wired OR capability is
provided on this line allowing
OE lines from other arrays to
be OR-tied. A high level out-
put voltage, VOH, indicates that
the previously received charac-
ter was not read (DR line not
reset) before the present
character was transferred to
the RECEIVER HOLDING REGISTER.
Figure 2-2.
T-5l0l Asynchronous Receiver/Transmitter (UART) (Continued)
2-5

PIN
NUMBER
16
17
18
19
20
21
22
STATUS FLAGS
DISCONNECT
RECEIVER REGIS-
TER CLOCK
DATA RECEIVED
RESET
DATA RECEIVED
RECE IVER INPUT
~STER RESET
TRANSMITTER
HOLDING
REGISTER
EMPTY
SYMBOL
SFD
RRC
ORR
DR
RI
MR
THRE
FUNCTION
A high-level input voltage,
V
IH
, applied to this pin
disconnects the PE, FE, OE,
DR and THRE circuit outputs.
This clock is sixteen (16)
times faster than the desired
receiver shift rate.
A low-level input voltage, V
IL
,
applied to this line resets
the DR line.
A high level output voltage,
V
OH
' indicates that an entire
character has been received
and transferred to the
RECEIVER HOLDING REGISTER.
Serial input data received on
this line enters the RECEIVER
REGISTER at a point determined
by the character length, parity,
and the number of stop bits.
A high-level input voltage, V
IH
,
must be present when data is
not being received.
This line is strobed to a high-
level input voltage, V
IH
, to
clear the logic after power
turn-on. It resets all registers
and sets the serial output line
to a high-level output voltage.
VOH·
A high-level output Voltage, V
OH
'
on this line indicates the
TRANSMITTER HOLDING REGISTER has
transferred its contents to the
TRANSMITTER REGISTER and may
be loaded with a new character.
Figure 2-2. T-5l0l Asynchronous Receiver/Transmitter (UART) (Continued)
2-6

PIN
NUMBER
23
24
25
NAME
TRANSMITTER
HOLDING
REGISTER
LOAD
TRANSMITTER
REGISTER
EMPTY
TRANSMITTER
REGISTER
OUTPUT
SYMBOL
THRL
TRE
TRO
FUNCTION
A
low-level input voltage,
V
IL
, applied to this line
enters a character into the
TRANSMITTER HOLDING REGISTER.
A
transition from a low-level
input voltage. V
IL
, to a high
level input voltage. VIH,
transfers the character into the
TRANSMITTER REGISTER if it is
not in the process of trans-
mitting a character. If a
character is being transmitted,
the transfer is delayed until
its transmission is completed.
Upon completion, the new charac-
ter is transferred simultaneously
with the initiation of the
serial transmission of the new
character.
A high-level output voltage.
V
OH
• on this line indicates that
the TRANSMITTER R::;GISTER has
completed serial transmission
of a full character including
STOP bit(s). It remains at this
level until the start of trans-
mission of the next character.
The contents of the TRANSMITTER
REGISTER (START
bit DATA bits,
PARITY bit, and STOP bit), are
serially shifted out on this
line. This line will remain
at a high level output voltage,
V
OHQ
when no data is being
transmitted. A start of trans-
mission is defined as the trans-
ition from a high-level output
voltage, VOL' of the start bit.
Figure 2-2.
T-5101 Asynchronous Receiver/Transmitter (UART) (Continued)
2-7

PIN
NUMBER
26-33
34
35
NAME
TRANSMITTER
REGISTER
DATA INPurS
CONTROL
REGISTER
LOAD
PARITY
INHIBIT
SYMBOL
CRL
PI
FUNCTION
Parallel 8-bit characters are
input on these lines into the
TRANSMITTER HOLDING REGISTRR
with THRL Strobe. If a charac-
ter of less than 8 bits has
been selected (by WLSl and WLS2),
the least significant bits only
are accepted. The character is
right justified into the least
significant bit. A high-level
input voltage, V
IH
, will cause
a high-level output voltage,
V
OH
' to be transmitted.
A high-level input voltage,
V , on the line loads the
C6~TROL REGISTER with the
control bits (WLSl' WLS
2,
EPE,
PI, SBS). This line may be
strobed or hard wired to a
high-level input voltage, VIH-
A high-level input voltage,
V
IH
, on this line inhibits the
parity generation and verification
circuits. The STOP bites) will
immediately follow the last data
bit on transmission if parity is
uninhibited. A low-level input
voltage, V
IL
, enables the
parity generation and verifica-
tion circuits_ PI will, when a
high-level input voltage, V
IH
,
is applied, also clamp the PE line
(pin 13) to a low-level output
voltage, VOL-
36 STOP BIT(S) SBS This line selects the number of
SELECT STOP bits generated after the
PARITY bit durinJ transmission. A
high-level input voltage, V
IH
, on
this line selects two STOP bits,
and a low-level input voltage, V
IL
,
selects a single STOP bit.
Figure 2-2. T-5l0l Asynchronous Receiver/Transmitter (UART) (Continu~d)
2-8

PIN
NUMBER
37-38
39
40
WORD
LENGTH
SELECT
EVEN
PARITY
ENABLE
TRANSMITTER
REGISTER
CLOCK
SYMBOL
EPE
TRC
FUNCTION
These two lines select the
character length to be 5, 6,
7, or 8 bits.
WORD LENGTH
5 bits
6 bits
7 bits
8 bits
This line selects either even
or odd PARITY to be generated by
the transmitter and checked by
the receiver. A high-level input
voltage, VIH' selects even
PARITY and a low-level input
voltage, V
1L
, selects odd
PARITY.
This CLOCK is sixteen (16) times
faster than the desired trans-
mitter shift rate.
Figure 2-2. T-5101 Asynchronous Receiver/Transmitter (UART) (Continued)
Information is transferred between functional units by way of the
tristate bus, TSB, under microprogram control. This information
transfer consists of eight-bit characters transmitted in parallel
between the following units.
2-9

Unit
Mnemonic
RCV
KEY
CPR
CPC
LIT
RDR
WDR
LRC
ADD
MACR
INPUT
OUTPUT
CMD
MAR
INn
CNTR
TABLE 2-1. T-S10l FUNCTIONAL UNITS
From
From
From
From
From/To
From
To
From/To
From
From/To
From/To
From/To
From/To
Unit
External Serial Source via UART Receiver
Keyboard
Cursor position row register
Cursor position character register
Eight bit literal register
Random access page buffer via the Read
Data Register
Random access page buffer via the write
Data Register
Modulo 2 adder and accumulator (7 bits)
Switch (8 bits) internal, manually set
Random access page buffer row counter
(address register high order five bits)
Utility Register*
Utility Register*
Utility Register*
Margin Register
Indicator Register
Counter Register
* Unused in Standard T-S101
2-10