Systran SCRAMNet+ VME3U Application guide

SCRAMNet+Network
VME3U
Hardware Reference
Document No. D-T-MR-VME3U###-A-0-A2

FOREWORD
The information in this document has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. SYSTRAN reserves the right to make changes without notice.
SYSTRAN makes no warranty of any kind with regard to this printed material, including, but not limited
to, the implied warranties of merchantability and fitness for a particular purpose.
Copyright 1995 SYSTRAN Corporation. All rights reserved.
SCRAMNetis a registered trademark of SYSTRAN Corporation.
VAXand VMSare trademarks of DIGITAL Equipment Corporation.
UNIXis a registered trademark of Novell.
STis a registered trademark of AT&T.
Revised: November 15, 1995
SYSTRAN Corporation
4126 Linden Avenue
Dayton, OH 45432-3068
[phone]

Copyright 1995, SYSIRAN Corp. 0-1VME3U H/W REFERENCE
TABLE OF CONTENTS
1.0 HOW TO USE THIS MANUAL ................................................................................................5
1.1 Scope.............................................................................................................................5
1.2 Organization..................................................................................................................5
1.3 Appendices....................................................................................................................5
1.4 Related Documentation.................................................................................................6
2.0 INTRODUCTION.................................................................................................................. 2-1
2.1 Overview................................................................................................................... 2-1
2.1.1 Network Features..................................................................................... 2-1
2.1.2 Options..................................................................................................... 2-2
2.1.3 VME3U Board Features ......................................................................... 2-2
2.2 VMEbus Specification Level................................................................................... 2-3
2.3 Addressing Compatibility ......................................................................................... 2-3
2.3.1 Memory ................................................................................................... 2-3
2.3.2 Control/Status Registers .......................................................................... 2-3
2.3.3 I/O............................................................................................................ 2-3
2.4 Data Transfer Capability........................................................................................... 2-3
2.4.1 Memory ................................................................................................... 2-3
2.4.2 I/O............................................................................................................ 2-3
2.5 Interrupt Capability................................................................................................... 2-3
2.6 P1 Connector............................................................................................................. 2-4
2.7 Utility Software......................................................................................................... 2-4
2.7.1 SCRAMNet Diagnostics.......................................................................... 2-4
2.7.2 EEPROM Initialization (EPI).................................................................. 2-4
2.7.3 SCRAMNet Monitor ............................................................................... 2-4
3 0 DESCRIPTION....................................................................................................................... 3-1
3.1 Overview................................................................................................................... 3-1
3.2 Shared Memory.........................................................................................................3-1
3.2.1 Dual Port Memory Controller.................................................................. 3-1
3.2.2 Control/Status Registers (CSRs).............................................................. 3-1
3.2.3 Virtual Paging.......................................................................................... 3-3
3.3 FIFO Buffers............................................................................................................. 3-3
3.3.1 Transmit FIFO ......................................................................................... 3-3
3.3.2 Transceiver FIFO..................................................................................... 3-3
3.3.3 Interrupt FIFO.......................................................................................... 3-3
3.3.4 Receiver FIFO .........................................................................................3-3
3.4 Network Ring............................................................................................................ 3-4
3.4.1 Protocol.................................................................................................... 3-4
3.5 Auxiliary Control RAM (ACR) ................................................................................ 3-4
3.6 Interrupts................................................................................................................... 3-5
3.6.1 Network Interrupt WRITEs.....................................................................3-6
3.6.2 Selected.................................................................................................... 3-6
3.6.3 Forced...................................................................................................... 3-8
3.7 External Triggers....................................................................................................... 3-8
3.8 General Purpose Counter/Global Timer.................................................................... 3-8
3.9 LED Status Indicators............................................................................................... 3-9
3.10 Modes of Operation ................................................................................................ 3-9
3.10.1 Data Filter Mode.................................................................................... 3-9
3.10.2 High Performance (HIPRO) Mode........................................................3-9
3.10.3 VME Holdoff Mode.............................................................................3-10

HOW TO USE THIS MANUAL
Copyright 1995, SYSIRAN Corp. 0-2 VME3U H/W REFERENCE
3.10.4 Loopback Modes ................................................................................. 3-10
3.10.5 Write-Me-Last Mode........................................................................... 3-11
3.11 Options.................................................................................................................. 3-11
3.11.1 Electronic Bypass Switch .................................................................... 3-11
3.11.2 Quad Switch......................................................................................... 3-12
3.11.3 Cabinet Kit...........................................................................................3-12
4 0 OPERATION......................................................................................................................... 4-1
4.1 Introduction............................................................................................................... 4-1
4.2 Shared Memory.........................................................................................................4-1
4.2.1 Virtual Paging.......................................................................................... 4-1
4.2.2 Memory Considerations........................................................................... 4-3
4.2.3 Control/Status Registers .......................................................................... 4-3
4.3 Initialization..............................................................................................................4-4
4.4 Network Ring............................................................................................................ 4-4
4.4.1 Message Contents.................................................................................... 4-4
4.4.2 Protocol.................................................................................................... 4-5
4.4.3 Performance............................................................................................. 4-6
4.4.4 Throughput .............................................................................................. 4-7
4.5 Auxiliary Control RAM............................................................................................ 4-7
4.6 Interrupt Controls...................................................................................................... 4-9
4.6.1 Interrupt Options...................................................................................... 4-9
4.7 Interrupt Conditions................................................................................................ 4-10
4.7.1 Network Data WRITE........................................................................... 4-10
4.7.2 Network Error........................................................................................ 4-14
4.7.3 Interrupt Handling ................................................................................. 4-15
4.8 External Triggers..................................................................................................... 4-15
4.9 General Purpose Counter/Timer .............................................................................4-15
4.9.1 Available Modes....................................................................................4-16
4.9.2 Rollover/Reset ....................................................................................... 4-16
4.9.3 Presetting Values ................................................................................... 4-16
4.10 Modes of Operation .............................................................................................. 4-16
4.10.1 Data Filter............................................................................................ 4-16
4.10.2 HIPRO Mode....................................................................................... 4-17
4.10.3 Loopback Modes ................................................................................. 4-19
4.10.4 Node Insert Mode................................................................................ 4-24
4.10.5 VME Holdoff Mode.............................................................................4-25
4.10.6 Write-Me-Last Mode........................................................................... 4-27
4.11 Quad Switch.......................................................................................................... 4-27
5 0 CSR DESCRIPTIONS...........................................................................................................5-1
5.1 Description................................................................................................................ 5-1
6 0 PHYSICAL FEATURES ....................................................................................................... 6-1
6.1 CSR Address Switches (S1-S5)................................................................................ 6-2
6.2 Resolution Bus Switch (S6)...................................................................................... 6-2
6.3 External Trigger Connections (J1/J2) ....................................................................... 6-2
6.4 Ground Jumper (J3.................................................................................................... 6-2
6.5 Variable Length Enable (VL_EN) Jumper (J4) ........................................................6-2
6.6 Software Compatibility (SW_CMPT) Jumper (J5)................................................... 6-2
6.7 Media Card Connection (J302)................................................................................. 6-2
6.8 EEPROM WRITE (J303).......................................................................................... 6-2
6.9 EEPROM READ (J304)...........................................................................................6-3
6.10 Mezzanine Memory Card Connection (J305)......................................................... 6-3
6.11 LED Status Indicators............................................................................................. 6-3
6.11.1 Insert...................................................................................................... 6-3
6.11.2 Carrier Detect.........................................................................................6-3

Copyright 1995, SYSIRAN Corp. 3 VME3U H/W REFERENCE
APPENDICES
APPENDIX A - CSR SUMMARY.............................................................................................. A-1
APPENDIX B - CABINET KIT ...................................................................................................B-1
APPENDIX C - SPECIFICATIONS.............................................................................................C-1
APPENDIX D - HOST ACCESS TIMING................................................................................. D-1
APPENDIX E - CONFIGURATION AIDS .................................................................................E-1
APPENDIX F - ACRONYMS......................................................................................................F-1
APPENDIX G - GLOSSARY...................................................................................................... G-1
FIGURES
Figure 2-1 VME3U Board............................................................................................................ 2-2
Figure 3-1 Functional Diagram.................................................................................................... 3-2
Figure 3-2 ACR/Memory Access................................................................................................. 3-5
Figure 3-3 Outgoing Interrupt...................................................................................................... 3-7
Figure 3-4 Incoming Interrupt...................................................................................................... 3-7
Figure 4-1 Memory Sharing With Virtual Paging........................................................................ 4-2
Figure 4-2 Transmit Interrupt Logic........................................................................................... 4-11
Figure 4-3 Receive Interrupt Logic............................................................................................ 4-13
Figure 4-4 Data Filter Logic....................................................................................................... 4-18
Figure 4-5 Monitor and Bypass Mode........................................................................................ 4-20
Figure 4-6 Wire Loopback Mode............................................................................................... 4-21
Figure 4-7 Mechanical Switch Loopback Mode ........................................................................ 4-22
Figure 4-8 Fiber Optic Loopback Mode..................................................................................... 4-24
Figure 4-9 Insert Mode............................................................................................................... 4-25
Figure 4-10 Quad Switch ........................................................................................................... 4-26
Figure 4-11 Interrupt Service Routine....................................................................................... 4-28
Figure 6-12 VME3U Layout........................................................................................................ 6-1
TABLES
Table 4-1 EEPROM Table........................................................................................................... 4-4
Table 4-2 SCRAMNet+ Message Contents .................................................................................4-5
Table 4-3 ACR Functions............................................................................................................. 4-8
Table 4-4 Interrupt Controls......................................................................................................... 4-9
Table 4-5 Interrupt Error Conditions.......................................................................................... 4-14
Table 4-6 General Purpose Counter/Timer Modes..................................................................... 4-16
Table 4-7 Monitor and Bypass Mode States ..............................................................................4-20
Table 4-8 Wire Loopback Mode States...................................................................................... 4-21
Table 4-9 Mechanical Switch Loopback Mode States............................................................... 4-22
Table 4-10 Fiber Optic Loopback Mode States..........................................................................4-23
Table 4-11 Node Insert Mode ....................................................................................................4-24
Table 5-2 CSR1 - Error Indicators ............................................................................................... 5-6
Table 5-3 CSR2 - Node Control................................................................................................... 5-8
Table 5-4 CSR3 - Node Information.......................................................................................... 5-10
Table 5-5 CSR4 - Interrupt Address (LSP)................................................................................ 5-10
Table 5-6 CSR5 - Interrupt Address and Status (MSP).............................................................. 5-10

HOW TO USE THIS MANUAL
Copyright 1995, SYSIRAN Corp. 0-4 VME3U H/W REFERENCE
Table 5-7 CSR6 - Interrupt Vector (Memory Update)............................................................... 5-11
Table 5-8 CSR7 - Interrupt Vector (SCRAMNet+Error) ......................................................... 5-11
Table 5-9 CSR8 - General SCRAMNet+Extended Control Register....................................... 5-12
Table 5-10 CSR9 - SCRAMNet+Interrupt On Error Mask ..................................................... 5-13
Table 5-11 CSR10 - SCRAMNet+Shared Memory Address (LSW) ....................................... 5-14
Table 5-12 CSR11 - SCRAMNet+Shared Memory Address (MSW)......................................5-14
Table 5-13 CSR12 - Virtual Paging Register............................................................................. 5-15
Table 5-14 CSR13 - General Purpose Counter/Timer................................................................ 5-16
Table 5-15 CSR14 - Reserved.................................................................................................... 5-17
Table 5-16 CSR15 -VME Interrupt Priority Level (IRQ) .......................................................... 5-17
Table 5-17 CSR16 -HIPRO READ Control Bits Register......................................................... 5-18

Copyright 1995, SYSIRAN Corp. 5 VME3U H/W REFERENCE
1. HOW TO USE THIS MANUAL
1.1 Scope
This document is a reference manual for the SCRAMNet+VME3U host interface board.
This document provides a physical and functional description of the SCRAMNet+
VME3U board designed for a VME based host system.
This information is intended for systems designers, engineers and network installation
personnel.
The reader should have at least a systems level understanding of general computer
processing, of memory and hardware operation, and of the specific host processor.
1.2 Organization
This document is divided into six sections: Introduction, Description, Installation,
Operation, Control/Status Register Description, and Physical Features.
Introduction: An overview of the SCRAMNet+VME3U product and
host interface compatibility.
Description: A functional description of the SCRAMNet+network
node.
Installation: Procedures for unpacking, configuring and installing the
SCRAMNet+VME3U node board.
Operation: A discussion of how the node works; including
Control/Status registers, Shared Memory, Message
Passing, Data Filtering, Interrupt Initialization and
Handling, Auxiliary Control RAM, and other features.
CSR Description: A detailed explanation of all the Control/Status
Registers.
Physical Features: A description of the physical features of the
SCRAMNet+VME3U board.
1.3 Appendices
A - CSR Summary: A quick reference summary of the Control/Status
Registers by bit, function and name.
B - Cabinet Kit: A discussion of how the board is connected to the
cabinet kit.
C - Specification Summary: General board specifications, Bus Voltage Specification,
part number breakdown, and Fiber Optic Bypass Switch
specifications.

HOW TO USE THIS MANUAL
Copyright 1995, SYSIRAN Corp. 0-6 VME3U H/W REFERENCE
D - Host Access Timing: A discussion of timing coordination between the board
and host.
E - Configuration Aids: Control/Status Register (CSR) Reference Sheet and
network configuration form.
F - Glossary: A glossary of words, phrases and terms used in the
reference manual.
1.4 Related Documentation
SCRAMNet Network Utilities User Manual (Doc. Nr. C-T-MU-UTIL####-A-0-A1) - A
user’s manual for the SCRAMNet Classic, SCRAMNet+, and SCRAMNet+
hardware diagnostic software, SCRAMNet+EEPROM initialization software, and the
SCRAMNet Network Monitor.
SCRAMNet Network Programmer’s Reference Guide(Doc. Nr. D-T-MR-PROGREF#-A-0-
A2) - Acollection of routines to assist SCRAMNet users with application development.