Systran SCRAMNet+ VME3U Application guide
SCRAMNet+Network
VME3U
Hardware Reference
Document No. D-T-MR-VME3U###-A-0-A2
FOREWORD
The information in this document has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. SYSTRAN reserves the right to make changes without notice.
SYSTRAN makes no warranty of any kind with regard to this printed material, including, but not limited
to, the implied warranties of merchantability and fitness for a particular purpose.
Copyright 1995 SYSTRAN Corporation. All rights reserved.
SCRAMNetis a registered trademark of SYSTRAN Corporation.
VAXand VMSare trademarks of DIGITAL Equipment Corporation.
UNIXis a registered trademark of Novell.
STis a registered trademark of AT&T.
Revised: November 15, 1995
SYSTRAN Corporation
4126 Linden Avenue
Dayton, OH 45432-3068
(513) 252-5601
Copyright 1995, SYSIRAN Corp. 0-1VME3U H/W REFERENCE
TABLE OF CONTENTS
1.0 HOW TO USE THIS MANUAL ................................................................................................5
1.1 Scope.............................................................................................................................5
1.2 Organization..................................................................................................................5
1.3 Appendices....................................................................................................................5
1.4 Related Documentation.................................................................................................6
2.0 INTRODUCTION.................................................................................................................. 2-1
2.1 Overview................................................................................................................... 2-1
2.1.1 Network Features..................................................................................... 2-1
2.1.2 Options..................................................................................................... 2-2
2.1.3 VME3U Board Features ......................................................................... 2-2
2.2 VMEbus Specification Level................................................................................... 2-3
2.3 Addressing Compatibility ......................................................................................... 2-3
2.3.1 Memory ................................................................................................... 2-3
2.3.2 Control/Status Registers .......................................................................... 2-3
2.3.3 I/O............................................................................................................ 2-3
2.4 Data Transfer Capability........................................................................................... 2-3
2.4.1 Memory ................................................................................................... 2-3
2.4.2 I/O............................................................................................................ 2-3
2.5 Interrupt Capability................................................................................................... 2-3
2.6 P1 Connector............................................................................................................. 2-4
2.7 Utility Software......................................................................................................... 2-4
2.7.1 SCRAMNet Diagnostics.......................................................................... 2-4
2.7.2 EEPROM Initialization (EPI).................................................................. 2-4
2.7.3 SCRAMNet Monitor ............................................................................... 2-4
3 0 DESCRIPTION....................................................................................................................... 3-1
3.1 Overview................................................................................................................... 3-1
3.2 Shared Memory.........................................................................................................3-1
3.2.1 Dual Port Memory Controller.................................................................. 3-1
3.2.2 Control/Status Registers (CSRs).............................................................. 3-1
3.2.3 Virtual Paging.......................................................................................... 3-3
3.3 FIFO Buffers............................................................................................................. 3-3
3.3.1 Transmit FIFO ......................................................................................... 3-3
3.3.2 Transceiver FIFO..................................................................................... 3-3
3.3.3 Interrupt FIFO.......................................................................................... 3-3
3.3.4 Receiver FIFO .........................................................................................3-3
3.4 Network Ring............................................................................................................ 3-4
3.4.1 Protocol.................................................................................................... 3-4
3.5 Auxiliary Control RAM (ACR) ................................................................................ 3-4
3.6 Interrupts................................................................................................................... 3-5
3.6.1 Network Interrupt WRITEs.....................................................................3-6
3.6.2 Selected.................................................................................................... 3-6
3.6.3 Forced...................................................................................................... 3-8
3.7 External Triggers....................................................................................................... 3-8
3.8 General Purpose Counter/Global Timer.................................................................... 3-8
3.9 LED Status Indicators............................................................................................... 3-9
3.10 Modes of Operation ................................................................................................ 3-9
3.10.1 Data Filter Mode.................................................................................... 3-9
3.10.2 High Performance (HIPRO) Mode........................................................3-9
3.10.3 VME Holdoff Mode.............................................................................3-10
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3.10.4 Loopback Modes ................................................................................. 3-10
3.10.5 Write-Me-Last Mode........................................................................... 3-11
3.11 Options.................................................................................................................. 3-11
3.11.1 Electronic Bypass Switch .................................................................... 3-11
3.11.2 Quad Switch......................................................................................... 3-12
3.11.3 Cabinet Kit...........................................................................................3-12
4 0 OPERATION......................................................................................................................... 4-1
4.1 Introduction............................................................................................................... 4-1
4.2 Shared Memory.........................................................................................................4-1
4.2.1 Virtual Paging.......................................................................................... 4-1
4.2.2 Memory Considerations........................................................................... 4-3
4.2.3 Control/Status Registers .......................................................................... 4-3
4.3 Initialization..............................................................................................................4-4
4.4 Network Ring............................................................................................................ 4-4
4.4.1 Message Contents.................................................................................... 4-4
4.4.2 Protocol.................................................................................................... 4-5
4.4.3 Performance............................................................................................. 4-6
4.4.4 Throughput .............................................................................................. 4-7
4.5 Auxiliary Control RAM............................................................................................ 4-7
4.6 Interrupt Controls...................................................................................................... 4-9
4.6.1 Interrupt Options...................................................................................... 4-9
4.7 Interrupt Conditions................................................................................................ 4-10
4.7.1 Network Data WRITE........................................................................... 4-10
4.7.2 Network Error........................................................................................ 4-14
4.7.3 Interrupt Handling ................................................................................. 4-15
4.8 External Triggers..................................................................................................... 4-15
4.9 General Purpose Counter/Timer .............................................................................4-15
4.9.1 Available Modes....................................................................................4-16
4.9.2 Rollover/Reset ....................................................................................... 4-16
4.9.3 Presetting Values ................................................................................... 4-16
4.10 Modes of Operation .............................................................................................. 4-16
4.10.1 Data Filter............................................................................................ 4-16
4.10.2 HIPRO Mode....................................................................................... 4-17
4.10.3 Loopback Modes ................................................................................. 4-19
4.10.4 Node Insert Mode................................................................................ 4-24
4.10.5 VME Holdoff Mode.............................................................................4-25
4.10.6 Write-Me-Last Mode........................................................................... 4-27
4.11 Quad Switch.......................................................................................................... 4-27
5 0 CSR DESCRIPTIONS...........................................................................................................5-1
5.1 Description................................................................................................................ 5-1
6 0 PHYSICAL FEATURES ....................................................................................................... 6-1
6.1 CSR Address Switches (S1-S5)................................................................................ 6-2
6.2 Resolution Bus Switch (S6)...................................................................................... 6-2
6.3 External Trigger Connections (J1/J2) ....................................................................... 6-2
6.4 Ground Jumper (J3.................................................................................................... 6-2
6.5 Variable Length Enable (VL_EN) Jumper (J4) ........................................................6-2
6.6 Software Compatibility (SW_CMPT) Jumper (J5)................................................... 6-2
6.7 Media Card Connection (J302)................................................................................. 6-2
6.8 EEPROM WRITE (J303).......................................................................................... 6-2
6.9 EEPROM READ (J304)...........................................................................................6-3
6.10 Mezzanine Memory Card Connection (J305)......................................................... 6-3
6.11 LED Status Indicators............................................................................................. 6-3
6.11.1 Insert...................................................................................................... 6-3
6.11.2 Carrier Detect.........................................................................................6-3
Copyright 1995, SYSIRAN Corp. 3 VME3U H/W REFERENCE
APPENDICES
APPENDIX A - CSR SUMMARY.............................................................................................. A-1
APPENDIX B - CABINET KIT ...................................................................................................B-1
APPENDIX C - SPECIFICATIONS.............................................................................................C-1
APPENDIX D - HOST ACCESS TIMING................................................................................. D-1
APPENDIX E - CONFIGURATION AIDS .................................................................................E-1
APPENDIX F - ACRONYMS......................................................................................................F-1
APPENDIX G - GLOSSARY...................................................................................................... G-1
FIGURES
Figure 2-1 VME3U Board............................................................................................................ 2-2
Figure 3-1 Functional Diagram.................................................................................................... 3-2
Figure 3-2 ACR/Memory Access................................................................................................. 3-5
Figure 3-3 Outgoing Interrupt...................................................................................................... 3-7
Figure 3-4 Incoming Interrupt...................................................................................................... 3-7
Figure 4-1 Memory Sharing With Virtual Paging........................................................................ 4-2
Figure 4-2 Transmit Interrupt Logic........................................................................................... 4-11
Figure 4-3 Receive Interrupt Logic............................................................................................ 4-13
Figure 4-4 Data Filter Logic....................................................................................................... 4-18
Figure 4-5 Monitor and Bypass Mode........................................................................................ 4-20
Figure 4-6 Wire Loopback Mode............................................................................................... 4-21
Figure 4-7 Mechanical Switch Loopback Mode ........................................................................ 4-22
Figure 4-8 Fiber Optic Loopback Mode..................................................................................... 4-24
Figure 4-9 Insert Mode............................................................................................................... 4-25
Figure 4-10 Quad Switch ........................................................................................................... 4-26
Figure 4-11 Interrupt Service Routine....................................................................................... 4-28
Figure 6-12 VME3U Layout........................................................................................................ 6-1
TABLES
Table 4-1 EEPROM Table........................................................................................................... 4-4
Table 4-2 SCRAMNet+ Message Contents .................................................................................4-5
Table 4-3 ACR Functions............................................................................................................. 4-8
Table 4-4 Interrupt Controls......................................................................................................... 4-9
Table 4-5 Interrupt Error Conditions.......................................................................................... 4-14
Table 4-6 General Purpose Counter/Timer Modes..................................................................... 4-16
Table 4-7 Monitor and Bypass Mode States ..............................................................................4-20
Table 4-8 Wire Loopback Mode States...................................................................................... 4-21
Table 4-9 Mechanical Switch Loopback Mode States............................................................... 4-22
Table 4-10 Fiber Optic Loopback Mode States..........................................................................4-23
Table 4-11 Node Insert Mode ....................................................................................................4-24
Table 5-2 CSR1 - Error Indicators ............................................................................................... 5-6
Table 5-3 CSR2 - Node Control................................................................................................... 5-8
Table 5-4 CSR3 - Node Information.......................................................................................... 5-10
Table 5-5 CSR4 - Interrupt Address (LSP)................................................................................ 5-10
Table 5-6 CSR5 - Interrupt Address and Status (MSP).............................................................. 5-10
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Table 5-7 CSR6 - Interrupt Vector (Memory Update)............................................................... 5-11
Table 5-8 CSR7 - Interrupt Vector (SCRAMNet+Error) ......................................................... 5-11
Table 5-9 CSR8 - General SCRAMNet+Extended Control Register....................................... 5-12
Table 5-10 CSR9 - SCRAMNet+Interrupt On Error Mask ..................................................... 5-13
Table 5-11 CSR10 - SCRAMNet+Shared Memory Address (LSW) ....................................... 5-14
Table 5-12 CSR11 - SCRAMNet+Shared Memory Address (MSW)......................................5-14
Table 5-13 CSR12 - Virtual Paging Register............................................................................. 5-15
Table 5-14 CSR13 - General Purpose Counter/Timer................................................................ 5-16
Table 5-15 CSR14 - Reserved.................................................................................................... 5-17
Table 5-16 CSR15 -VME Interrupt Priority Level (IRQ) .......................................................... 5-17
Table 5-17 CSR16 -HIPRO READ Control Bits Register......................................................... 5-18
Copyright 1995, SYSIRAN Corp. 5 VME3U H/W REFERENCE
1. HOW TO USE THIS MANUAL
1.1 Scope
This document is a reference manual for the SCRAMNet+VME3U host interface board.
This document provides a physical and functional description of the SCRAMNet+
VME3U board designed for a VME based host system.
This information is intended for systems designers, engineers and network installation
personnel.
The reader should have at least a systems level understanding of general computer
processing, of memory and hardware operation, and of the specific host processor.
1.2 Organization
This document is divided into six sections: Introduction, Description, Installation,
Operation, Control/Status Register Description, and Physical Features.
Introduction: An overview of the SCRAMNet+VME3U product and
host interface compatibility.
Description: A functional description of the SCRAMNet+network
node.
Installation: Procedures for unpacking, configuring and installing the
SCRAMNet+VME3U node board.
Operation: A discussion of how the node works; including
Control/Status registers, Shared Memory, Message
Passing, Data Filtering, Interrupt Initialization and
Handling, Auxiliary Control RAM, and other features.
CSR Description: A detailed explanation of all the Control/Status
Registers.
Physical Features: A description of the physical features of the
SCRAMNet+VME3U board.
1.3 Appendices
A - CSR Summary: A quick reference summary of the Control/Status
Registers by bit, function and name.
B - Cabinet Kit: A discussion of how the board is connected to the
cabinet kit.
C - Specification Summary: General board specifications, Bus Voltage Specification,
part number breakdown, and Fiber Optic Bypass Switch
specifications.
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D - Host Access Timing: A discussion of timing coordination between the board
and host.
E - Configuration Aids: Control/Status Register (CSR) Reference Sheet and
network configuration form.
F - Glossary: A glossary of words, phrases and terms used in the
reference manual.
1.4 Related Documentation
SCRAMNet Network Utilities User Manual (Doc. Nr. C-T-MU-UTIL####-A-0-A1) - A
user’s manual for the SCRAMNet Classic, SCRAMNet+, and SCRAMNet+
hardware diagnostic software, SCRAMNet+EEPROM initialization software, and the
SCRAMNet Network Monitor.
SCRAMNet Network Programmer’s Reference Guide(Doc. Nr. D-T-MR-PROGREF#-A-0-
A2) - Acollection of routines to assist SCRAMNet users with application development.
Copyright 1995, SYSIRAN Corp. 2-1 VME3U H/W REFERENCE
2. 0 INTRODUCTION
2.1 Overview
SCRAMNet+(Shared Common RandomAccess Memory Network) is a
communications network geared toward real-time applications, and based on a replicated,
shared-memory concept.
The SCRAMNet+VME3U host interface node board is backwards-compatible with the
original SCRAMNet Classic product with the exception of the GOLD Ring
communication protocol. The programmable byte-swapper is no longer available on
VMEbus-based products.
The SCRAMNet+VME3U board requires a single slot in the VMEbus chassis.
The SCRAMNet+VME3U board base address for Control/Status Registers (CSRs) is
switch selectable. The 128 KB on-board shared memory can be upgraded to 512 KB,
1 MB, 2 MB, 4 MB or 8 MB random access memory (RAM). Installing any memory
upgrade overrides the on-board 128 KB memory.
2.1.1 Network Features
A ring topology with 150 Mbit/s line transmission rate.
A “Data-Filter” that allows only data stored in shared memory that has changed to be
communicated to the other network nodes.
Field Upgrade Memory Options up to 8 MB of replicated, shared memory for each node
processor.
BURST Mode protocol (Error Correction Disabled) with fixed-length message packets of
82 bits.
BURST PLUS Mode communication based on variable length message packet size to a
maximum of either 256 bytes or 1024 bytes.
PLATINUM Mode protocol (Error Correction enabled) with fixed-length message
packets of 82 bits.
PLATINUM PLUS Mode communication based on variable length message packet size
to a maximum of either 256 bytes or 1024 bytes.
256 node capacity on each ring.
No operating or system software required to support network protocol.
No network-dependent application software required.
INTRODUCTION
Copyright 1995, SYSIRAN Corp. 2-2 VME3U H/W REFERENCE
Figure 2-1 VME3U Board
2.1.2 Options
Optional paired fiber optic or coax transmission media
Fiber Optic Bypass Switch for ring continuity when node power is off.
Quad Switch—A switching control device that controls up to four nodes or sub- rings,
eliminates the need for a separate Fiber Optic Bypass, and functions as a repeater.
2.1.3 VME3U Board Features
Mezzanine board memory upgrade option
General Purpose Counter
Error Interrupt Mask
Dynamic shared memory addressing
Switch selectable CSR Address Selector
Virtual paging for Shared Memory (CSR selectable)
Variable length message packet capability
Dual port memory
Dual vector memory/error interrupt (Single Level Interrupt)
Single Slot Solution
EEPROM initialization
INTRODUCTION
Copyright 1995, SYSIRAN Corp. 2-3 VME3U H/W REFERENCE
2.2 VMEbus Specification Level
The SCRAMNet+VME3U host board was designed in accordance with the VMEbus
specification Revision C.3, ANSI/IEEE Std 1014-1987.
Slave device
SADO24 (No UAT, no BLT)
SRMW16 (D16, D08 (EO))
8-bit vector ROAK
3U single height card size
2.3 Addressing Compatibility
2.3.1 Memory
The shared memory resident on the SCRAMNet+VME3U host interface board must be
located on the A24 standard bus. The memory address selected must be an address
boundary that is a multiple of the shared-memory size, and must be loaded and enabled
through the CSRs.
2.3.2 Control/Status Registers
2.3.3 I/O
Control in the form of CSRs can be located on either the A16 bus or the A24 bus. The
address is set manually using the rotary switches on the board. This is independent of the
shared memory address. The CSRs require 64 contiguous bytes of address space.
2.4 Data Transfer Capability
2.4.1 Memory
Data transfers to the shared memory on the SCRAMNet+VME3U host interface can be
8- or 16-bits wide and may be of the read-modify-write type. If the host needs to pass 32-
bit data to shared memory, it must be accomplished in two 16-bit segments. The host
system does this automatically; transparent to the user. Three-byte unaligned transfers are
not permitted.
2.4.2 I/O
Data transfers to the I/O control area of the SCRAMNet+VME3U host interface can be
8- or 16- bits wide and may be of the read-modify-write type. If the host needs to pass
32-bit data to the Control/Status Registers, it must be accomplished in two 16-bit
segments. The host system does this automatically; transparent to the user. Three-byte
unaligned transfers are not permitted.
2.5 Interrupt Capability
The SCRAMNet+VME3U host interface is an interrupter of the type D08. Interrupt
level 1 through 7 may be selected by setting a value in CSR15. The IRQ is mapped using
a bit-wise format; bit 1 is IRQ 1, bit 2 is IRQ 2, etc. (Bit 0 is not used.) The vector
generated by the node is 8 bits wide. Being an ROAK (Release On interrupt
AcKnowledge) type of interrupter means that the device releases the interrupt request
INTRODUCTION
Copyright 1995, SYSIRAN Corp. 2-4 VME3U H/W REFERENCE
during the interrupt acknowledge cycle. The 8-bit vector address is loaded at CSR6 -
Memory, and CSR7 - Error. If Interrupt-on-Error is not used, CSR7 must contain the
same vector as CSR6.
2.6 P1 Connector
The SCRAMNet+VME3U card’s P1 backplane connector is in accordance with the
VMEbus specifications.
2.7 Utility Software
2.7.1 SCRAMNet Diagnostics
The SCRAMNet Network Hardware Diagnostics are designed to test the functionality of
the hardware. This suite of tests will detect whether it is testing a SCRAMNet Classic
board or a SCRAMNet-LX/SCRAMNet+board and adjust the test menus accordingly.
2.7.2 EEPROM Initialization (EPI)
The EEPROM Initialization program is a SCRAMNet+utility used to simplify
configuration of the network node. The EPI program will store a start-up configuration in
the serial EEPROM which can initialize the node on power up. This initialization
program can be run when the board is installed to set the desired power-up state of the
SCRAMNet+node. EPI is completely menu driven and contains a context-sensitive help
feature.
2.7.3 SCRAMNet Monitor
The SCRAMNet Monitor allows viewing and editing of memory and CSR locations on
the SCRAMNet node. This utility is useful during software development to verify that
the correct values are being written to SCRAMNet memory and CSRs.
Copyright 1995, SYSIRAN Corp. 3-1 VME3U H/W REFERENCE
3. 0 DESCRIPTION
3.1 Overview
The SCRAMNet+Network is a real-time communications network, based on a
replicated, shared-memory concept. Each host processor on the network has access to its
own local copy of shared memory which is updated over a high-speed, serial-ring
network. It is optimized for the high-speed transfer of data among multiple, real-time
computers that are all solving portions of the same real-time problem. The SCRAMNet+
node board can automatically filter out redundant data.
3.2 Shared Memory
In its simplest form, the SCRAMNet+Network system is designed to appear as general-
purpose memory. The use of this memory depends only on the conventions and
limitations imposed by the specific host computer system and operating system. On most
processors, this means that the application program can use this memory in basically the
same way as any other data storage area of memory. The memory cannot be used as
instruction space.
The major difference between SCRAMNet+memory and system memory is that any
data written into SCRAMNet+memory is automatically sent to the same SCRAMNet+
memory location in all nodes on the network. This is why it is also referred to as
replicated shared memory. Agood analogy is the COMMONAREA used by the
FORTRAN programming language. Where the COMMON AREAmakes variables
available to subroutines of a program, SCRAMNet+makes variables available to
processors of a network.
The SCRAMNet+memory size can range from 128 KB on-board memory to 8 MB of
expansion memory. Available options include: 128 KB, 512 KB, 1 MB, 2 MB, 4 MB and
8 MB. No software driver is required except for interrupt handling. When a host
computer writes to the shared memory, the proper handshaking for a memory card is
supplied by the SCRAMNet+node host adapter. The shared memory behaves somewhat
like resident or local memory.
3.2.1 Dual Port Memory Controller
The Dual Port Memory Controller (see Figure 2-1) allows the host to READ from or
WRITE to shared memory with a simultaneous network WRITE to shared memory.
Unless an interrupt has been authorized for that memory address, the host is not aware the
network is writing to shared memory. This is why caching must be disabled for
SCRAMNet memory. If an interrupt has been authorized, the interrupt will then be sent
to the host processor.
3.2.2 Control/Status Registers (CSRs)
The operation of the SCRAMNet+board is controlled by 17 Input/Output (I/O) CSRs.
The location of the CSRs in the computer’s address space is switch selectable. In most
DESCRIPTION
Copyright 1995, SYSIRAN Corp. 3-2 VME3U H/W REFERENCE
NODE
IN
NODE
OUT
AllReads
AllWrites
P1
ASIC
Host
Interface
Logic
Replicated
Shared
Memory
Interrupt
FIFO
Network
Control
Logic
Tranceiver
FIFO
Receiver
Transmitter
Transmitt
FIFO
Dual Port
Memory
Controller
Port 1 - Host
Port 2 - Network
Receiver
FIFO
Figure 3-1 Functional Diagram
DESCRIPTION
Copyright 1995, SYSIRAN Corp. 3-3 VME3U H/W REFERENCE
cases, the mode of operation is set during initialization and remains unchanged during run
time. The CSRs are described in detail in Section 5.
3.2.3 Virtual Paging
All SCRAMNet+nodes use the same 8 MB shared memory map. This feature permits
different SCRAMNet+boards with 4 MB of shared memory or less to be paged into
different sections of the 8 MB memory map. A board with a 4 MB or smaller memory
may be located on any shared memory address boundary that is an even multiple of itself
(e.g. 2 MB can page to 0, 2, 4 or 6 MB address).
3.3 FIFO Buffers
The SCRAMNet+board contains various FIFO buffers used for temporarily storing
information during normal send and receive operation of the node. Refer to Figure 3-1.
3.3.1 Transmit FIFO
The Transmit FIFO is a message holding area for native messages waiting to be
transmitted. Each host write to SCRAMNet+memory may constitute a WRITE to the
Transmit FIFO. (Data Filtering and HIPRO features may interfere with this.) Each
WRITE to the Transmit FIFO contains 21 bits of address (A22-A2), 32 bits of data, and
one bit of interrupt information. The Transmit FIFO can hold up to 1024 WRITEs before
becoming full.
The Transmit FIFO has a 7/8 Full condition indicator (CSR1, bit 2 ON). When the
Transmit FIFO reaches a FULL condition (CSR1, bit 0 ON), one more host WRITE
could cause a message to be lost. To prevent this, the CSR-controllable, built-in
SCRAMNet+feature called VME Holdoff extends the computer WRITE cycle until the
Transmit FIFO is able to empty at least one message.
3.3.2 Transceiver FIFO
This buffer is used to receive foreign messages from the network, and send them on, or to
hold received foreign messages while inserting a native message from the host onto the
network.
Each node is responsible for receiving foreign messages, writing them to its copy of
shared memory, and re-transmitting the message to the next node.
3.3.3 Interrupt FIFO
The Interrupt FIFO contains a 21-bit address (A22 - A2) and a retry status bit for each
shared-memory-based interrupt received. The Interrupt FIFO can hold 1024 interrupt
addresses. This FIFO can be read using CSR4 and CSR5.
3.3.4 Receiver FIFO
The Receiver FIFO is designed as a temporary holding place for incoming foreign
messages while the shared memory is busy servicing a host request. This FIFO is three
messages deep, and is designed so it can never be overrun. Each item in the Receiver
FIFO contains 21 bits of address (A22 - A2), 32 bits of data, and one incoming interrupt
bit. When the messages are 1024 bytes, the initial header information data stays in the
FIFO, the subsequent 4 bytes of data are loaded in, and the address is incremented by
four.
DESCRIPTION
Copyright 1995, SYSIRAN Corp. 3-4 VME3U H/W REFERENCE
3.4 Network Ring
The SCRAMNet+Network is a ring topology network. Data is transmitted at a rate of
150 Mbits/s over dual fiber optic cables. The two lines together produce the incoming
data clock. Due to the network speed and message slot size, the network can
accommodate over 1,800,000 message slots passing by each node every second. There is
an approximate 247 ns (minimum) delay at each node as the message slot works its way
around the ring. The maximum delay depends on the selection of fixed or variable length
message packets. A fixed message packet has a maximum delay of 800 ns, a 256-byte
variable packet is 16 µs, and a 1024-byte variable packet is 62 µs. Delay can be imposed
when a node must complete the transmission of a native message packet before
retransmitting a foreign message packet. A SCRAMNet+ Network can accommodate up
to 256 nodes per network ring.
3.4.1 Protocol
The protocol is a register-insertion methodology and is NOT a token ring. Depending on
the protocol selected, all message packets are the same size or are variable (as in the
PLUS modes), and multiple nodes can transmit data simultaneously. There is no master
node, and all nodes have equal priority for network bandwidth. The message protocol is
designed specifically for real-time applications where data must be passed very rapidly.
When the node operates in BURST or BURST PLUS mode, the node will never re-
transmit its own messages for error correction. When operating in PLATINUM or
PLATINUM PLUS mode, error detection is enabled, and re-transmission can occur.
BURST MODE
BURST mode is an open loop, non-error-corrected communication mode. This mode
allows multiple 32-bit messages per node on the ring at a time. The limited packet length
enhances the data latency characteristics of the network by providing the shortest possible
media access delay. The messages are transmitted as fast as the system will allow.
PLATINUM MODE
PLATINUM mode is BURST mode with error detection enabled. The messages are
transmitted as fast as the system will allow, but error checking is used to detect and re-
transmit corrupted packets.
PLUS MODES
The PLUS mode protocol enhancement can increase the maximum network throughput
from 6.5 MB/sec to approximately 15.2 to 16.7 MB/sec by the use of variable-length
message packets. Each SCRAMNet+message packet has a 50-bit header plus the data.
The user-selectable maximum packet size increases the data size from the normal 32 bits
to either 256 or 1024 bytes of data. Data must be written sequentially.
3.5 Auxiliary Control RAM (ACR)
The Auxiliary Control RAM (ACR) provides a method of external triggering and
interrupt control by offering a choice of four actions to occur when a particular
SCRAMNet+shared-memory address is written into. Each shared-memory location has
its own action or set of actions associated with it.
DESCRIPTION
Copyright 1995, SYSIRAN Corp. 3-5 VME3U H/W REFERENCE
0
1
Shared Memory
ACR Memory
CSR0, bit 4
Host READ/WRITE
request to a specific
32-bit memory address
Byte 0 Byte 1 Byte 2 Byte 3
Byte 0
PHYSICAL
MEMORY CHIP DOES NOT
REALLY EXIST
LEGEND
Figure 3-2 ACR/Memory Access
In Figure 3-2, host CPU READ/WRITE operations are channeled to either SCRAMNet+
memory or to theACR. The ACR is a physically separate memory from the shared
memory. Channeling is based on a user-controlled switch setting and may be toggled to
the desired position by writing to a bit in the SCRAMNet+CSR. When access to the
ACR is enabled, shared memory is not accessible by the host and theACR byte is viewed
as the least significant byte (LSB) of every shared-memory four-byte address. The ACR
bits define what external trigger and/or interrupt action(s) are to be taken whenever
writing to any byte of the SCRAMNet+shared memory 4-byte word.
Only five bits of the ACR are associated with every four-byte word of shared memory
(on even four-byte boundaries). The other 27 bits of the ACR are phantom bits and do not
physically exist.
3.6 Interrupts
SCRAMNet+allows a node processor to receive interrupts from and transmit interrupts
to any node on the network, including the originating node, provided the receiving node
is set up to receive an interrupt message. Interrupts can be generated under two different
conditions:
SCRAMNet+Network data WRITEs to shared memory; and
SCRAMNet+network errors detected on the local node.
SCRAMNet+interrupts usually require a device driver to interface with the node
processor. There must also be a host-dependent interrupt vector placed in CSR6 and
CSR7 identifying the Interrupt Service Routine (ISR). The driver is required primarily to
permit the host processor to handle interrupts from the SCRAMNet device.
DESCRIPTION
Copyright 1995, SYSIRAN Corp. 3-6 VME3U H/W REFERENCE
3.6.1 Network Interrupt WRITEs
FOREIGN MESSAGE
The node can receive a message from another node with the interrupt bit set. If Receive
Interrupt Enable (ACR, bit 0) and Interrupt Mask Match Enable (CSR0, bit 5) are
enabled, the data is written to shared memory and the address is placed on the Interrupt
FIFO.
NATIVE MESSAGE
If the message received was originated by the node, and Write Own Slot Enable (CSR2,
bit 9) and Enable Interrupt on Own Slot (CSR2, bit 10) are enabled, the host has
authorized a Self-Interrupt. The data is written to shared memory and the address is
placed on the Interrupt FIFO.
Network Interrupt WRITEs can be accomplished by two methods:
Selected. Data WRITEs to selected shared memory locations from the network.
Forced. Any data WRITEs to any shared memory from the network.
In either case, the node can be configured to WRITE to itself. This condition is called
“Self Interrupt” .
3.6.2 Selected
The “selected” method requires choosing SCRAMNet+shared-memory locations on
each node to receive and/or to transmit interrupts. These shared-memory locations may
also be used to generate signals to external triggers. The procedure for selecting shared-
memory locations for interrupts and/or external triggers is explained in the paragraph on
the Auxiliary Control RAM, paragraph 3.5.
OUTGOING INTERRUPT
The Outgoing Interrupt is described in Figure 3-3. If both Transmit Interrupt Enable
(ACR, bit 1) and Network Interrupt Enable (CSR0, bit 8) are set, and a data item is
transmitted to any of the selected-interrupt memory locations, then an interrupt message
is sent out on the network. This message will generate interrupts to any processors on the
network that have that same shared-memory location selected to receive interrupts.
INCOMING INTERRUPT
Figure 3-4 demonstrates the process of receiving a message with the interrupt bit set. The
data is written to shared memory and the address is placed in CSR5 and CSR4 to await
being sent to the host. If the Receive Interrupt Enable (ACR, bit 0), Host Interrupt Enable
(CSR0, bit 3), and the Interrupt Memory Mask Match Enable (CSR, bit 5) are set, and
network interrupt data is received for any one of the selected interrupt memory locations
the following occurs:
the data is stored in that location
the SCRAMNet+address of the memory location is placed on the Interrupt FIFO queue,
and
an interrupt is sent to the processor.
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