Teac CR-L600 User manual

CCRR--LL660000
SERVICE MANUAL
CD Receiver
Effective : December, 2002
NOTES
●PC boards shown are viewed from parts side.
●The parts with no reference number or no parts number in the
exploded views are not supplied.
●As regards the resistors and capacitors, refer to the circuit diagrams
contained in this manual.
●£Parts marked with this sign are safety critical components. They
must be replaced with identical components - refer to the appropriate
parts list and ensure exact replacement.
●Parts of [ ] mark can be used only with the version designated.
[J]:JAPAN[E]:EUROPE[UK]:U.K.
注 意
●プリント基板図は部品面を示しています。
●分解図に部番のない部品および品番のない部品は供給できま
せん。
●標準の抵抗、コンデンサーは省略してあります。
回路図を参照してください。
●£印は安全重要部品です。
交換する時は必ず指定の部品を使用してください。
●仕向先
[J]:JAPAN[E]:EUROPE[UK]:U.K.
CONTENTS
1 SPECIFICATIONS ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・2
2 ADJUSTMENTS AND CHECKS ・・・・・・・・・・・・・・・・・・・・・・・・3
3 IC BLOCK DIAGRAMS AND PIN FUNCTIONS ・・・・・・・・6
4 EXPLODED VIEWS AND PARTS LIST ・・・・・・・・・・・・・・・18
5 PC BOARDS AND PARTS LIST ・・・・・・・・・・・・・・・・・・・・・・22
6 INCLUDED ACCESSORIES ・・・・・・・・・・・・・・・・・・・・・・・・・・・27
目次
1仕 様 ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・2
2調整と確認 ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・3
3ICブロック図と端子説明 ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・6
4分解図とパーツリスト ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・18
5基板図とパーツリスト ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・22
6付属品 ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・27
暫定版
Preliminary

1 SPECIFICATIONS
−2−
仕 様
AMPLIFIER Section
Output Power .............................. 30 W/ch (6 ohms, 0.5 %,1 kHz)
Input Sensitivity................................................ 350 mV/47k ohms
Frequency Response ...................... 20 Hz to 20,000 Hz (+1/-3 dB)
TUNER Section
FM Section
Frequency Range .......... 87.50 MHz to 108.00 MHz (50 kHz steps)
Signal-to-Noise Ratio .................... 65 dB (Mono) / 60 dB (Stereo)
AM Section
Frequency Range .................... 522 kHz to 1629 kHz (9 kHz steps)
Signal-to-Noise Ratio............................................................ 35 dB
CD PLAYER Section
Frequency Response .......................... 20 Hz to 20,000 Hz (±2 dB)
Signal-to-Noise Ratio .......................................... more than 85 dB
Wow and Flutter ...................................................... Unmeasurable
GENERAL
Power Requirements............................................ 230 V AC, 50 Hz
Power Consumption .............................................................. 40 W
Power Consumption (standby)................................................ 5 W
Dimension (W x H x D) ................................ 190 x 104 x 349 mm
Weight ................................................................................ 3.0 kg
Standard Accessories .............. Remote Control Unit (RC-864) x 1
Batteries (AA, R6, SUM-3) x 2
AM Loop Antenna x 1
FM Lead-type Antenna x 1
Owner's Manual x 1
Warranty Card x 1
•Design and specifications are subject to change without notice.
•Weight and dimensions are approximate.
■アンプ部
定格出力 .................................... 30W+30W(0.5%,1kHz,6Ω)
入力感度 .................................................................. 350mV/47kΩ
周波数特性 ........................................................ 20Hz〜20,000Hz
■FMチューナー部
受信周波数 ................ 76.0MHz〜90.0MHz(100kHzステップ)
■AMチューナー部
受信周波数........................ 522kHz〜1,629kHz(9kHzステップ)
■CDプレーヤー部
周波数特性 ........................................ 20Hz〜20,000Hz(±2dB)
S/N比 ................................................................................ 85dB以上
ワウフラッター ........................................................ 測定限界値以下
■共通部
電源................................................................ AC100V,50-60Hz
消費電カ ...................................................................................... 40W
消費電力(スタンバイ時) .............................................................. 3W
外形寸法(幅、高さ、奥行) ........................ 190×104×349mm
質量............................................................................................ 3.0kg
付属品 ............................................................................ リモコン×1
乾電池(単3形)×2
FM室内アンテナ×1
AMループアンテナ×1
取扱説明書×1
保証書×1
●仕様および外観は改善のため予告なく変更することがあります。

2 ADJUSTMENTS AND CHECKS
−3−
調整と確認
準備中
Preliminary

−4−
準備中
Preliminary

−5−
準備中
Preliminary

3 IC BLOCK DIAGRAMS AND PIN FUNCTIONS
−6−
ICブロック図と端子説明
P96 (S14)
P95 (S13)
P94 (S12)
P93 (S11)
P92 (S10)
P91 (S9)
P90 (S8)
P87 (S7)
P86 (S6)
P85 (S5)
P84 (S4)
P83 (S3)
P82 (S2)
P81 (S1)
P80 (S0)
P77 (G0)
P76 (G1)
P75 (G2)
P74 (G3)
(SIS) P97
123456789101112131415161718192021222324
55565758596061626364 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VKK
(KEY0) P40
(KEY1) P41
(KEY2) P42
(KEY3) P43
(KEY4) P44
(KEY5) P45
(CIN5/KEY6) P46
(CIN4/KEY7) P47
(CIN3) P50
(CIN2) P51
(CIN1) P52
(CIN0) P53
P54
(PWM/PDO) P55
P73 (G4)
P72 (G5)
P71 (G6)
P70 (G7)
P67 (G8)
(INT0) P10
(INT1) P11
(INT2/TC1) P12
(DVO) P13
P14
(TC2) P15
P16
P17
TEST
(XTIN) P21
(XTIN) P22
RESET
XIN
XOUT
VSS
(INTS/STOP) P20
(INT3/TC3) P30
(TC4) P31
(SCK) P32
(SI) P33
(SO) P34
(HSCK) P35
P36
(HSO) P37
P66 (G9)
P65 (G10)
P64 (G11)
P63 (G12)
P62 (G13)
P61 (G14)
P60 (G15)
VDD
P07
P06
P05
P04
P03
P02
P01
P00
VDD P9
VFT drive circuit (automatic display) Key scan
control
Program counter
Register banks
Stack PointerP S W
Interrupt Controller
System Controller
Standby Controller
Timing Generator
High
frequ.
Low
frequ.
Clock
Generator
Time Base
Timer
16-bit
Timer/Counters
TC1 TC2 TC3 TC4 SIO HSO
8-bit
Timer/Counters
Serial
Interfaces
6-bit A/D
Converter
P4
P47
to
P40
P5
P55
to
P50
P3
P37
to
P30
P1
P17
to
P10
P0
P07
to
P00
P2
P22
to
P20
Inst.
Register
Inst.
Decoder
Watchdog
Timer
Flags
ALU RBS
Program Memory
(ROM)
Data Memory
(RAM)
I/O Ports
P97
to
P90
P8
Output Ports
P87
to
P80
P7
I/O Ports
P77
to
P70
P6
P67
to
P60
Power Supply
VFT Power
Supply
Reset I/O
Test Pin
Resonator
connecting
Pins
VSS
VKK
RESET
TEST
XIN
XOUT
I/O Ports
■ BLOCK DIAGRAM
TMP87PS71AF (IC31)
■ PIN ASSIGNMENTS
(TOP VIEW)

−7−
PIN NO. SYMBOL I/O
1 F_MUTE O FUNCTION MUTE CONTROL PORT
2 REMO I REMOTE CONTROL SENSOR DATA INPUT
3 RDS CLK I
4 RDS DATA O
5 V_SDATA O
6 V_SCLK O
7-
8 CD_M_STBY O CD STAND-BY PORT
9 GND -
10 VSW2 I
11 VSW1 I
12 RESET I RESET INPUT PORT
13 X_IN I
14 X_OUT O
15 GND -
16 BACK_UP I BACK UP MODE CONTROL
17 CD_BUS0 O
18 CD_BUS1 O
19 CD_BUS2 O
20 CD_BUS3 O
21 (DVD)RXDO O CD OPEN CONTROL PORT
22 D_RST O CD CLOSE CONTROL PORT
23 - -
24 TUNER_IN I
25 STEREO_IN I
26 OPLED O LED ON/OFF CONTROL PORT
27 POWER O POWER ON/OFF CONTROL PORT
28 PLL_DATA_IN I PLL DATA INPUT PORT
29 F_STB O
30 F_P_CLK O
31 F_P_DATA O
32 PLL_CE O PLL ENABLE CONTROL PORT
33 VDD - POWER PORT(+5)
34 OPTION(A) O
35 OPTION(B) O
36 OPTION(C) O
37 OPTION(D) O
38 OPTION(E) O
39~65 FIP SEGMENT O
66 VKK(-) - POWER PORT(-30)
67 OPTION I OPTION CONTROL PORT
68 PROTECT I PROTECT INPUT PORT
69 HPIN I HEADPHONE IN/OUT DEFECT PORT
70 CD_PWR O CD POWER PORT
71 CD/RST O CD RESET PORT
72 CD_BUCK O CD BUCK PORT
73 CD/CCE O CD ENABLE CONTROL PORT
74 CD/RW O CD_RW PORT
75 M_OP_M O
76 M_CL_M O
77 KEY2 I
78 KEY1 I
79 SP_ON I SPEAKER ON/OFF PORT
80 T_MUTE O TUNER MUTE PORT
CD DATA BUS PORT
VOLUME CONTROL PORT
CRYSTAL CONNECTION PORT
DESCRIPTION
KEY CONTROL INPUT
MECHA. CONTROL PORT
OPTION/FIP SEGMENT CONTROL PORT
FUNCTION IC CONTROL PORT
TUNED/STEREO DISPLAY CONTROL PORT
VOL.IC CONTROL PORT
RDS CLOCK/DATA PORT

−8−
AGC
VOL1
VOL1
I2C BUS
Interface
Bias
TONE
VOL2
TONE
VOL2
LPF
NJRC
Original
Surround
&
Simulat ed
Stereo
AGC1
AGC2
IN b
IN a
CVA
CVB
CVW
CTH
CTL
CSR
PORT
PORT
AUX1
AUX0
GND
V+
SCL SDA AD
Vref
TONE
-Ha
SS-FIL
SR-FIL
TONE
-Hb
TONE
-La
TONE
-Lb
LF1
LF2
LF3
OUTa
OUTb
OUTw
VOL2
Tr i m m er
AGC
VOL1
VOL1
I2C BUS
Interface
Bias
TONE
VOL2
TONE
VOL2
LPF
NJRC
Original
Surround
&
Simulat ed
Stereo
AGC1
AGC2
IN b
IN a
CVA
CVB
CVW
CTH
CTL
CSR
PORT
PORT
AUX1
AUX0
GND
V+
SCL SDA AD
Vref
TONE
-Ha
SS-FIL
SR-FIL
TONE
-Hb
TONE
-La
TONE
-Lb
LF1
LF2
LF3
OUTa
OUTb
OUTw
VOL2
Tr i m m er
TA2125AF (IC13)
■ BLOCK DIAGRAM
24
6 7 12 131 2
RL5
36
VR
35 34 33 32 31 30
Control
Logic
3
STBY STBY
RIN FIN
4ch
Driver
STB IN3 IN4
REG
STB
29 2728 FIN
VCC
26 25
RE
G OUT
N.C.
23 22 21
3 3 3 3
20 19
4
VCIN IN1
5
N.C. N.C.
3 3 3 3
15 16 17 18
IN2
N.C. N.C.
11 148 9 FIN 10
GND
Iref TSD
RL4 RL3
RL2 RL1
NJW1136 (IC24)
■ BLOCK DIAGRAM

−9−
Frequency
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RFN2
GND
RFO
AGCIN
GVSW
RFGO
RFRPIN
PKC
RFCT
BTC
RFRP
VRO
SEB
FEN
FEO SBAD
TEO
TEN
TEB
SEL
2VRO
LDO
MDI
TNI
TPI
FPI
FNI
GMAD
RFGC
VCC
I-I
I-I
15 pF
15 pF
238 kΩ
238 kΩ
13 kΩ2.26 kΩ
1.4 kΩ
1 kΩ
83 kΩ
2.9 kΩ
48 kΩ
21.82 kΩ
3 STATE
DET.
20 kΩ
3 pF
10 kΩ
10 kΩ
50 kΩ
36 pF
15 kΩ
15 kΩ
10 pF
30 kΩ
1 kΩ
40 pF
150 kΩ
60 kΩ
10 pF
20 kΩ
20 kΩ
20 kΩ
12 kΩ
12 kΩ
BOTTOM
PEAK
20 kΩ
AGC Amp.
100 Ω
11 k Ω
100 kΩ
100 kΩ
11 k Ω
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1 kΩ
SW1
SW2
SW3
20 kΩ
10 kΩ
30 kΩ
3 pF
20 kΩ
60 kΩ
90 kΩ
60 kΩ
150 kΩ
40 pF
TA2153FN (IC12)
■ BLOCK DIAGRAM

−10−
LEVEL SHIFTER
2
1
2
3
4
1
5
6
2
8
4
1
2
3
4
6
8
4
1
3
4
5
6
7
8
9
10
14 28
11
12
13
27
26
25
24
23
22
21
20
19
18
17
16
15
LATCH CIRCUIT
SHIFT REGISTER
LEVEL SHIFTER
LATCH CIRCUIT
L-S R-S
Vss GND VDD
L-S
L-S
L-S
L-S
L-COM
L-S
L-COM
L-S
7
L-S
L-COM
ST
R-S
R-S
R-S
5
R-S
1
R-COM
R-S
2
R-COM
R-S
R-COM
DATA
CK
7
R-S
LEVEL SHIFTER
2
1
2
4
8
4
1
2
4
8
4
1
3
4
5
6
7
8
9
10
14 28
11
12
13
27
26
25
24
23
22
21
20
19
18
17
16
15
LATCH CIRCUIT
SHIFT REGISTER
LEVEL SHIFTER
LATCH CIRCUIT
L-S R-S
Vss GND VDD
L-S
1
L-COM
3
L-S
L-S
5
L-S
2
L-COM
6
L-S
L-S
7
L-S
L-COM
ST
R-S
1
R-COM
3
R-S
R-S
2
R-COM
5
R-S
6
R-S
R-S
R-COM
DATA
CK
7
R-S
TC9163AF (IC21)
■ BLOCK DIAGRAM
TC9164AF
■ BLOCK DIAGRAM

−11−
VCOR
P2VREF
TSMOD
TMAX
TMAXS
PDO
ZDET
HSSW
TESIO0
VDD
MONIT
COFS
SPDA
SPCK
SBSY
SFSY
DAT A
VSS
VDD
CLCK
SBOK
IPF
MBOV
DOUT
AOUT
BCK
VSS
LRCK
EMPH
TEST0
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
PLL
TMAX
VCO
Data
slicer
status
A/D
D/APWM
Servo
control
CLV servo
Sub code
decoder
Synchronous
guarantee
EFM decode
RST
TEST4
CCE
BUCK
VSS
VDD
BUS3
BUS2
BUS1
BUS0
TEST3
TEST2
TEST1
DV SL
LO
DV R
RO
DV DD
DV SR
RAM
ROM Digital equalizer
Automatic
adjustment circuit
Address circuit
16 KRAM
Digital out
Clock
generator
1 bit
DAC
LPF
Micon
interface Correction
circuit
Audio out
circuit
PVREF
LPFO
LPFN
VREF
TRO
FOO
TEZI
TSIN
TEI
SBAD
FEI
RFRP
RFZI
RFCT
AV DD
RFI
SLCO
AV SS
VCOF
RFGC
TEBC
FMO
DMO
2VREF
SEL
FLGA
FLGB
FLGC
FLGD
VDD
VSS
IO0
IO1
IO2
TESIN
TESIO1
VSS
PXI
PXO
VDD
XVSS
XI
XO
XVDD
FVO
IO3
DACT
CKSE
DMOUT
UHSO
HSO
TC9462A (IC10)
■ BLOCK DIAGRAM

−12−
Pin No. Symbol I/O Functional Description Remarks
1 TEST0 I Tes t mode terminal. Normally, keep at open. With pull-up resistor.
2 HSO O
3 UHSO O
Playback speed mode flag output terminal.
UHSO HSO Playback Speed
H H Normal
H L 2 times
L H 4 times
L L
4 EMPH O
Subcode Q data emphasis flag output terminal.
Emphasis ON at “H” level and OFF at “L” level.
The output polarity can invert by command.
5 LRCK O
Channel clock output terminal. (44.1 kHz)
L-ch at “L” level and R-ch at “H” level. The output polarity can
invert by command.
6 VSS Digital GND terminal.
7 BCK O Bit clock output terminal. (1.4112 MHz)
8 AOUT O Audio data output terminal.
9 DOUT O Digital data output terminal.
10 MBOV O
Buffer memory over signal output terminal.
Over at “H” level.
11 IPF O
Correction flag output terminal.
At “H” level, AOUT output is made to correction impossibility
by C2correction processing.
12 SBOK O
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at “H” level.
13 CLCK I/O
Subcode P~W data readout clock input/output terminal.
This terminal can select by command bit. Schmitt input
14 VDD Digital power supply voltage terminal.
15 VSS Digital GND terminal.
16 DATA O Subcode P~W data output terminal.
17 SFSY O Play-back frame sync signal output terminal.
18 SBSY O Subcode block sync signal output terminal.
19 SPCK O Processor status signal readout clock output terminal.
20 SPDA O Processor status signal output terminal.
21 COFS O
Correction frame clock output terminal.
(7.35 kHz)
22 MONIT O
Internal signal (DSP internal flag and PLL clock) output
terminal. Selected by command.
This terminal output the text data with serial by command.
23 VDD Digital power supply voltage terminal.
24 TESIO0 I
Test input/output terminal. Normally, keep at “L” level.
The terminal that inputted the clock for read of text data by
command.
25 P2VREF PLL double reference voltage supply terminal.
26 HSSW O This terminal is used to output PVREF or HiZ by command. 2-state output.
(PVREF, HiZ)
27 ZDET O 1 bit DA converter zero detect flag output terminal.
28 PDO O
Phase difference signal output terminal of EFM signal and
PLCK signal.
3-state output.
(P2VREF, PVREF
, V
SS)

−13−
Pin No. Symbol I/O Functional Description Remarks
29 TMAXS O
TMAX detection result output terminal. Selected by
command bit (TMPS).
3-state output.
(P2VREF, PVREF, VSS)
30 TMAX O
TMAX detection result output terminal. Selected by
command bit (TMPS).
TMAX Detection TMAX Output
Longer than fixed freq. “P2VREF”
Shorter than fixed freq. “VSS”
Within the fixed freq. “HiZ”
3-state output.
(P2VREF, HiZ, VSS)
31 LPFN I LPF amplifier inverting input terminal for PLL. Analog input.
32 LPFO O LPF amplifier output terminal for PLL. Analog output.
33 PVREF PLL reference voltage supply terminal.
34 VCOREF I
VCO center frequency reference level terminal.
Normally, keep at “PVREF” level.
35 VCOF O VCO filter terminal. Analog output.
36 AVSS Analog GND terminal.
37 SLCO O Data slice level output terminal. Analog output.
38 RFI I RF signal input terminal. Analog input.
(Zin: selected by command)
39 AVDD Analog power supply voltage terminal.
40 RFCT I RFRP signal center level input terminal. Analog input.
(Zin: 50 k )
41 RFZI I RFRP zero cross input terminal. Analog input.
42 RFRP I RF ripple signal input terminal. Analog input.
43 FEI I Focus error signal input terminal. Analog input.
44 SBAD I Sub-beam adder signal input terminal. Analog input.
45 TSIN I Tes t input terminal. Normally, keep at “VREF” level. Analog input.
46 TEI I
Tracking error signal input terminal.
Take in at tracking servo on. Analog input.
47 TEZI I Tracking error zero cross input terminal. Analog input.
(Zin: 10 k )
48 FOO O Focus servo equalizer output terminal.
49 TRO O Tracking servo equalizer output terminal.
Analog output.
(2VREF~AVSS)
50 VREF Analog reference voltage supply terminal.
51 RFGC O
RF amplitude adjustment control signal output terminal.
3-state PWM signal output. (PWM carrier 88.2 kHz)
52 TEBC O
Tracking balance control signal output terminal.
3-state PWM signal output. (PWM carrier 88.2 kHz)
53 FMO O
Feed equalizer output terminal.
3-state PWM signal output. (PWM carrier 88.2 kHz)
54 FVO O
Speed error signal or feed search equalizer output terminal.
3-state PWM signal output. (PWM carrier 88.2 kHz)
55 DMO O
Disc equalizer output terminal.
(PWM carrier 88.2 kHz for DSP, Synchronize to PXO)
3-state output.
(2VREF, VREF, VSS)
56 2VREF Analog double reference voltage supply terminal.
57 SEL O
APC circuit ON/OFF indication signal output terminal.
At the laser on time, “HiZ” level at UHS L and “H” level at
UHS H.

−14−
Pin No. Symbol I/O Functional Description Remarks
58 FLGA O
External flag output terminal for internal signal.
Can select signal from TEZC, FOON , FOK and RFZC by
command.
59 FLGB O
External flag output terminal for internal signal.
Can select signal from DFCT , FOON , FMON and RFZC
by command.
60 FLGC O
External flag output terminal for internal signal.
Can select signal from TRON , TRSR , FOK and SRCH
by command.
61 FLGD O
External flag output terminal for internal signal.
Can select signal from TRON , DMON , HYS and SHC
by command.
62 VDD Digital power supply voltage terminal.
63 VSS Digital GND terminal.
64 IO0
65 IO1
66 IO2
67 IO3
I/O
General I/O terminal be changed over input port or output
port by command. At the input port mode, it can readout a
state of terminal (H/L) by read command. At the output port
mode, it outputs (H/L/HiZ) by command.
68 DMOUT I
“L” active, when this terminal is set “L”, IO 0/1 and 2/3 output
feed equalizer signal and disc equalizer signal of 2-state
PWM respectively.
With pull-up resistor.
69 CKSE I Normally, keep at open. With pull-up resistor.
70 DACT I DAC test mode terminal. Normally, keep at open. With pull-up resistor.
71 TESIN I Tes t input terminal. Normally, keep at “L” level. Analog input.
72 TESIO1 I Tes t input/output terminal. Normally, keep at “L” level.
73 VSS Digital GND terminal.
74 PXI I
Crystal oscillator connecting input terminal for DSP.
Normally, keep at “L” level.
75 PXO O Crystal oscillator connecting output terminal for DSP.
76 VDD Digital power supply voltage terminal.
77 XVSS Oscillator GND terminal for system clock.
78 XI I Crystal oscillator connecting input terminal for system clock.
79 XO O Crystal oscillator connecting output terminal for system clock.
80 XVDD Oscillator power supply voltage terminal for system clock.
81 DVSR Analog GND terminal for DA converter. (R-ch)
82 RO O R channel data forward output terminal.
83 DVDD Analog supply voltage terminal for DA converter.
84 DVR Reference voltage terminal for DA converter.
85 LO O L channel data forward output terminal.
86 DVSL Analog GND terminal for DA converter. (L-ch)
87 TEST1 I Tes t mode terminal. Normal, keep at open. With pull-up resistor.
88 TEST2 I Tes t mode terminal. Normal, keep at open. With pull-up resistor.
89 TEST3 I Tes t mode terminal. Normal, keep at open. With pull-up resistor.
90 BUS0 I/O
91 BUS1 I/O
92 BUS2 I/O
93 BUS3 I/O
Micon interface data input/output terminal. Schmitt input.
With pull-up resistor.
94 VDD Digital power supply voltage terminal.

−15−
Vss Digital GND terminal.
BUCK I Micon in terface clock input terminal Schmitt input
CCE I
Command and data sending/receiving chip enable signal
input terminal.
The bus line becomes active at "L"level.
Schmitt input
TEST4 I Test mode selection terminal. With pull-up resistor
TSMOD I Local test mode selection terminal With pull-up resistor
RST I Reset signal input terminal. Reset at "L"level. With pull-up resistor
Pin No. Symbol I/O Functional Description Remarks
95
97
98
99
100
96

−16−
TC2000 Audio Signal Processor Pin Descriptions
Pin Function Description
1 BIASCAP Bandgap reference times two (typically 2.5VDC). Used to set the common mode
voltage for the input op amps. This pin is not capable of driving external circuitry.
2, 6 FDBKP2, FDBKP1 Positive switching feedback.
3 DCMP Internal mode selection. This pin must be grounded for proper device
operation.
4, 7 FDBKN2, FDBKN1 Negative switching feedback.
5 VPWR Test pin. Must be left floating.
8 HMUTE Logic output. A logic high indicates both amplifiers are muted, due to the mute pin
state, or a ìfaultî.
9, 12 Y1, Y2 Non-inverted switching modulator outputs.
10, 11 Y1B, Y2B Inverted switching modulator outputs.
13 NC No connect
14 OCD2 Over Current Detect.
15 REF Internal reference voltage; approximately 1.2 VDC.
16 OCD1 Over Current Detect. This pin must be grounded for proper device
operation.
17 VLO Negative power stage over/under supply voltage sense resistor tie point.
18 OVRLDB A logic low output indicates the input signal has overloaded the amplifier.
19 VHI Positive power stage over/under supply voltage sense resistor tie point.
20 GND Ground.
21 V5 5 Volt power supply input.
22, 27 VP1, VP2 Input stage output pins.
23, 28 IN1, IN2 Single-ended inputs. Inputs are a ìvirtualî ground of an inverting opamp with
approximately 2.4VDC bias.
24 MUTE When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. Ground if not used.
25, 26 BBM1, BBM0 Break-before-make timing control to prevent shoot-through in the output FETs.
TC2000 Audio Signal Processor Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
BIASCAP
FDBKP2
DCMP
FDBKN2
VPWR
FDBKP1
FDBKN1
HMUTE
Y1
Y1B
Y2B
Y2
NC
OCD2 REF
OCD1
VLO
OVRLDB
VHI
GND
V5
VP1
IN1
MUTE
BBM1
BBM0
VP2
IN2

−17−
TP2050 Power Stage Pin Descriptions
Pin Function Description
1 GND-SUB Substrate ground
35,36 VccSign Signal positive supply
15 Vcc1A Positive supply
12 Vcc1B Positive supply
7 Vcc2A Positive supply
4 Vcc2B Positive supply
14 GND1A Negative supply
13 GND1B Negative supply
6 GND2A Negative supply
5 GND2B Negative supply
16,17 OUT1A Output half bridge 1A
10,11 OUT1B Output half bridge 1B
8,9 OUT2A Output half bridge 2A
2,3 OUT2B Output half bridge 2B
29 IN1A Input of half bridge 1A
30 IN1B Input of half bridge 1B
31 IN2A Input of half bridge 2A
32 IN2B Input of half bridge 2B
21,22 Vdd 5V regulator referenced to ground
33,34 Vss 5V regulator referenced to Vcc
25 PWRDN Stand-by pin
26 TRI-STATE Hi-Z pin
27 FAULT Fault output
24 CONFIG Config input
28 TH-WAR Thermal warning output
19 GND-clean Logic ground
23 IBIAS Logic high voltage
18 NC Not connected
20 GND-Reg Ground for Vdd regulator
TP2050 Power Stage Pinout
(Top view with heat slug up)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 GNDSUB
OUT2B
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT2A
OUT1B
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
OUT1A
NC
GNDCLEAN
GNDREG
VDD
VDD
IBIAS
CONFIG
PWRDN
TRISTATE
FAULT
TH_WAR
IN1A
IN1B
IN2A
IN2B
VSS
VSS
VCCSIGN
VCCSIGN

−18−
4 EXPLODED VIEWS AND PARTS LIST
分解図とパーツリスト
EXPLODED VIEW-1

−19−
EXPLODED VIEW-1
REF.NO. PARTSNO. DESCRIPTION REMARKS
1‑1 9A09567000 VOLUMEKNOBASSY HGX1A322ZA
1‑2 9A09557700 DOOR,CD CGR1A281ZK101
1‑3 9A09571100 WINDOW,FIP[J] KGU1A291Y
9A09571120 WINDOW,FIP[E,UK] KGU1A291Z
1‑4 9A09556700 KNOB,CAP(R) CBT1A847YK101
1‑5 9A09559400 FRONTPANEL(AL) CKM2A126ZC35
1‑6 9A09558000 PANEL,SUB CGW1A348K101
1‑7 9A09556800 KNOB,CAP(L) CBT1A847ZK101
1‑8 9A09557600 INDICATOR,POWER CGL1A207
1‑9 9A09557000 KNOB,HOUSING CBT1A862
1‑10 9A09557800 WINDOW,IR CGU1A292K101
1‑11 9A09556500 KNOB,FUNCTION(L) CBT1A845C22
1‑12 9A09556600 KNOB,FUNCTION(R) CBT1A846C22
1‑13 9A09556900 KNOB,SUPPORT CBT1A848
1‑14 9A09571300 FOOT KKL2A055M7G6
1‑15 9A05837300 FOOTCUSHION KHG1A050Y
1‑16 9A08885700 RUBBER CHG1A113
1‑17 9A09559800 BRACKET,PCB CMD1A473
1‑18 9A09562700 CHASSIS,BOTTOM CUA1A219
1‑19 9A07891600 SUPPORT,PCB KMH1A092
1‑20 9A09559200 TOPCABINET CKC1B133S35
1‑21 9A09559600 PLATE,SHIELD CMC1A187
1‑22 9A09559300 REARPANEL[J] CKF1A241Y
9A09559320 REARPANEL[E,UK] CKF1A241Z
1‑23£9A06754900 BUSHING,ACCORD KHR1A028
1‑24£9A08125200 CORD,POWER[J] CJA2J049Z
£9A07916700 CORD,POWER2.5A250V[E] CJA2B043Z
£9A07916800 CORD,POWER2.5A250V[UK] CJA2E045Z
1‑25 9A09559900 INSULATOR,SMPS CMX1A133
1‑26 9A09560200 SMPSPCBASSY[J] COPDDS114B
9A09560220 SMPSPCBASSY[E,UK] COPDDS114A
1‑27 9A09560600 AMPPCBASSY[J] COP11536D
9A09560620 AMPPCBASSY[E,UK] COP11536E
1‑28 9A09560100 TUNERMODULE[J] CNVMB006MA18SL
9A09560120 TUNERMODULE[E,UK] CNVMB114MA18L
1‑29,1‑30 9A09560500 MAINPCBASSY[J] COP11535D
9A09560520 MAINPCBASSY[E,UK] COP11535E
1‑31 9A09560400 CDPCBASSY[J] COP11534D
9A09560420 CDPCBASSY[E,UK] COP11534E
1‑32 9A09056400 MECHANISM,KSL2130CCM HJDKSL2130CCM
1‑33,1‑34 9A09560300 FRONTPCBASSY[J,UK] COP11533D
9A09560320 FRONTPCBASSY[E] COP11533E
9A09564000 CARDCABLE CWC1B2A15A120B
9A09564100 CARDCABLE CWC1B2A30A120B
9A09564300 CARDCABLE CWC1C4A17B070B
9A09564200 CARDCABLE[J,UK] CWC1C4A15B130B
9A09572600 CARDCABLE[E] CWC1C4A17B130B
9A09316700 MECHACABLE CWC1F1A16A200A

EXPLODED VIEW-2
−20−
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