7A42
Operators
Figure
No
.
1-1
1-2
2-1
2-2
LIST
OF
ILLUSTRATIONS
Page
7A42 release latch
................................................
1-3
7A42 dimensional drawing
.......................................
1-23
Simplified block diagram of the 7A42
..............................
2-2
Definition of the Boolean AND
.
OR
.
NOT and XOR (EXCLUSIVE-OR)
logic functions
....................................................
2-3
Examples of products of Channel 1through 4
......................
2-5
Function
.
f
and
g
OR'ed together
...................................
2-6
Example of EDGE Qualified TRIGGER FUNCTION
.................
2-7
Example of A THEN B Nested Triggering
...........................
2-8
7A42 controls. connectors. and indicators
........................
2-10
Self-test in progress
.............................................
2-48
Self-test finished
................................................
2-48
7A42 front-panel drawing showing pushbuttons and indicators
that are illuminated during the self-test sequence
.................
2-49
Typical self-test failure display
...................................
2-50
7A42 front-panel control lights when initialized
...................
2-54
Channel readout display
.........................................
2-58
Channel readout display with 10X probes attached to inputs
of CHI. CH2. CH3. and CH4
.....................................
2-58
Timing diagram showing the relationship of the TRIGGER OUT
waveform to the input signals
....................................
2-63
Timing diagram depicting the TRIGGER OUT waveform. as a
result of the TRIGGER FUNCTION reacting to the input signals
...
2-63
Example of A THEN
€3.
level and EDGE sensitive TRIGGER FUNCTION.
showing the Normal and A THEN B Gate waveform alternatives
...
2-64
Triggering on the decimal "10" event
...............................
3-2
Display of four channels with TRIG VIEW trace
.....................
3-3
Four channel display with an external clock signal displayed on the
TRIG VIEW trace
..................................................
3-3
...............................
Triggering on a low-amplitude pulse 3-5
Timing diagram of
a
typical microprocessor read cycle
.............
3-6
...........................
Set up to monitor invalid data transitions 3-8
The 7A42 captures
a
positive transition of data during the time data
..................................................
should be stable 3.8
Bus contention measurement set up
.............................
3-10
Standard 500-ohm probe forms voltage divider with termination
.........................................................
resistor 3-14
Simplified diagram of the P6230 Variable Bias/Offset probe
.......
3-15
Two ECL level waveforms
.
A without bias offset. B with a -2 volt
......................................................
bias offset 3-16
