
TM 11-6625-3145-14
TABLE OF CONTENTS (cont.)
Section 4 THEORY OF OPERATION (cont.)
Trigger Sequencer Flag <7> ........................................................................................................ 4-14
N Flag Circuit........................................................................................................................ 4-14
TRIG’D Flag Circuit.............................................................................................................. 4-15
SUCCEED Flag Circuit......................................................................................................... 4-15
STOP Flag Circuit ................................................................................................................ 4-15
SQRAM Data/Word Recognizer Data Multiplexer <7>................................................................. 4-15
LSI-A A03U158 <7>..................................................................................................................... 4-15
Address Decoder.................................................................................................................. 4-15
N Register ............................................................................................................................ 4-16
DL Register .......................................................................................................................... 4-16
Mask Register ...................................................................................................................... 4-16
Event/Delay Counter............................................................................................................ 4-16
ACQ Status Logic................................................................................................................. 4-16
318 A04 ACQ Memory Board <8> <9>................................................................................................. 4-17
Acquisition Memory and ACQ Address Counter <8>................................................................... 4-17
Chip Select Latch................................................................................................................. 4-17
Acquisition Memory.............................................................................................................. 4-18
ACQ Address Counter and Carry Latch............................................................................... 4-18
Timebase and MPU Bus Interface <9>........................................................................................ 4-19
TTL-to-ECL Translator ......................................................................................................... 4-19
Address Decoder.................................................................................................................. 4-19
Oscillator .............................................................................................................................. 4-19
Divider, Timer, and Slow Clock Detector ............................................................................. 4-19
INTCLK Buffer...................................................................................................................... 4-19
Data Selector........................................................................................................................ 4-19
ECL-to-TTL Translator and TTL Bus Buffer......................................................................... 4-19
Full Valid Flag Latch............................................................................................................. 4-20
LSI-B (A04U 140)................................................................................................................. 4-20
318/338 A05 ROM/Threshold Board --<10>......................................................................................... 4-24
ROM Circuitry............................................................................................................................... 4-24
Threshold Circuit .......................................................................................................................... 4-25
D/A Converter....................................................................................................................... 4-25
Analog Switches................................................................................................................... 4-25
318/338 A06 MPU/Display Board<11>................................................................................................ 4-27
MPU ..................................................................................................................................... 4-27
RAM ..................................................................................................................................... 4-27
Bus Drivers................................................................................................................................... 4-27
Keyboard and Keyboard Controller.............................................................................................. 4-27
Interrupt Gates ............................................................................................................................. 4-27
Display Controller......................................................................................................................... 4-27
318/338 A07 Serial, Non-Volatile Memory, RS-232C <17> <18>........................................................ 4-30
Serial Input <17>.......................................................................................................................... 4-30
Input Comparator ................................................................................................................. 4-30
Offset Adjust......................................................................................................................... 4-30
Clock-Level Translator . ....................................................................................................... 4-30
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