Telit Wireless Solutions SE867-AGPS User manual

SE867-AGPS User Guide
1VV0300860 Rev. 0 - 2009-10-23

SE867-AGPS User Guide
1VV0300860 Rev. 0 - 2009-10-23
Reproduction forbidden without Telit Communications S.p.A. written authorization - All Rights Reserved page 2 of 62
This document is relating to the following products:
PRODUCT
SE867-AGPS

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Contents
1. Introduction................................................................................................................ 6
1.1. Audience...........................................................................................................................6
1.2. Contact Information, Support ...........................................................................................6
1.3. Text Conventions ..............................................................................................................7
1.4. Related Documents ..........................................................................................................7
1.5. Document change log ....................................................................................................... 7
2. Overview ..................................................................................................................... 8
3. Mechanical Dimension ............................................................................................... 9
4. GPS module connections...........................................................................................11
4.1. PIN-OUT .........................................................................................................................11
4.2. Pin-out view....................................................................................................................12
5. Electrical description ................................................................................................13
5.1. Available power supply configurations ........................................................................... 13
5.1.1. Configuration 1.................................................................................................................................. 13
5.1.2. Configuration 2.................................................................................................................................. 15
5.1.3. Configuration 3.................................................................................................................................. 16
5.2. Power-on sequence........................................................................................................ 18
5.3. Logic levels..................................................................................................................... 18
6. RF path and antenna .................................................................................................20
6.1. RF design guidlines ........................................................................................................ 20
6.2. GPS antenna PCB line guidelines ................................................................................... 22
6.3. Antenna installation guidelines ...................................................................................... 22
7. Mounting the SE867-AGPS on the application board .................................................23
7.1. Stencil ............................................................................................................................ 23
7.2. PCB pad design .............................................................................................................. 23
7.3. Solder paste ................................................................................................................... 25
7.4. SE867-AGPS solder reflow ............................................................................................. 25
8. Moisture sensitivity ...................................................................................................27
9. Software Features.....................................................................................................28

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9.1. GPS NMEA 0183.............................................................................................................. 28
9.1.1. Standard NMEA Sentences............................................................................................................... 28
9.1.2. Custom NMEA Sentences ................................................................................................................. 29
9.1.2.1. ASSIST ........................................................................................................................................... 30
9.1.2.2. CORR ............................................................................................................................................. 30
9.1.2.3. STORELGF ..................................................................................................................................... 31
9.1.2.4. START ............................................................................................................................................ 31
9.1.2.5. SLEEP............................................................................................................................................ 32
9.1.2.6. WAKEUP ........................................................................................................................................ 33
9.1.2.7. STOP .............................................................................................................................................. 33
9.1.2.8. CONFIG.......................................................................................................................................... 34
9.1.2.9. SET................................................................................................................................................. 35
9.1.2.10. GETCONFIG ............................................................................................................................... 35
9.1.2.11. VERSION.................................................................................................................................... 35
9.1.2.12. FOM ........................................................................................................................................... 35
9.1.2.13. EPH 1,2,3 ................................................................................................................................... 36
9.1.2.14. EPH0.......................................................................................................................................... 38
9.1.2.15. CFG_R........................................................................................................................................ 39
9.1.2.16. CFG_S........................................................................................................................................ 39
9.1.2.17. ERR............................................................................................................................................ 39
9.1.2.18. OK .............................................................................................................................................. 41
9.1.3. Configuration Sections...................................................................................................................... 41
9.1.3.1. Output Configuration..................................................................................................................... 41
9.1.3.2. Time Zone Configuration............................................................................................................... 44
9.1.3.3. Version Number ............................................................................................................................ 45
9.1.3.4. SBAS Configuration....................................................................................................................... 46
9.1.3.5. Datum Configuration..................................................................................................................... 47
9.1.3.6. Position Pinning Configuration ..................................................................................................... 49
9.2. Assisted GPS – AGPS...................................................................................................... 51
9.3. Analysis Tool .................................................................................................................. 52
10. SE867-AGPS evaluation kit........................................................................................53
10.1. Short description......................................................................................................... 53
11. Conformity assessment issues..................................................................................54
12. Safety recommendations...........................................................................................55
Appendix A– Datum Codes ...............................................................................................57

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DISCLAIMER
The information contained in this document is the proprietary information of Telit
Communications S.p.A. and its affiliates (“TELIT”).
The contents are confidential and any disclosure to persons other than the officers,
employees, agents or subcontractors of the owner or licensee of this document,
without the prior written consent of Telit, is strictly prohibited.
Telit makes every effort to ensure the quality of the information it makes available.
Notwithstanding the foregoing, Telit does not make any warranty as to the information
contained herein, and does not accept any liability for any injury, loss or damage of any
kind incurred by use of or reliance upon the information.
Telit disclaims any and all responsibility for the application of the devices
characterized in this document, and notes that the application of the device must
comply with the SAFETY standards of the applicable country, and where applicable,
with the relevant wiring rules.
Telit reserves the right to make modifications, additions and deletions to this document
due to typographical errors, inaccurate information, or improvements to programs
and/or equipment at any time and without notice.
Such changes will, nevertheless be incorporated into new editions of this document.
Copyright: Transmittal, reproduction, dissemination and/or editing of this document as
well as utilization of its contents and communication thereof to others without express
authorization are prohibited. Offenders will be held liable for payment of damages. All
rights are reserved.
Copyright © Telit Communications S.p.A. 2009.
.

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1. Introduction
The information presented in this document is believed to be accurate and reliable.
However, no responsibility is assumed by Telit Communications S.p.A. for its use, nor
any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent rights of Telit
Communications S.p.A. other than for circuitry embodied in Telit products. This
document is subject to change without notice.
1.1. Audience
This document is intended for customers who are evaluating one or more products in
the applicability table.
1.2. Contact Information, Support
For general contact, technical support, to report documentation errors and to order
manuals, contact Telit’s Technical Support Center (TTSC) at:
[email protected]
[email protected]
[email protected]
[email protected]
Alternatively, use:
3TUhttp://www.telit.com/en/products/technical-support-center/contact.phpU3T
For detailed information about where you can buy the Telit modules or for
recommendations on accessories and components visit:
3TUhttp://www.telit.comU3T
To register for product news and announcements or for product questions contact
Telit's Technical Support Center (TTSC).
Our aim is to make this guide as helpful as possible. Keep us informed of your
comments and suggestions for improvements.
Telit appreciates feedback from the users of our information.

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1.3. Text Conventions
Danger – This information MUST be followed or catastrophic equipment failure or
bodily injury may occur.
Caution or Warning – Alerts the user to important points about integrating the
module, if these points are not followed, the module and end user equipment may
fail or malfunction.
Tip or Information –Provides advice and suggestions that may be useful when
integrating the module.
All dates are in ISO 8601 format, i.e. YYYY-MM-DD.
1.4. Related Documents
The following documents are related to this user guide:
[1] “SE867-AGPS Product description”
[2] “SE867-AGPS Evaluation Board User Guide”
All documentation can be downloaded from Telit official web site www.telit.com if not
otherwise indicated.
1.5. Document change log
R
Re ev vi is si io on n D Da at te e C Ch ha an ng ge es s
ISSUE#0 2009-10-23 First issue

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2. Overview
This document is a user guide for developing a GPS application based on Telit
Communications S.p.A. stand-alone GPS module SE867-AGPS.
This document cannot embrace the whole hardware solutions and products that may
be designed. The information given is a guide line and a starting point for properly
developing products with the Telit stand-alone module.

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3. Mechanical Dimension
The Telit SE867-AGPS module overall dimensions are:
Length: 18 mm
Width: 18 mm
Thickness: 3.5 mm
Weight 1.8 g

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Bottom side

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4. GPS module connections
4.1. PIN-OUT
Ball Signal I/O Function Type Notes
Miscellaneous Functions
A1 RFEN O Active high enable signal of RF section Control
B1 RFXEN O Active low enable signal of RF section Control
B2 BOOTSEL I Boot mode selection signal Control Internal pull-up
C2 WAKE1 I Wake signal input Control
A3 RTC_IN I Input of the external RTC crystal Timing
A4 RTC_OUT O Output of the external RTC crystal Timing
D2 1V8_RF_EN I
Active low enable signal of the 1V8_RF voltage
regulator Control Internal pull-up
E2 1V8_DIG_EN I
Active low enable signal of the 1V8_DIG voltage
regulator Control Internal pull-up
D4 RESET I Active low reset signal Control
Schmitt trigger
input
F4 RF_IN I RF input RF
B6 PPS O Precise timing signal Timing
UART
B4 TX_UART O UART TX signal UART
B5 RX_UART I UART RX signal UART
POWER
D1 1V8_RF PWR RF section power supply -
E1 1V8_DIG PWR BB section power supply -
F1 VIN PWR Internal dual regulator input -
B3 VDD_CTRL PWR CTRL power island supply -
C3 IOVDD_AIN PWR Analog input power island supply -
D3 VREG_OUT PWR Output of the internal single output regulator -
A2 VDD_REG_IN PWR Input of the internal single output regulator -
A6 V_IO PWR I/O power island supply -
GROUND
C1 GND -
F2 GND -
E3 GND -
E4 GND -
A5 GND -
C5 GND -
D5 GND - -
F5 GND - -
E6 GND - -
F6 GND - -
RESERVED

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Ball Signal I/O Function Type Notes
E5 N.C. - -
C6 N.C. - -
D6 N.C. - -
C4 N.C. - -
4.2. Pin-out view
A B C D E F
1 RFEN RFXEN GND 1V8_RF 1V8_DIG VIN
2 VDD_REG_IN BOOTSEL WAKE1 1V8_RF_EN 1V8_DIG_EN GND
3 RTC_IN VDD_CTRL IOVDD_AIN VREG_OUT GND
4 RTC_OUT TX_UART NC RESET GND RF_IN
5 GND RX_UART GND GND NC GND
6 V_IO PPS NC NC GND GND
NOTE: The drawing above is a top view.

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5. Electrical description
The power supply circuitry and board layout are a very important part in the full product
design and they strongly reflect on the product overall performances, hence read
carefully the requirements and the guidelines that will follow for a proper design.
5.1. Available power supply configurations
In order to give a higher flexibility to the required power configuration different
powering options are allowed:
1) Wide range voltage input from 2.5V up to 4.2V plus an additional 3V 10%
reference voltage for I/O peripherals (for 3V logic level interfaces)
2) Wide range voltage input from 2.5V up to 4.2V plus an additional 1.8V 10%
reference voltage (internally or externally generated) for I/O peripherals (for 1.8V
logic level interfaces)
3) Externally generated 1.8V 5% supply plus 3V 10% or 1.8V 10% for I/O
peripherals (bypassing the internal regulator). This solution allows for a lower
flexibility but assures lower power consumptions (no dissipation in the internal
linear regulator).
5.1.1. Configuration 1
The first available power supply configuration exploits the internal voltage regulators to
generate the required 1V8_DIG and 1V8_RF supplies. In order to do so the internal
regulators must be enabled via the 1V8_DIG_EN and 1V8_RF_EN signals (active low).
Additional 3V voltage must be supplied on the V_IO pin (this voltage regulate the I/O
voltage levels for the UART signals). VDD_REG_IN pin and IOVDD_AIN must be tied
together and must be equal to or greater than every other voltage supplied to the
internal GPS chipset (they must be compared with V_IO and VDD_CTRL but not with VIN
because VIN is internally regulated). VDD_CTRL is responsible of powering the
SYSCTRL island and must be connected with the output of the internal regulator
(VREG_OUT). SYSCTRL island includes the RFEN, RFXEN and RESET signals, plus the
RTC circuitry (so it’s responsible of the system powering during power save modes
involving the RTC). The diagram reported in the figure below shows the power
connections for this configuration.

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Figure 1 Power supply connections for configuration 1
The voltage ranges for this configuration are:
Voltage Min Max
VIN 2.5V 4.2V
V_IO 2.7V 3.3V
VDD_REG_IN 2V 3.6V
The condition VDD_REG_IN V_IO must be satisfied for every module power mode
(included power save modes).
Note: Please note that the diagram above reports only the required connections.
For detailed circuit with all the required components (including bypass and
decoupling capacitors) please refer to the suggested designs.

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5.1.2. Configuration 2
This configuration is similar to the previous one with the difference that the V_IO is now
set to 1.8V and the I/O logic levels have changed consequently. This change in the V_IO
levels requires also a change in the IOVDD_AIN supply. Indeed this supply control the
logic level of the WAKE1 pin and so, in order to have all the I/O pin at the same logic is
necessary to change also the IOVDD_AIN configuration, although always respecting the
condition of IOVDD_AIN being the higher voltage in the system. In this configuration,
the internal regulator with input VDD_REG_IN is not exploited in order to have
IOVDD_AIN connected to the 1V8_DIG voltage and 1.8V logic levels on the WAKE1 pin.
The diagram below indicates the connections required for this configuration.
Figure 2 Power supply connections for configuration 2
The VIN voltage range is the same reported for the previous configuration. Please
consider that in place of exploiting the internally generated 1V8_DIG an external 1.8V
supply is allowed to be used as well (in this case please verify to have a not noisy and
clear 1.8V supply). The voltage range for this external 1.8V supply is 1.62V ÷ 1.98V.
Note: Please note that the diagram above reports only the required connections.
For detailed circuit with all the required components (including bypass and
decoupling capacitors) please refer to the suggested designs.

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5.1.3. Configuration 3
In this configuration, the internal regulators are bypassed and the module power
consumption is reduced. The internal LDO must be disabled via 1V8_DIG_EN and
1V8_RF_EN signals and to separate 1.8V supplies must be connected to the 1V8_DIG
and 1V8_RF pins. The two 1.8V supplies must be generated from two separate
regulators (or from the separate outputs of a dual regulator) in order to prevent low
frequency digital noise coupling in the module. Passive filtering of such a noise is not
sufficient and this solution allows gaining 1 or 2 dB in sensitivity with a proper power
supply design. If 3V logic level I/O interfaces are required is necessary to connect V_IO,
VDD_REG_IN, IOVDD_AIN and VDD_CTRL as in configuration 1, while if 1.8V logic levels
are required the connections are similar to configuration 2 with V_IO, IOVDD_AIN and
VDD_CTRL connected to 1V8_DIG (externally generated) and VDD_REG_IN and
VDD_REG_OUT left floating. The diagrams below illustrate connections for both of the
situations.
Figure 3 Power supply connections for configuration 3 (I/O at 3V)
The V_IO and VDD_REG_IN ranges are the same as in configuration 1, the 1V8_RF and
1V8_DIG signals have a nominal value of 1.8V with range 1.71V ÷ 1.89V.

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Figure 4 power supply connections for configuration 3 (I/O at 1.8V)
1V8_DIG and 1V8_RF limits are the same reported above.
Note: Please note that the diagrams above report only the required connections.
For detailed circuit with all the required components (including bypass and
decoupling capacitors) please refer to the suggested designs.

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5.2. Power-on Sequence
A few rules must be respected when powering the SE867-AGPS module. When using a
configuration with a 3V power supply on the V_IO pin attention must be paid in order to
avoid asserting V_IO when the 1V8_DIG is not asserted as well. Indeed applying 3V
without the core voltage will cause improper internal of the GPS chipset with a
subsequent large current flow and potential device damage. In order to allow correct
power-on of the module and according to the chipset vendor recommendations an
internal network on the V_IO power has been inserted. However attention must be paid
in order to avoid asserting V_IO without 1V8_DIG asserted for long intervals.
Furthermore, the module requires a power-on reset and fault detection. At the power
up the active low reset signal must be asserted, after the reset signal is received the
module is forced in a power-on state and boots up at the negation of the reset signal.
The reset signal must be asserted also when a power fault is detected in the 1V8_DIG
signal in order to avoid conditions which can cause corruption of the internal flash
memory. The reset signal can be asserted by either an external power-on-reset
supervisor or a host processor.
5.3. Logic levels
Digital Signals
Item Condition Min Max Unit
VIH VDDIO 10%
0.7 x
VDDIO V
VIL VDDIO 10% 0.3 x
VDDIO V
VOH IOH = -3.5mA @3V 10% VDDIO
IOH = -2.25mA @1.8V 10% VDDIO
0.8 x
VDDIO VDDIO V
VOL IOL = 3.5mA @3V 10% VDDIO
IOL = 2.25mA @1.8V 10% VDDIO GND 0.2 x VDDIO V
RESET: Schmitt trigger low to
high threshold VT+ VDDIO = 1.8V 10% 0.85 1.4 V
RESET: Schmitt trigger high to
low threshold VT- VDDIO = 1.8V 10% 0.53 1.05 V
RESET: Schmitt trigger
hysteresis window VDDIO = 1.8V 10% 0.12 0.64 V
1V8_RF_EN High 1.2 V
1V8_RF_EN Low 0.3 V
1V8_DIG_EN High 1.2 V
1V8_DIG_EN Low 0.3 V

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Important: in the previous table VDDIO represents the reference voltage of the
different signals. Please refer to the following table for a signal-to-reference
voltage mapping.
Signal-to-reference voltage mapping
Signal I/O Reference voltage
RFEN O VDD_CTRL
RFXEN O VDD_CTRL
BOOTSEL I IOVDD_AIN
WAKE1 I IOVDD_AIN
RTC_IN I VDD_CTRL
RTC_OUT O VDD_CTRL
RESET I VDD_CTRL
PPS O V_IO
TX_UART O V_IO
RX_UART I V_IO

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6. RF path and antenna
The RF path and board layout design are, together with the correct antenna choice, the
most important part in the full product design and they strongly reflect on the product
overall performances, hence read carefully and follow the requirements and the
guidelines for a proper design.
6.1. RF design guidlines
The SE867-AGPS module requires an external RF path with a net gain > 16dB and a
noise figure < 1.5dB in order to achieve the best performances. In order to achieve this
gain designs with external LNA and/or active antenna are allowed, even if the
suggestion for better RF performances is to concentrate the path gain in the active
antenna avoiding the LNA when such an antenna is available.
Increasing path gain far beyond 16 dB is not suggested because after this threshold,
the improvements in sensitivity deriving from a gain increase are limited and chances
of jamming issues increase. When concentrating the whole gain in the antenna the
maximum allowed gain for it is 30dB. In the table below active and passive antenna
required features are reported.
ANTENNA REQUIREMENTS
Central frequency 1575.42 MHz (GPS L1)
Bandwidth 1.023MHz
Amplification (active antenna
only) 25dB typ. (30dB max)
Noise figure (active
antenna only) < 1.5dB
Impedance [Ohm] 50
Supply voltage (active
antenna only) Depends on customer design
Coupling with other signals is not allowed
When choosing an active antenna gain the cable loss must be taken into account in
order to get the desired RF path net gain. Furthermore, please note that when
using a passive antenna the external LNA is mandatory.
The chosen active antenna must be properly biased using a correctly design bias
tee. The figure below shows a bias tee example (including ESD protection diode).