TENX TECHNOLOGY TM59MA41 User manual

Advance
Information
0tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
TM59MA41
User’s Manual
tenx technology, inc.

Advance Information UM-TM59MA41_E
1tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
Contents
Chapter 1. Overview ................................................................................... 2
1-1. Feature.................................................................................................................. 2
1-2. Clock Scheme and Instruction Cycle................................................................. 5
1-3. Addressing Mode................................................................................................. 5
1-4. ALU and Working (W) Register........................................................................... 6
1-5. STATUS Register.................................................................................................. 6
1-6. Interrupt ................................................................................................................ 7
1-7. Reset ..................................................................................................................... 7
1-8. Power-Down Mode............................................................................................... 8
1-9. System Config Register....................................................................................... 8
1-10. Instruction Set.................................................................................................... 10
Chapter 2. Control Register ..................................................................... 21
Chapter 3. Timer0,1................................................................................... 40
Chapter 4. 8-Bit PWM................................................................................ 43
Chapter 5. 12-Bit PWM.............................................................................. 45
Chapter 6. Analog to Digital Converter................................................... 47
Chapter 7. I/O Ports................................................................................... 49
Chapter 8. Buzzer Out .............................................................................. 53
Chapter 9. Flash Memory Interface ......................................................... 55
Chapter 10. Electrical Characteristics....................................................... 56
10-1. Absolute Maximum Ratings.............................................................................. 56
10-2. DC Characteristics............................................................................................. 56
10-3. Clock Timing Constants.................................................................................... 57
10-4. External Interrupt Characteristics.................................................................... 58
10-5. A/D Converter Electrical Characteristics......................................................... 58
10-6. Reset Timing Characteristics............................................................................ 59
10-7. LVR Circuit Characteristics............................................................................... 59
Chapter 11. Packaging Information........................................................... 60
11-1. 20-DIP Package Dimension ............................................................................... 61
11-2. 20-SOP Package Dimension.............................................................................. 62
11-3. 20-SSOP Package Dimension ........................................................................... 63
11-4. 16-DIP Package Dimension ............................................................................... 64
11-5. 16-SOP Package Dimension.............................................................................. 65
11-6. 16-SSOP Package Dimension ........................................................................... 66

Advance Information UM-TM59MA41_E
2tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
Chapter 1. Overview
1-1. Feature
1. ROM: 4K x 14 bits flash memory (MTP)
2. RAM: 192 x 8 bits
3. STACK: 6 Levels
4. I/O ports: Three I/O ports (Max 18 pins) and Bit programmable ports
5. Timer/counter: Two 8-bit timer/counter (or one 16-bit) with time interval modes
6. Watchdog Timer: On chip WDT based on system oscillator
7. Power-On Reset & Watchdog timer overflow Reset & Low Voltage detector reset
8. Oscillation Frequency:
z1 MHz to 12 MHz external crystal oscillator
zInternal RC: 4.6 MHz (typ.) in VDD = 5 V
zExternal RC
9. High-speed PWM:
z8-bit PWM 1-ch, 6-bit base + 2-bit extension (Max: 156 kHz)
z12-bit PWM 1-ch, 6-bit base + 6-bit extension (Max: 156 kHz)
10. Operation Voltage:
z2.0 to 5.5V (LVR disable)
zLVR to 5.5V (LVR enable)
11. Instruction set: 35 Instructions
12. Execution Time: 167 ns at 12 MHz fOSC (minimum)
13. A/D Converter: 10-bit conversion resolution with 10-ch analog input pins (MAX)
14. Interrupts: 5 interrupt sources with one vector with one interrupt level
15. Buzzer Out: Frequency Selectable Buzzer Output
16. System Config Option:
zLVR Level Selection zLVR/IVC control in STOP mode
zn Reset pin Selection zClock Source Selection
zRead protection control
17. Reset vector: 000H
18. Interrupt vector: 001H
19. Power Down mode
20. Package Types:
z20-SOP, SSOP, DIP z16-SOP, SSOP, DIP

Advance Information UM-TM59MA41_E
3tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
<Figure 1-1. System Block Diagram>
<Figure 1-2. Pin Assignment Diagram _ Package Types: 20-Pin SOP/DIP/SSOP>

Advance Information UM-TM59MA41_E
4tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
<Figure 1-3. Pin Assignment Diagram _ Package Types: 16-Pin SOP/DIP/SSOP>
Name In/Out Pin Description Shared Function
PA.0–PA.7 I/O
Bit-programmable I/O port for Schmitt-trigger input or
push-pull output. Pull-up resistors are assignable by
software. PortA pins can also be used as A/D converter
input, PWM output or external interrupt input.
ADC0-ADC7
INT0/INT1
PWM0/PWM1
PB.0–PB.1 I/O
Bit-programmable I/O port for Schmitt-trigger input or
push-pull, open-drain output. Pull-up resistors or pull-
down resistors are assignable by software.
XIN,XOUT
PB.2 I Schmitt trigger input port nRESET
nRESET I External Reset input PB.2
PC.0–PC.6 I/O
Bit-programmable I/O port for Schmitt-trigger input or
push-pull, open-drain output. Pull-up resistors are
assignable by software.
ADC8-9/CLO
T0OUT/BUZZER
XIN,XOUT – Crystal/Ceramic, or RC oscillator signal for system clock. PB.0–PB.1
VDD,VSS P Voltage input pin and ground –
CLO O System clock output port PC.6
INT0–INT1 I External interrupt input port PA.0, PA.1
PWM0 O 8-Bit high speed PWM output PA.6
PWM1 O 12-Bit high speed PWM output PA.7
T0OUT O Timer0 match output PC.0
ADC0–ADC9 I A/D converter input PA.0–PA.7
PC.5–PC.6
< Table 1-1. PIN Description > < I: Input; O: Output; I/O: Bi-direction; P: Power >

Advance Information UM-TM59MA41_E
5tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
1-2. Clock Scheme and Instruction Cycle
The clock input (XIN) is internally divided by two to generate Q1 state and Q2 state for each instruction cycle.
The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program ROM and
latched into the instruction register in Q2. It is then decoded and executed during the following Q1-Q2 cycle.
Fetch Execute
Branch
Instruction
Instruction
Pipeline
Flow Fetch Execute
Fetch Flush
Fetch Execute
Instruction
Cycle
FOSC
Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2
< Figure 1-5. Clock/Instruction cycle and pipeline >
Branch instructions take two cycles since the fetch instruction is ‘flushed’ from the pipeline, while the new
instruction is being fetched and then executed.
1-3. Addressing Mode
The Programming Counter is 12-bit wide capable of addressing a 4K x 14 program ROM. As a program
instruction is executed, the PC will contain the address of the next program instruction to be executed. The
PC value is normally increased by one except the followings. The Reset Vector (000h) and the Interrupt
Vector (001h) are provided for PC initialization and Interrupt. For CALL/GOTO instructions, PC loads 12 bits
address from instruction word and the MSB from STATUS’s bit 6. For RET/RETI/RETLW instructions, PC
retrieves its content from the top level STACK. For the other instructions updating PC[7:0], the PC[11:8]
keeps unchanged. The STACK is 12-bit wide and 6-level in depth. The CALL instruction and Hardware
interrupt will push STACK level in order, While the RET/RETI/RETLW instruction pops the STACK level in
order.
The data memory is partitioned into two banks, which contain the General Purpose Data Memory and the
Special Function Registers (SFR). STATUS.4 is the bank select bits. Each bank extends up to 7Fh (128
bytes). The lower locations of each bank (00h-1Fh) are reserved for the SFR. Above the SFR is General
Purpose Data Memory, implemented as static RAM. SFR area is mirrored in all banks for code reduction and
quicker access.
The first half of RAM (00h – 3Fh) is bit-addressable.
Data memory can be addressed directly or indirectly. Indirect Addressing is made by INDF register. The
INDF register is not a physical register. Addressing INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). Reading INDF itself indirectly (FSR=0) will produce 00h.
Writing to the INDF register indirectly results in a no-operation.

Advance Information UM-TM59MA41_E
6tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
Program Memory
0000 Reset Vector
0001 Interrupt Vector
0FFF
Program ROM Page0
< Figure 1-6. Address space >
1-4. ALU and Working (W) Register
The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. In two-operand
instructions, typically one operand is the W register, which is an 8-bit non-addressable register used for ALU
operations. The other operand is either a file register or an immediate constant. In single operand
instructions, the operand is either W register or a file register. Depending on the instruction executed, the
ALU may affect the values of Carry(C), Digit Carry(DC), and Zero(Z) Flags in the STATUS register. The C
and DC flags operate as a /Borrow and /Digit Borrow, respectively, in subtraction.
1-5. STATUS Register
This register contains the arithmetic status of ALU and the Bank select for RAM. The STATUS register can
be the destination for any instruction, as with any other register. If the STATUS register is the destination for
an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set
or cleared according to the device logic. It is recommended, therefore, that only BCF, BSF and MOVWF
instructions be used to alter the STATUS Register because these instructions do not affect those bits.
STATUS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Value – – – 0 – 0 0 0
R/W – – – R/W – R/W R/W R/W
Bit Description
7-5 Not Used (Must be set to 0)
4
SRAM: SRAM Bank Selection Bit
0: Bank 0
1: Bank 1
3 Not Used (Must be set to 0)
2
Zero Flag (Z)
0: the result of a logic operation is not zero
1: the result of a logic operation is zero
Decimal Carry Flag or Decimal/Borrow Flag (DC)
ADD instruction SUB instruction
1 1: a carry from the low nibble bits of the result occurred
0: no carry
1: no borrow
0: a borrow from the low nibble bits
of the result occurred
Carry Flag(C) or Borrow Flag
ADD instruction SUB instruction
0 1: a carry occurred from the MSB
0: no carry
1: no borrow
0: a borrow occurred from the MSB
<Table 1-2. STATUS — System Flags Register (Address: 03H)>
Data Memory
00
1F
Registers, STATUS.4=0/1
Bit addressable
20
3F
RAM, STATUS.4=0
Bit addressable
RAM, STATUS.4=1
Bit addressable
40
7F
RAM
STATUS.4=0
RAM
STATUS.4=1

Advance Information UM-TM59MA41_E
7tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
1-6. Interrupt
The TM59MA41 has 1 level, 1 vector and 6 sources. Each interrupt source has its own enable control bit. An
interrupt event will set its individual flag. Because TM59MA41 has only 1 vector, there is not a interrupt
priority register. The interrupt priority is determined by F/W.
Interrupt Pending
Interrupt
Vector
i-Flag
Interrupt
Source
Interrupt
Enable
< Figure 1-7. Interrupt Function Diagram >
If the corresponding interrupt enable bit has been set (INTCON), it would trigger CPU to service the interrupt.
CPU accepts interrupt in the end of current executed instruction cycle. In the mean while, A “CALL 0001”
instruction is inserted to CPU, and the i-flag is set to prevent recursive interrupt nesting. The i-flag is cleared
in the instruction after the “RETI” instruction. That is, at least one instruction in main program is executed
before service the pending interrupt. The interrupt event is edge trigged. F/W must clear the interrupt event
register while serves the interrupt routine.
1-7. Reset
The TM59MA41 can be RESET in four ways.
- Power-On-Reset
- Hardware Reset by nRESET pin
- Low Voltage Reset (LVR)
- Watchdog Reset
< Figure 1-8. Reset Circuit Diagram >

Advance Information UM-TM59MA41_E
8tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
The nRESET pin must be held to low level for a minimum after the power supply comes within tolerance in
order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation
stabilization time is approximately 2.5 ms (fOSC = 10 MHz). When the CPU is operating in normal state (VDD
and nRESET at High level), if the signal at the nRESET pin is forced Low then the Reset operation starts. All
system and peripheral control registers are set to their default hardware Reset values.
The Low Voltage Reset features static reset when supply voltage is below a reference value. The three
levels of reference voltage can be configured in SYSL register. During the STOP mode. the LVR can be
disabled to decrease power consumption. Please refer 1.8 Power-Down Mode.
The Watchdog Timer is disabled after Reset. F/W can use the CLRWDT instruction to clear and enable the
Watchdog Timer. If once enabled, the Watchdog Timer overflow and generate a chip reset signal if no
CLRWDT executed in a period of 221 oscillator’s cycle (0.25 Second for 8.192MHz crystal). The Watchdog
Timer does not work in Power-down mode to provide wake-up function. It is only designed to prevent F/W
goes into endless loop.
1-8. Power-Down Mode
The Power-down mode is activated by SLEEP instruction. During the Power-down mode, the system clock
(SYS
f) oscillation stops to minimize power consumption and all the peripherals which the same oscillator is
selected as clock source are not working. Therefore, The Power down mode can be terminated by Reset or
enabled external Interrupts (External Interrupt 0, 1). When the Power down mode is released, the clock
circuit requires oscillation stabilization time also. The STOPCON register must be set to ‘10100101b’ before
enter the STOP mode. If the STOPCON is not set to ‘10100101b’, the SLEEP instruction cause system reset.
During the STOP mode, the IVR(internal Voltage Converter) and LVR can disable power consumption. If the
system released from STOP mode, the IVC and LVR and enabled again. It can be controlled by SYSL
register. The IVC level in the SYSL register means the maximum DD
Vlevel which is supplied current system.
Therefore, if you want to disable IVC in STOP mode, you must select the IVC level which is appropriate to
DD
V.
1-9. System Config Register
The System Config Register (SYSL) is the ROM option for initial condition of the MCU. The address 2000H
is virtual address which is not reachable in F/W. It can be written by MDS and system use only.
You can configure read protection, clock source selection, reset pin control , IVR/LVR control at STOP mode
and IVR/LVR reference voltage control in SYSL register. The default value of SYSL is 3FFFh. The 13th bit is
code protection selection bit. If write this bit to 0, the data of ROM will be all 3FFFh, when user read ROM.

Advance Information UM-TM59MA41_E
9tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
Hardware TICE59 DIP switch selection bit:
Code protection selection bit
0 Code protect
6
1 No protect
4-5 Not used
IVC Enable bit
0 Disable IVC in stop mode
3
1 Enable IVC in stop mode
IVC level selection bit
0 0 Vdd in 3.3V
1 0 Vdd in 4.0V
0 1 Vdd in 5.0V
SW5
1-2
1 1 Vdd in 5.5V
PB.2 selection bit
0 nRESET input
SW4 1
1 PB.2 intput
Clock source selection bit
0 0 External crystal /ceramic oscillator
1 0 External RC
SW2 1-2
1 1 Internal RC (4.6MHz in Vdd = 5.0V)
5 Not Used
LVR Enable bit
0 Disable LVR at sleep mode
4
1 Enable LVR at all time
LVR level selection bit
1 0 0 3.9V
1 1 0 3.0V
0 1 1 2.3V
SW1
1-3
Other Not Used

Advance Information UM-TM59MA41_E
10 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
1-10. Instruction Set
Each instruction is a 14-bit word divided into an OPCODE, which specified the instruction type, and one or
more operands, which further specify the operation of the instruction. The instructions can be categorized as
byte-oriented, bit-oriented and literal operations list in the following table. For byte-oriented instructions, “f”
represents address designator and “d” represents destination designator. The address designator is used to
specify which address in Program memory is to be used by the instruction. The destination designator
specifies where the result of the operation is to be placed. If “d” is “0”, the result is placed in the W register. If
“d” is “1”, the result is placed in the address specified in the instruction. For bit-oriented instructions, “b”
represents a bit field designator, which selects the number of the bit affected by the operation, while “f”
represents the address designator. For literal operations, “k” represents the literal or constant value.
Field Description
f Register File Address
b Bit address
k Literal. Constant data or label
d Destination selection field. 0 : Working register 1 : Register file
W Working Register
Z Zero Flag
C Carry Flag
DC Decimal Carry Flag
PC Program Counter
TOS Top Of Stack
GIE Global Interrupt Enable Flag (i-Flag)
[] Option Field
( ) Contents
. Bit Field
←Assign direction
< Table 1-3. OP-CODE Field Description >

Advance Information UM-TM59MA41_E
11 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
Mnemonic Op Code Cycle Flag Affect Description
Byte-Oriented File Register Instruction
ADDWF f,d
00 0111 dfff ffff 1 C,DC,Z Add W and "f"
ANDWF f,d
00 0101 dfff ffff 1 Z AND W with "f"
CLRF f
00 0001 1fff ffff 1 Z Clear "f"
CLRW
00 0001 0100 0000 1 Z Clear W
COMF f,d
00 1001 dfff ffff 1 Z Complement "f"
DECF f,d
00 0011 dfff ffff 1 Z Decrement "f"
DECFSZ f,d
00 1011 dfff ffff 1 or 2 - Decrement "f", skip if zero
INCF f,d
00 1010 dfff ffff 1 Z Increment "f"
INCFSZ f,d
00 1111 dfff ffff 1 or 2 - Increment "f", skip if zero
IORWF f,d
00 0100 dfff ffff 1 Z OR W with "f"
MOVFW f
00 1000 0fff ffff 1 - Move "f" to "w"
MOVWF f
00 0000 1fff ffff 1 - Move W to "f"
RLF f,d
00 1101 dfff ffff 1 C Rotate left "f" through carry
RRF f,d
00 1100 dfff ffff 1 C Rotate right "f" through carry
SUBWF f,d
00 0010 dfff ffff 1 C,DC,Z Subtract W from "f"
SWAPF f,d
00 1110 dfff ffff 1 - Swap nibbles in "f"
TESTZ f
00 1000 1fff ffff 1 Z Test if "f" is zero
XORWF f,d
00 0110 dfff ffff 1 Z XOR W with "f"
Bit-Oriented File Register Instruction
BCF f,b
01 000b bbff ffff 1 - Clear "b" bit of "f"
BSF f,b
01 001b bbff ffff 1 - Set "b" bit of "f"
BTFSC f,b
01 010b bbff ffff 1 or 2 - Test "b" bit of "f", skip if clear
BTFSS f,b
01 011b bbff ffff 1 or 2 - Test "b" bit of "f", skip if set
Literal and Control Instruction
ADDLW k
01 1100 kkkk kkkk 1 C,DC,Z Add Literal "k" and W
ANDLW k
01 1011 kkkk kkkk 1 Z AND Literal "k" with W
CALL k
10 kkkk kkkk kkkk 2 - Call subroutine "k"
CLRWDT
00 0000 1000 1001 1 - Clear and enable Watch Dog Timer
GOTO k
11 kkkk kkkk kkkk 2 - Jump to branch "k"
IORLW k
01 1010 kkkk kkkk 1 Z OR Literal "k" with W
MOVLW k
01 1001 kkkk kkkk 1 - Move Literal "k" to W
NOP
00 0000 0000 0000 1 - No operation
RET
00 0000 0100 0000 2 - Return from subroutine
RETI
00 0000 0110 0000 2 - Return from interrupt
RETLW k
01 1000 kkkk kkkk 2 - Return with Literal "k" in W
SLEEP
00 0000 1000 1010 1 -
Go into standby mode, Clock
oscillation stops
XORLW k
01 1111 kkkk kkkk 1 Z XOR Literal "k" with W
< Table 1-4. Instruction Summary >

Advance Information UM-TM59MA41_E
12 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
ADDLW Add Literal “k” and W
Syntax ADDLW k
Operands k : 00h ~ FFh
Operation (W) ←(W) + k
Status Affected C, DC, Z
OP-Code 01 1100 kkkk kkkk
Description The contents of the W register are added to the eight-bit literal ’k’ and the
result is placed in the W register.
Cycle 1
Example ADDLW 0x15 B : W = 0x10
A : W = 0x25
ADDWF Add W and ‘f’
Syntax ADDWF f [,d]
Operands f : 00h ~ 7Fh d : 0, 1
Operation (Destination) ←(W) + (f)
Status Affected C, DC, Z
OP-Code 00 0111 dfff ffff
Description Add the contents of the W register with register ‘f’. If ‘d’ is 0, the result is
stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.
Cycle 1
Example ADDWF FSR, 0 B : W = 0x17, FSR = 0xC2
A : W = 0xD9, FSR = 0xC2
ANDLW Logical AND Literal "k" with W
Syntax ANDLW k
Operands k : 00h ~ FFh
Operation (W) ←(W) ‘AND’ (f)
Status Affected Z
OP-Code 01 1011 kkkk kkkk
Description The contents of W register are AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Cycle 1
Example ANDLW 0x5F B : W = 0xA3
A : W = 0x03
ANDWF AND W with f
Syntax ANDWF f [,d]
Operands f : 00h ~ 7Fh d : 0, 1
Operation (Destination) ←(W) ‘AND’ (f)
Status Affected Z
OP-Code 00 0101 dfff ffff
Description AND the W register with register ’f’. If ’d’ is 0, the result is stored in the W
register. If ’d’ is 1, the result is stored back in register ’f’.
Cycle 1
Example ANDWF FSR, 1 B : W = 0x17, FSR = 0xC2
A : W = 0x17, FSR = 0x02
BCF Clear "b" bit of "f"
Syntax BCF f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation (f.b) ←0
Status Affected -
OP-Code 01 000b bbff ffff
Description Bit ’b’ in register ’f’ is cleared.
Cycle 1
Example BCF FLAG_REG, 7 B : FLAG_REG = 0xC7
A : FLAG_REG = 0x47

Advance Information UM-TM59MA41_E
13 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
BSF Set "b" bit of "f"
Syntax BSF f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation (f.b) ←1
Status Affected -
OP-Code 01 001b bbff ffff
Description Bit ’b’ in register ’f’ is set.
Cycle 1
Example BSF FLAG_REG, 7 B : FLAG_REG = 0x0A
A : FLAG_REG = 0x8A
BTFSC Test ‘b’ bit of ‘f’, skip if clear(0)
Syntax BTFSC f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation Skip next instruction if (f.b) = 0
Status Affected -
OP-Code 01 010b bbff ffff
Description If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is executed. If bit ‘b’ in
register ‘f’ is ‘0’, then the next instruction is discarded, and a NOP is
executed instead, making this a 2nd cycle instruction.
Cycle 1 or 2
Example LABEL1 BTFSC FLAG, 1
TRUE GOTO SUB1
FALSE ...
B : PC = LABEL1
A : if FLAG.1 = 0, PC = FALSE
if FLAG.1 = 1, PC = TRUE
BTFSS Test "b" bit of "f", skip if set(1)
Syntax BTFSS f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation Skip next instruction if (f.b) = 1
Status Affected -
OP-Code 01 011b bbff ffff
Description If bit ’b’ in register ’f’ is ’0’, then the next instruction is executed. If bit ’b’ in
register ’f’ is ’1’, then the next instruction is discarded, and a NOP is
executed instead, making this a 2nd cycle instruction.
Cycle
Example LABEL1 BTFSS FLAG, 1
TRUE GOTO SUB1
FALSE ...
B : PC = LABEL1
A : if FLAG.1 = 0, PC = TRUE
if FLAG.1 = 1, PC = FALSE
CALL Call subroutine "k"
Syntax CALL k
Operands K : 00h ~ FFFh
Operation Operation: TOS ←(PC)+ 1, PC.11~0 ←k
Status Affected -
OP-Code 10 kkkk kkkk kkkk
Description Call Subroutine. First, return address (PC+1) is pushed onto the stack.
The eleven-bit immediate address is loaded into PC bits <11:0>. CALL is
a two-cycle instruction.
Cycle 2
Example LABEL1 CALL SUB1 B : PC = LABEL1
A : PC = SUB1, TOS = LABEL1+1

Advance Information UM-TM59MA41_E
14 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
CLRF Clear f
Syntax CLRF f
Operands f : 00h ~ 7Fh
Operation (f) ←00h, Z ←1
Status Affected Z
OP-Code 00 0001 1fff ffff
Description The contents of register ‘f’ are cleared and the Z bit is set.
Cycle 1
Example CLRF FLAG_REG B : FLAG_REG = 0x5A
A : FLAG_REG = 0x00, Z = 1
CLRW Clear W
Syntax CLRW
Operands -
Operation (W) ←00h, Z ←1
Status Affected Z
OP-Code 00 0001 0100 0000
Description W register is cleared and Zero bit (Z) is set.
Cycle 1
Example CLRW B : W = 0x5A
A : W = 0x00, Z = 1
CLRWDT Clear Watchdog Timer
Syntax CLRWDT
Operands -
Operation WDTE ←00h
Status Affected -
OP-Code 00 0000 1000 1001
Description CLRWDT instruction enables and resets the Watchdog Timer.
Cycle 1
Example CLRWDT B : WDT counter = ?
A : WDT counter = 0x00
COMF Complement f
Syntax COMF f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation (destination) ←(f
_
)
Status Affected Z
OP-Code 00 1001 dfff ffff
Description The contents of register ’f’ are complemented. If ’d’ is 0, the result is
stored in W. If ’d’ is 1, the result is stored back in register ’f’.
Cycle 1
Example COMF REG1,0 B : REG1 = 0x13
A : REG1 = 0x13, W = 0xEC
DECF Decrement f
Syntax DECF f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation (destination) ←(f) - 1
Status Affected Z
OP-Code 00 0011 dfff ffff
Description Decrement register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’
is 1, the result is stored back in register ‘f’.
Cycle 1
Example DECF CNT, 1 B : CNT = 0x01, Z = 0
A : CNT = 0x00, Z = 1

Advance Information UM-TM59MA41_E
15 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
DECFSZ Decrement f, Skip if 0
Syntax DECFSZ f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation (destination) ←(f) - 1, skip next instruction if result is 0
Status Affected -
OP-Code 00 1011 dfff ffff
Description The contents of register ’f’ are decremented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is placed back in register ’f’. If the
result is 1, the next instruction is executed. If the result is 0, then a NOP is
executed instead, making it a 2 cycle instruction.
Cycle 1 or 2
Example LABEL1 DECFSZ CNT, 1
GOTO LOOP
CONTINUE
B : PC = LABEL1
A : CNT = CNT – 1
if CNT=0, PC = CONTINUE
if CNT≠0, PC = LABEL1+1
GOTO Unconditional Branch
Syntax GOTO k
Operands k : 00h ~ FFFh
Operation PC.11~0 ←k
Status Affected -
OP-Code 11 kkkk kkkk kkkk
Description GOTO is an unconditional branch. The 12-bit immediate value is loaded
into PC bits <11:0>. GOTO is a two-cycle instruction.
Cycle 2
Example LABEL1 GOTO SUB1 B : PC = LABEL1
A : PC = SUB1
INCF Increment f
Syntax INCF f [,d]
Operands f : 00h ~ 7Fh
Operation (destination) ←(f) + 1
Status Affected Z
OP-Code 00 1010 dfff ffff
Description The contents of register ’f’ are incremented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is placed back in register ’f’.
Cycle 1
Example INCF CNT, 1 B : CNT = 0xFF, Z = 0
A : CNT = 0x00, Z = 1
INCFSZ Increment f, Skip if 0
Syntax INCFSZ f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation (destination) ←(f) + 1, skip next instruction if result is 0
Status Affected -
OP-Code 00 1111 dfff ffff
Description The contents of register ’f’ are incremented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is placed back in register ’f’. If the
result is 1, the next instruction is executed. If the result is 0, a NOP is
executed instead, making it a 2 cycle instruction.
Cycle 1 or 2
Example LABEL1 INCFSZ CNT, 1
GOTO LOOP
CONTINUE
B : PC = LABEL1
A : CNT = CNT + 1
if CNT=0, PC = CONTINUE
if CNT≠0, PC = LABEL1+1

Advance Information UM-TM59MA41_E
16 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
IORLW Inclusive OR Literal with W
Syntax IORLW k
Operands k : 00h ~ FFh
Operation (W) ←(W) OR k
Status Affected Z
OP-Code 01 1010 kkkk kkkk
Description The contents of the W register is OR’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Cycle 1
Example IORLW 0x35 B : W = 0x9A
A : W = 0xBF, Z = 0
IORWF Inclusive OR W with f
Syntax IORWF f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation (destination) ←(W) OR k
Status Affected Z
OP-Code 00 0100 dfff ffff
Description Inclusive OR the W register with register ’f’. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is placed back in register ’f’.
Cycle 1
Example IORWF RESULT, 0 B : RESULT = 0x13, W = 0x91
A : RESULT = 0x13, W = 0x93, Z = 0
MOVFW Move f to W
Syntax MOVFW f
Operands f : 00h ~ 7Fh
Operation (W) ←(f)
Status Affected -
OP-Code 00 1000 0fff ffff
Description The contents of register f are moved to W register.
Cycle 1
Example MOVFW FSR, 0 B : W = ?
A : W ←f
MOVLW Move Literal to W
Syntax MOVLW k
Operands k : 00h ~ FFh
Operation (W) ←k
Status Affected -
OP-Code 01 1001 kkkk kkkk
Description The eight-bit literal ‘k’ is loaded into W register. The don’t cares will
assemble as 0’s.
Cycle 1
Example MOVLW 0x5A B : W = ?
A : W = 0x5A
MOVWF Move W to f
Syntax MOVWF f
Operands f : 00h ~ 7Fh
Operation (f) ←(W)
Status Affected -
OP-Code 00 0000 1fff ffff
Description Move data from W register to register ‘f’.
Cycle 1
Example MOVWF REG1 B : REG1 = 0xFF, W = 0x4F
A : REG1 = 0x4F, W = 0x4F

Advance Information UM-TM59MA41_E
17 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
NOP No Operation
Syntax NOP
Operands -
Operation No Operation
Status Affected Z
OP-Code 00 0000 0000 0000
Description No Operation
Cycle 1
Example NOP -
RETI Return from Interrupt
Syntax RETI
Operands -
Operation PC ←TOS, GIE ←1
Status Affected -
OP-Code 00 0000 0110 0000
Description Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded
in to the PC. Interrupts are enabled. This is a two-cycle instruction.
Cycle 2
Example RETFIE A : PC = TOS, GIE = 1
RETLW Return with Literal in W
Syntax RETLW k
Operands k : 00h ~ FFh
Operation PC ←TOS, (W) ←k
Status Affected -
OP-Code 01 1000 kkkk kkkk
Description The W register is loaded with the eightbit literal ’k’. The program counter
is loaded from the top of the stack (the return address). This is a two-
cycle instruction.
Cycle 2
Example CALL TABLE
:
TABLE :
ADDWF PCL,1
RETLW k1
RETLW k2
:
RETLW kn
B : W = 0x07
A : W = value of k8
RET Return from Subroutine
Syntax RET
Operands -
Operation PC ←TOS
Status Affected -
OP-Code 00 0000 0100 0000
Description Return from subroutine. The stack is POPed and the top of the stack
(TOS) is loaded into the program counter. This is a two-cycle instruction.
Cycle 2
Example RETURN A : PC = TOS

Advance Information UM-TM59MA41_E
18 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
RLF Rotate Left f through Carry
Syntax RLF f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation CRegister f
Status Affected C
OP-Code 00 1101 dfff ffff
Description The contents of register ‘f’ are rotated one bit to the left through the Carry
Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is
stored back in register ‘f’.
Cycle 1
Example RLF REG1,0 B : REG1 = 1110 0110, C = 0
A : REG1 = 1110 0110
W = 1100 1100, C = 1
RRF Rotate Right f through Carry
Syntax RRF f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation CRegister f
Status Affected C
OP-Code 00 1100 dfff ffff
Description The contents of register ‘f’ are rotated one bit to the right through the
Carry Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the
result is placed back in register ‘f’.
Cycle 1
Example RRF REG1,0 B : REG1 = 1110 0110, C = 0
A : REG1 = 1110 0110
W = 0111 0011, C = 0
SLEEP Go into standby mode, Clock oscillation stops
Syntax SLEEP
Operands -
Operation -
Status Affected -
OP-Code 00 0000 1000 1010
Description Go into SLEEP mode with the oscillator stopped.
Cycle 1
Example SLEEP -

Advance Information UM-TM59MA41_E
19 tenx technology, inc.
Preliminary Rev 1.2, 2008/05/19
X
SUBWF Subtract W from f
Syntax SUBWF f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation (destination) ←(f) – (W)
Status Affected C, DC, Z
OP-Code 00 0010 dfff ffff
Description Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is 0,
the result is stored in the W register. If ‘d’ is 1, the result is stored back in
register ‘f’.
Cycle 1
Example SUBWF REG1,1
SUBWF REG1,1
SUBWF REG1,1
B : REG1 = 3, W = 2, C = ?, Z = ?
A : REG1 = 1, W = 2, C = 1, Z = 0
B : REG1 = 2, W = 2, C = ?, Z = ?
A : REG1 = 0, W = 2, C = 1, Z = 1
B : REG1 = 1, W = 2, C = ?, Z = ?
A : REG1 = FFh, W = 2, C = 0, Z = 0
SWAPF Swap Nibbles in f
Syntax SWAPF f [,d]
Operands f : 00h ~ 7Fh, d : 0, 1
Operation (destination,7~4) ←(f.3~0), (destination.3~0) ←(f.7~4)
Status Affected -
OP-Code 00 1110 dfff ffff
Description The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is 0, the
result is placed in W register. If ‘d’ is 1, the result is placed in register ‘f’.
Cycle 1
Example SWAPF REG, 0 B : REG1 = 0xA5
A : REG1 = 0xA5, W = 0x5A
TESTZ Test if ‘f’ is zero
Syntax TESTZ f
Operands f : 00h ~ 7Fh
Operation Set Z flag if (f) is 0
Status Affected Z
OP-Code 00 1000 1fff ffff
Description If the content of register ‘f’ is 0, Zero flag is set to 1.
Cycle 1
Example TESTZ REG1 B : REG1 = 0, Z = ?
A : REG1 = 0, Z = 1
XORLW Exclusive OR Literal with W
Syntax XORLW k
Operands k : 00h ~ FFh
Operation (W) ←(W) XOR k
Status Affected Z
OP-Code 01 1111 kkkk kkkk
Description The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
Cycle 1
Example XORLW 0xAF B : W = 0xB5
A : W = 0x1A