Terasic ALTERA DE4 User manual

DE4 User Manual
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June 20, 2018

DE4 User Manual
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CONTENTS
CHAPTER 1 OVERVIEW ..........................................................................................................................................4
1.1 GENERAL DESCRIPTION ............................................................................................................................................4
1.2 KEY FEATURES..........................................................................................................................................................5
1.3 BOARD OVERVIEW....................................................................................................................................................6
1.4 BLOCK DIAGRAM......................................................................................................................................................7
CHAPTER 2 USING THE DE4 BOARD ................................................................................................................13
2.1 CONFIGURATION OPTIONS ......................................................................................................................................13
2.2 SETUP ELEMENTS....................................................................................................................................................20
2.3 STATUS ELEMENTS..................................................................................................................................................21
2.4 GENERAL USER INPUT/OUTPUT ..............................................................................................................................22
2.5 HIGH-SPEED MEZZANINE CARDS............................................................................................................................26
2.6 GPIO EXPANSION HEADERS ...................................................................................................................................37
2.7 DDR2 SO-DIMM...................................................................................................................................................41
2.8 USB OTG...............................................................................................................................................................49
2.9 SD CARD ................................................................................................................................................................52
2.10 CLOCK CIRCUITRY ................................................................................................................................................53
2.11 PCI EXPRESS.........................................................................................................................................................57
2.12 GIGABIT ETHERNET (GIGE) ..................................................................................................................................60
2.13 SERIALATA(SATA) .............................................................................................................................................63
2.14 RS-232 SERIAL PORT............................................................................................................................................66
2.15 FLASH MEMORY .................................................................................................................................................66
2.16 SSRAM MEMORY ................................................................................................................................................68
2.17 I2C SERIAL EEPROM ..........................................................................................................................................70
2.18 TEMPERATURE SENSOR.........................................................................................................................................70
2.19 POWER..................................................................................................................................................................71
CHAPTER 3 CONTROL PANEL ............................................................................................................................74
3.1 CONTROL PANEL SETUP ..........................................................................................................................................74
3.2 CONTROLLING THE LEDS AND 7-SEGMENT DISPLAYS ............................................................................................78
3.3 SWITCH/BUTTON...............................................................................................................................................80
3.4 MEMORY CONTROLLER...........................................................................................................................................81

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3.5 USB2.0 OTG..........................................................................................................................................................84
3.6 SD CARD...............................................................................................................................................................85
3.7 TEMPERATURE MONITOR ........................................................................................................................................86
3.8 POWER....................................................................................................................................................................87
3.9 PLL ........................................................................................................................................................................88
3.10 SATA....................................................................................................................................................................89
3.11 HSMC ..................................................................................................................................................................90
3.12 FAN .......................................................................................................................................................................91
CHAPTER 4 DE4 SYSTEM BUILDER ..................................................................................................................93
4.1 INTRODUCTION .......................................................................................................................................................93
4.2 GENERAL DESIGN FLOW.........................................................................................................................................94
4.3 USING DE4 SYSTEM BUILDER ................................................................................................................................95
CHAPTER 5 EXAMPLES OF ADVANCED DEMONSTRATION ....................................................................106
5.1 USB HOST............................................................................................................................................................106
5.2 USB DEVICE......................................................................................................................................................... 115
5.3 ETHERNET –SIMPLE SOCKET SERVER................................................................................................................... 119
5.4 SD CARD READER ................................................................................................................................................127
5.5 DDR2 SDRAM ....................................................................................................................................................131
5.6 EXTERNAL CLOCK GENERATOR ............................................................................................................................135
5.7 POWER MEASUREMENT ........................................................................................................................................142
5.8 WEB SERVER.........................................................................................................................................................146
5.9 SERIALATA(SATA) .............................................................................................................................................155
5.10 HIGH-SPEED MEZZANINE CARD (HSMC)...........................................................................................................156
5.11 PCIE DEMONSTRATION .......................................................................................................................................158
ADDITIONAL INFORMATION ...................................................................................................................................159

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Chapter 1
Overview
This chapter provides an overview of the DE4 Development Board and details the components and
features of the board.
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1. .1 1 G Ge en ne er ra al l D De es sc cr ri ip pt ti io on n
The DE4 Development Board provides the ideal hardware platform for system designs that demand
high-performance, serial connectivity, and advanced memory interfacing. Developed specifically to
address the rapidly evolving requirements in many end markets for greater bandwidth, improved
jitter performance, and lower power consumption. The DE4 is powered by the Stratix® IV GX
device and supported by industry-standard peripherals, connectors and interfaces that offer a rich set
of features that is suitable for a wide range of compute-intensive applications.
The advantages of the Stratix® IV GX FPGA platform with integrated transceivers have allowed
the DE4 to fully compliant with version 2.0 of the PCI Express standard. This will accelerate
mainstream development of PCI Express-based applications enabling customers to deploy designs
for a broad range of high-speed connectivity applications. The DE4 coupled with serial ATA (SATA)
interfaces, offer a solution for developing storage applications. The DE4 delivers fully tested and
supported connectivity targeted reference design that integrates built-in blocks for PCI Express,
SATA transceiver verification testing, and Gigabit Ethernet protocol.
The DE4 is supported by multiple reference designs and two High-Speed Mezzanine Card (HSMC)
connectors that allow scaling and customization with mezzanine daughter cards. For large-scale
ASIC prototype development, it can be established by a cable connecting to multiple DE4/FPGA
boards through the HSMC connectors.
It is highly recommended that users read the DE4 Getting Started Guide.pdf before using the DE4

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board.
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1. .2 2 K Ke ey y F Fe ea at tu ur re es s
The following hardware is implemented on the DE4 board:
Featured device
oAltera Stratix® IV GX FPGA (EP4SGX230C2/EP4SGX530C2)
Configuration status and set-up elements
oBuilt-in USB Blaster circuit for programming
oFast passive parallel (FPP) configuration via MAX II CPLD and flash memory
oThree External Programmable PLL timing chip
Component and interfaces
oFour Gigabit Ethernet (GigE) with RJ-45 connector
oTwo host and two device Serial ATA (SATA II) ports
oTwo HSMC connectors
oTwo 40-pin expansion headers
oPCI Express 2.0 (x8 lane) connector
Memory
oDDR2 SO-DIMM socket
oFLASH
oSSRAM
oSD Card socket
oI2C EEPROM
General user input/output:
o8 LEDs
o4 push-buttons and 4 slide switches
o8-position DIP switch
o2 seven-segment displays
Clock system
oOn-board clock oscillators: 50MHz and 100MHz

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oSMA connectors for external clock input
oSMA connectors for clock output
Other interfaces
oUSB 2.0 high-speed host/device OTG
oCurrent sensor for FPGA current measurement
oTemperature sensor
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1. .3 3 B Bo oa ar rd d O Ov ve er rv vi ie ew w
Figure 1–1and Figure 1–2 is the top and bottom view of the DE4 board. It depicts the layout of the
board and indicates the location of the connectors and key components. Users can refer to this
figure for relative location when the connectors and key components are introduced in the following
chapters.
Figure 1–1 The DE4 board (Top view)

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Figure 1–2The DE4 board (Bottom view)
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1. .4 4 B Bl lo oc ck k D Di ia ag gr ra am m
Figure 1–3shows the block diagram of the DE4 board. To provide maximum flexibility for the
users, all key components are connected with the Stratix IV GX FPGA device. Thus, users can
configure the FPGA to implement any system design.

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Figure 1–3 Block diagram of the DE4 board
Below is more detailed information regarding the blocks in Figure 1–3.

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Stratix IV GX FPGA
EP4SGX230C2
o228,000 logic elements (LEs)
o17,133 total memory Kbits
o1,288 18x18-bit multipliers blocks
o2 PCI Express hard IP blocks
o744 user I/Os
o8 phase locked loops (PLLs)
EP4SGX530C2
o531,200 logic elements (LEs)
o27,376K total memory Kbits
o1,024 18x18-bit multipliers blocks
o4 PCI Express hard IP Blocks
o744 user I/Os
o8 phase locked loops (PLLs)
Configuration device and USB Blaster circuit
MAXII CPLD EPM2210 System Controller and Fast Passive Parallel (FPP) configuration
On-board USB Blaster for use with the Quartus II Programmer
Programmable PLL timing chip configured via MAX II CPLD
Support JTAG mode
Memory devices
64MB Flash (32M x16) with a 16-bit data bus
2MB SSRAM (1M x 16)
2Kb EEPROM

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Two DDR2 SO-DIMM sockets
Up to 8GB capacity in total
Maximum memory clock rate at 400MHz
Theortical Bandwidth over 102Gbps
SD Card socket
Provides SPI and 4-bit SD mode for SD Card access
General user I/O
8 user controllable LEDs
2 seven-segment displays
8 user DIP switches
Push-buttons
4 user-defined inputs
Normally high; generates one active-low pulse when the switch is pressed
Slide switches
4 slide switches for user-defined inputs
When a switch is set to the DOWN or UP position, it causes logic 0 or 1, respectively.
On-Board Clocking Circuitry
50MHz/100MHz oscillator
2 SMA connector for external transceiver clock input
4 SMA connector for LVDS clock input/output
2 SMA connectors for clock output

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1 SMA connector for external clock input
Four Serial ATA ports
SATA 3.0 standard 6Gbps signaling rate
Four Gigabit Ethernet ports
Integrated 1.25GHz SERDES
PCI Express x8 edge connector
Support connection speed of Gen1 at 2.5Gbps/lane to Gen2 at 5.0Gbps/lane
Connection established with PC motherboard with x8 or x16 PCI Express slot
Two High Speed Mezzanine Card (HSMC)
2 female-HSMC connectors
Total of 12 pairs CDR-based transceivers at data rate up to 8.5Gbps
Total 38 LVDS transmitter channels at data rate up to 1.6Gbps, and 36 LVDS receiver channels
I/O voltage 2.5V
Two 40-pin expansion headers
72 FPGA I/O pins, as well as 4 power and ground lines, are brought out to two 40-pin
expansion connectors
40-pin header is designed to accept a standard 40-pin ribbon cable used for IDE hard drives
Compatible with I/O standard 3.3V

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USB Host/Slave controller
Complies fully with Universal Serial Bus Specification Rev. 2.0
Support data transfer at high-speed, full-speed, and low-speed
Support both USB host and device
Three USB ports (one type mini-AB for host/device and two type A for host)
Support Nios II with the Terasic driver
Power
Standalone DC inputs 12V and 3.3V
PCI Express edge connector power
Optional PCI Express external power source
On-Board power measurement circuitry

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Chapter 2
Using the DE4 Board
This chapter gives instructions for using the DE4 board and its components.
It is strongly recommended that users read the DE4 Getting Started Guide.pdf before using the DE4
board. The document is located in the Usermanual folder on the DE4 System CD. The contents of
the document include the following:
Introduction to the DE4 development board
DE4 development kit contents
Key features
Before you begin
Software Installation
Development board setup
Programming the Stratix IV GX device on the DE4 board
Programming through the Flash memory device
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2. .1 1 C Co on nf fi ig gu ur ra at ti io on n O Op pt ti io on ns s
JTAG FPGA Programming over USB-Blaster
The USB-blaster is implemented on the DE4 board to provide JTAG configuration through onboard
USB-to-JTAG configuration logic using a type-B USB connector, a FTDI USB 2.0 Controller, and
an Altera MAX II CPLD. Current configuration will be lost when the power is turned off. Figure
2–1illustrates the JTAG configuration scheme for the DE4.

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To download a configuration bit stream into the Stratix IV GX FPGA, perform the following steps:
Make sure that power is provided to the DE4 board
Connect the USB cable supplied directly to the USB Blaster port of the DE4 board
The FPGA can now be programmed in the Quartus II Programmer by selecting a configuration
bit stream file with the .sof filename extension.
Please refer to DE4 Getting Started Guide.pdf for more detailed procedure of FPGA programming.
Figure 2–1 JTAG configuration scheme
Flash Programming
The DE4 development board contains a common flash interface (CFI) flash memory to meet the
demands for a larger FPGA configuration storage. The parallel flash loader (PFL) feature in MAX
II devices provides an efficient method to program CFI flash memory devices through the JTAG

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interface and the logic to control configuration from the flash memory device to the Stratix IV GX
FPGA. Figure 2–2depicts the connection setup between the CFI flash memory, Max II CPLD, and
Stratix IV GX.
Please refer to the DE4 Getting Started Guide.pdf for the basic programming instruction on parallel
flash loader on the CFI flash memory.
Figure 2–2 Flash programming scheme
Programming Flash Memory using batch file
The DE4 provides a program_flash batch file (\demonstrations\de4_<Stratix device>\de4_board_
update_portal\demo_batch\Program_flash) to limit the steps that are taken when users program the
flash memory on the DE4.
Software Requirements:
Quartus II 9.1 SP2 or later
Nios II IDE tools 9.1 SP2 or later
Program_flash folder contents:
Program_flash.bat
Program_flash.pl
Program_flash.sh

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de4_board_update_portal.sof
Before you use the program_flash.bat batch file to program the flash memory, make sure the DE4 is
turned on and USB cable is connected to the USB blaster port (J5). In addition, place the .sof
and .elf file (optional) you wish to program/convert in the Program_flash directory.
Programming Flash Memory with .sof using Program_flash.bat
1. Launch the program_flash.bat batch file from the directory (\demonstrations\de4_<Stratix
device>\de4_board_update_portal\demo_batch\Program_flash) of the DE4 system CD-ROM.
2. The flash program tool shows the menu options.
Figure 2–3 Flash program tools
3. Select option 2.

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Figure 2–4 Option 2
4. Enter the .sof file name to be programmed onto the flash memory.
Figure 2–5 Enter .sof name to be program
5. The following lines will appear during flash programming: ‘Extracting Option bits SREC’,
‘Extracting FPGA Image SREC’, and ‘Deleting intermediate files’. If these lines don’t appear
on the windows command, programming on the flash memory is not successfully setup. Please
make sure Quartus II 9.1 SP2 and Nios II 9.1 IDE SP2 or later is used.

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Figure 2–6 Loading .sof file to be program
6. Erasing flash.
Figure 2–7 Erasing flash
7. Programming flash.

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Figure 2–8 Programming flash
8. Programming complete.
Figure 2–9 Programming flash complete

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2
2. .2 2 S Se et tu up p E El le em me en nt ts s
JTAG Control DIPSwitch
The JTAG control DIP switch is provided to either remove or include devices in the active JTAG
chain. The JTAG signals (TDI and TDO) found on the HSMC connectors and PCIe interface can be
enabled using a 3-position DIP switch. In the “OFF” position, the TDI and TDO signals are looped,
similarly in the “ON” position, the JTAG signals are bypassed. Table 2–1lists the position of the
DIP switch and their associated interface.
Table 2–1SW8 JTAG Control DIPSwitch
Board Reference
Signal Name
Description
Default
SW8.1
JTAG_HSMA_EN
On : Bypass HSMA
Off: HSMA In-chain
On
SW8.2
JTAG_HSMB_EN
On: Bypass HSMB
Off: HSMB In-chain
On
SW8.3
JTAG_PCIE_EN
On: Bypass PCI Express
Off : PCI Express In-Chain
On
PCI Express Control DIP switch
The PCI Express Control DIP switch is provided to enable or disable different configurations of the
PCIe Connector. Table 2–2 lists the switch controls and description.
Table 2–2 SW9 PCIe Control DIPSwitch
Board Reference
Signal Name
Description
Default
SW9.1
PCIE_PRSNT2n_x1
On : Enable x1 presence detect
Off: Disable x1 presence detect
Off
SW9.2
PCIE_PRSNT2n_x4
On : Enable x4 presence detect
Off: Disable x4 presence detect
Off
SW9.3
PCIE_PRSNT2n_x8
On : Enable x8 presence detect
Off: Disable x8 presence detect
On