Terasic TSOM User manual

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TABLE OF CONTENTS
Chapter 1 Introduction ...................................................................................................................2
1.1 TSoM Design Package........................................................................................................................2
1.2 Getting Help........................................................................................................................................2
Chapter 2 Board Specification .........................................................................................................3
2.1 Layout and Components.....................................................................................................................3
2.2 Block Diagram....................................................................................................................................3
2.3 Mechanical Specifications ..................................................................................................................5
2.4 Power Requirement.............................................................................................................................5
Chapter 3 System Interface ............................................................................................................. 7
3.1 Device Configuration..........................................................................................................................7
3.2 Clock System....................................................................................................................................10
3.3 Reset System.....................................................................................................................................11
3.4 260-pin Edge Connector...................................................................................................................11
Chapter 4 HPS Fabric Components ............................................................................................... 13
4.1 USB 2.0.............................................................................................................................................13
4.2 Gigabit Ethernet................................................................................................................................14
4.3 eMMC...............................................................................................................................................15
4.4 HPS 3.3V GPIO................................................................................................................................16
4.5 DDR3................................................................................................................................................18
Chapter 5 FPGA Fabric Components............................................................................................. 21
5.1 DDR3................................................................................................................................................21
5.2 FPGA IOs on 260-Pin Edge Connector ............................................................................................23

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Chapter 1
Introduction
TSoM (Terasic SoC System on Module) are small, integrated single-board computers with
Cyclone® V SoCs at the core. The SoC SoM includes DDR3 memory, flash memory, power
management, common interface controllers, and board support package (BSP) software to help you
create a fully customized embedded design without starting from scratch.
1
1. .1 1 T TS So oM M D De es si ig gn n P Pa ac ck ka ag ge e
The TSoM design package contains all the documents and supporting materials associated with
TSoM module, including the user manual, system builder, reference designs, and device datasheets.
Users can download this design package from the link: http://TSoM.terasic.com/cd.
1
1. .2 2 G Ge et tt ti in ng g H He el lp p
Here are the addresses where you can get help if you encounter any problems:
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: [phone]
Website: TSoM.terasic.com

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Chapter 2
Board Specification
This chapter provides an introduction to the features and design characteristics of the module.
2
2. .1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
Figure 2-1 shows a photograph of the module. It depicts the layout of the module and indicates the
location of the connectors and key components.
Note: The Cyclone® V system-on-a-chip (SoC) is composed of two distinct portions: a single or
dual-core Arm® Cortex® A9 hard processor system (HPS) and an FPGA. The HPS architecture
integrates a wide set of peripherals that reduce board size and increase performance within a
system.
Figure 2-1 Mechanical Layout of the TSoM Module
2
2. .2 2 B Bl lo oc ck k D Di ia ag gr ra am m
Figure 2-2 is the block diagram of the module. The most FPGA I/Os of TSoM module are all
connected to the onboard 260-pin Edge connector, then it’s easy to connected to customer’s main
board.

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Figure 2-2 Block diagram of the TSoM Module
Detailed information about Figure 2-2 are listed below.
◼Module:
⚫FPGA: Cyclone V SE 5CSEBA6U23I7NDK (110K LEs)
⚫Interface: DDR4 Edge (include 3.3V power source)
⚫Dimension: 50 mm x 70 mm
◼FPGA Fabric side:
⚫DDR3 SDRAM 1GB, 32bit –303MHz (Soft IP)
⚫LVDS Transmitter x15 & LVDS Receiver x17 pairs & GPIO x3 ( Total GPIO x67)
⚫Optional EPCS64
◼HPS Fabric side:
⚫Boot Selection DIP Switch: boot from eMMC or MicroSD Card
⚫DDR3 SDRAM 1GB, 32bit - 400MHz
⚫USB 2.0 PHY
⚫Gigabit Ethernet PHY
⚫3.3V GPIO x25 (Can/UART/SPI/I2C/Trace Buses)
⚫1.5V GPI x4 (Input pins)
⚫Optional eMMC 8GB

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2
2. .3 3 M Me ec ch ha an ni ic ca al l S Sp pe ec ci if fi ic ca at ti io on ns s
Figure 2-3 is the Mechanical Layout of TSoM module and Table 2-1 shows the mechanical data of
the TSoM module.
Figure 2-3 Mechanical Layout of the TSoM Module
Table 2-1 Mechanical data of the TSoM Module
Symbol
Value
Size
70 x50mm
2
2. .4 4 P Po ow we er r R Re eq qu ui ir re em me en nt t
The TSoM module is powered by the 260-pin edge connector. The user only needs to supply
3.3V/6A to the 260-pin edge connector of the TSoM module. The power circuit on the TSoM
module can convert 3.3V to 1.1V/1.2V/1.5V/1.8V/2.5V, which then is supplied to the FPGA and
other components. Figure 2-4 shows the power tree of TSoM module.

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Figure 2-4 Power Tree of the TSoM Module

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Chapter 3
System Interface
This chapter will introduce the system level interfaces on the TSoM module. Users can get the Boot
method of the HPS, the clock and reset system on the module, and the detailed pin distribution of
the 260-pin edge connector connected externally.
3
3. .1 1 D De ev vi ic ce e C Co on nf fi ig gu ur ra at ti io on n
This section describes the various interfaces on the TSoM module that can be configured with
FPGAs and HPS. Users can learn about the JTAG interface on TSoM module, the sources that can
be used as boot devices on the HPS side, and the configuration chips on the FPGA side through this
section.
◼JTAG
Figure 3-1 is the JTAG interface on TSoM module, users can configure the FPGA from host PC
through the JTAG interface, the HPS is also included in the JTAG chain on TSoM module which
allows user to debug and develop the HPS ARM through the JTAG interface. The JTAG signals
come from the 260-pin edge connector, USB Blaster circuit or external Blaster connector need to be
reserved on customer’s main board for the JTAG communication with the FPGA on the TSoM
module.
Figure 3-1 JTAG Interface on the TSoM Module
◼HPS Boot Mode
As shown in Figure 3-2, The TSoM module has two HPS boot source, one is the 8G eMMC
(Embedded Multimedia Card) memory, another is the external boot device on the 260-pin edge
connector. When the 260-pin edge connector is connected to the main board which contains

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external SD card socket or QSPI flash, the external SD card socket is used as the HPS boot source.
Only one of the two boot sources can be chosen for the boot source on TSoM board . User can
control the multiplexer and choose eMMC or external boot device as the boot source through SW1,
as shown in Table 3-1.
Figure 3-2 Boot Source on the TSoM Module
Table 3-1 SW1 Setting for Boot Source
SW1 Status
Boot Source
ON Position
eMMC device
OFF Position
External SD card
In addition, the QSPI interface on the TSoM HPS side is connected to the 260-pin edge connector
(HPS_V3P3_GPIO[24..19]), so user also can use the external QSPI flash as the HSP boot source by
connecting QSPI flash on the external main board to the TSoM 260-pin edge connector. But please
note that the HPS boot source setting control pins (HPS_BOOTSEL[2:0]) are by default set as
SD/MMC mode by the resistors, as shown in Figure 3-3. To set the external QSPI flash as the HPS
source, user needs to set HPS_BOOTSEL[2:0] as "111". Figure 3-4 shows the resistors setting.

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Figure 3-3 Using QSPI Flash as HPS boot source on the TSoM Module
Figure 3-4 HPS_BOTSEL[2..0] resistors setting
◼EPCS
There is an EPCS64 configuration device reserved on the TSoM module. The EPCS device is a
flash memory device that can store configuration data that you use for FPGA configuration purpose
after powering on. You can use the EPCS device on all FPGAs that support AS x1configuration
scheme. User needs to modify the setting resistors of the FPGA MSEL pins if they want to use the
EPCS64 device. The factory setting of the MSEL[4:0] on the TSoM module is FPPx32 mode which
is used to configure FPGA from HPS. If user wants to the EPCS64 device, he can modify the
resistors as shown in Figure 3-5 to set the MSEL[4:0] as "10010" to switch to AS mode. Figure 3-6
and Figure 3-7 show the resistors actual position on the TSoM module (Top and Bottom Side).
Figure 3-5 MSEL[4:0] Setting Resistors (FPPx32 Mode)

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Figure 3-6 MSEL[4:0] Setting Resistors on the TSoM Module (Top Side)
Figure 3-7 MSEL[4:0] Setting Resistors on the TSoM Module (Bottom Side)
3
3. .2 2 C Cl lo oc ck k S Sy ys st te em m
The clock source on the TSoM module is provided by an Si5350C clock generator, which can
generate several groups of clocks for the devices on the TSoM module. The Si5350C generates
25MHz clock for the clock groups in the HPS, and provides two 50MHz clocks for the FPGA fabric
to drive customer’s design. Users also can multiple or devise the 50MHz clock through the FPGA
internal PLL. The Si5350C also provides clock for Ethernet PHY and USB OTG PHY.
Besides the Si5350C clock generator, users can input/output clock to the FPGA through the 260-pin
edge connector. There are four pairs LVDS clock inputs and two pairs LVDS clock outputs defined
on the 260-pin edge connector. These I/O are all connected to the dedicated clock pin of the FPGA
and can also be used as Single-end.

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Figure 3-8 Clock System of the TSoM Module
3
3. .3 3 R Re es se et t S Sy ys st te em m
The TSoM module provides warm reset and cold reset function for the HPS, as shown in the Figure
3-9. The cold reset comes from external mainboard and is used for HPS Ethernet PHY, USB OTG
PHY and eMMC memory through the 260-pin edge connector. The HPS_nRST pin is connected to
the 260-pin edge connector to be reserved for Intel DS-5 software tool to reset the HPS and connect
to the USB Blaster connector of the mainboard.
Figure 3-9 Reset System of the TSoM Module
3
3. .4 4 2 26 60 0- -p pi in n E Ed dg ge e C Co on nn ne ec ct to or r
The TSoM module can be connected to external mainboard through the 260-pin edge connector
with the same specification (See Figure 3-10.), all the externally connected signals on the TSoM
module are communicated with and transferred to external main board through the edge connector,
which includes the FPGA and HPS I/O, the circuit of Ethernet PHY and USB OTG PHY, and also

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provides system power and JTAG function. Users can refer to TSoM schematic for the detailed
signal connections. Users can connect the TSoM module to the main board that contains DDR4
SODIMM socket. Table 3-2 lists the several recommended DDR4 SODIMM sockets for reference.
Table A-1 in the Appendix chapter shows the detailed pin assignments of the 260-pin edge
connector.
Figure 3-10 260-pin edge connector on the TSoM module
Table 3-2 DDR4 SODIMM Socket
Vendor
Part
Number
Descriptions
TE
Connectivity
2309409-3
TE Connectivity DDR4 SODIMM 260P 5.2H STD
BellWether
80888-2023
DDR4 5.2H Connector 0.5mm Pitch, 260 Circuits Standard Type, SMT
Type, 10u"

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Chapter 4
HPS Fabric
Components
The HPS and FPGA portions of the device each have their own pins. Pins are not freely shared
between the HPS and the FPGA fabric. This chapter will describe the peripherals connected to HPS
fabric, such as DDR3, Ethernet, eMMC and USB OTG.
4
4. .1 1 U US SB B 2 2. .0 0
The TSoM module has a single Host/Device (USB OTG) USB 2.0 PHY that connects to the SoC
device, the PHY can operate in USB host, USB device and USB On-The-Go (host and device
capable) modes. The PHY is connected to the 260-pin DDR4 SO-DIMM edge connector. The
following Figure 4-1 shows the connections between the USB 2.0 PHY and the HPS.
Note: There is only a USB 2.0 OTG PHY on the TSoM module (without any USB physical
interface), for using this function, users need to connect a TSoM Based Board (or other customized
expansion board) to implement the connection between the USB 2.0 OTG PHY and a USB physical
interface.
Figure 4-1 The Connections between the USB 2.0 PHY and the HPS
The ULPI interface is connected to HPS pins for use with the integrated USB controller. The USB
reset has a pull-down resistor and needs to be driven high to release the PHY from reset.
Table 4-1 lists the pin assignment of the USB 2.0 PHY and the HPS.
Table 4-1 the USB 2.0 PHY Pin Assignments
Signal Name
HPS Pin No.
Description
I/O Standard
HPS_USB_CLKOUT
PIN_G4
Reference Clock Output
3.3V
HPS_USB_DATA[1]
PIN_C10
HPS_USB_DATA[1]
3.3V
HPS_USB_DATA[1]
PIN_F5
HPS_USB_DATA[1]
3.3V

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HPS_USB_DATA[2]
PIN_C9
HPS_USB_DATA[2]
3.3V
HPS_USB_DATA[3]
PIN_C4
HPS_USB_DATA[3]
3.3V
HPS_USB_DATA[4]
PIN_C8
HPS_USB_DATA[4]
3.3V
HPS_USB_DATA[5]
PIN_D4
HPS_USB_DATA[5]
3.3V
HPS_USB_DATA[6]
PIN_C7
HPS_USB_DATA[6]
3.3V
HPS_USB_DATA[7]
PIN_F4
HPS_USB_DATA[7]
3.3V
HPS_USB_DIR
PIN_E5
Direction of the Data Bus
3.3V
HPS_USB_NXT
PIN_D5
Throttle the Data
3.3V
HPS_USB_STP
PIN_C5
Stop Data Stream on the Bus
3.3V
4
4. .2 2 G Gi ig ga ab bi it t E Et th he er rn ne et t
The TSoM module supports a Giga Ethernet PHY. The Giga Ethernet uses the HPS RGMII
interface. The following Figure 4-2 describes the connections between Giga Ethernet PHY and the
HPS.
Note: There is only a Giga Ethernet PHY on the TSoM module (without any ethernet physical
interface, eg. J45), for using this function, users need to connect a TSoM Based Board (or other
customized expansion board) to implement the connection between the Giga Ethernet PHY and a
ethernet physical interface.
Figure 4-2 The connections between the Giga Ethernet interface and the HPS
The 1G Ethernet PHY is Micrel's KSZ9031. It uses an RGMII interface running at 125 MHz. The
125 MHz clock is generated by the KSZ9031 Giga Ethernet PHY.
The 1G Ethernet PHY analog signals (TX+/-, RX+/-) are connected to the 260-pin Edge Connector.
Two led signals from the GE PHY are also connected to the 260-pin Edge Connector. The Ethernet
MDC/MDIO signals are connected to the internal PHY and are not available on the 260-pin Edge
Connector.
Table 4-2 lists the pin assignment of Ethernet PHY and HPS.

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Table 4-2 The Giga Ethernet interface Pin Assignments
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_ENET_TX_EN
PIN_A12
GMII and MII transmit enable
3.3V
HPS_ENET_TX_DATA[0]
PIN_A16
MII transmit data[0]
3.3V
HPS_ENET_TX_DATA[1]
PIN_J14
MII transmit data[1]
3.3V
HPS_ENET_TX_DATA[2]
PIN_A15
MII transmit data[2]
3.3V
HPS_ENET_TX_DATA[3]
PIN_D17
MII transmit data[3]
3.3V
HPS_ENET_RX_DV
PIN_J13
GMII and MII receive data valid
3.3V
HPS_ENET_RX_DATA[0]
PIN_A14
GMII and MII receive data[0]
3.3V
HPS_ENET_RX_DATA[1]
PIN_A11
GMII and MII receive data[1]
3.3V
HPS_ENET_RX_DATA[2]
PIN_C15
GMII and MII receive data[2]
3.3V
HPS_ENET_RX_DATA[3]
PIN_A9
GMII and MII receive data[3]
3.3V
HPS_ENET_RX_CLK
PIN_J12
GMII and MII receive clock
3.3V
HPS_ENET_MDIO
PIN_E16
Management Data
3.3V
HPS_ENET_MDC
PIN_A13
Management Data Clock Reference
3.3V
HPS_ENET_INT_N
PIN_B14
Interrupt Open Drain Output
3.3V
HPS_ENET_GTX_CLK
PIN_J15
GMII Transmit Clock
3.3V
4
4. .3 3 e eM MM MC C
The TSoM module supports an 8GByte eMMC device offering 8 parallel data lines at 52 MHz.
The eMMC device can be formatted and/or programmed in u-boot or Linux, like a regular SD card.
In the eMMC boot mode, the HPS boots from the eMMC device located on the module and
configures the FPGA logic from the HPS. The HPS configuration and the FPGA bitstream need to
be stored in a boot image. The following Figure 4-3 describes the eMMC device in the TSoM
module.
Note: As described in the section 3.1, the eMMC on the TSoM module and the external SD Card
interface (on the 260-pin Edge Connector) share the same HPS data bus. If user wants to select
eMMC to boot HPS, please set the SW1 to "On" position to switch the IO to the eMMC.
Figure 4-3 The connections between the eMMC and the HPS

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Table 4-3 lists the pin assignment of eMMC and HPS.
Table 4-3 eMMC Pin Assignments
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_SDMMC_CLK
PIN_B8
eMMC clock
3.3V
HPS_SDMMC_CMD
PIN_D14
eMMC command/response
3.3V
HPS_SDMMC_DATA[0]
PIN_C13
eMMC Data I/O
3.3V
HPS_SDMMC_DATA[1]
PIN_B6
eMMC Data I/O
3.3V
HPS_SDMMC_DATA[2]
PIN_B11
eMMC Data I/O
3.3V
HPS_SDMMC_DATA[3]
PIN_B9
eMMC Data I/O
3.3V
HPS_SDMMC_DATA[4]
PIN_H13
eMMC Data I/O
3.3V
HPS_SDMMC_DATA[5]
PIN_A4
eMMC Data I/O
3.3V
HPS_SDMMC_DATA[6]
PIN_H12
eMMC Data I/O
3.3V
HPS_SDMMC_DATA[7]
PIN_B4
eMMC Data I/O
3.3V
4
4. .4 4 H HP PS S 3 3. .3 3V V G GP PI IO O
The board provides 25 HPS GPIOs (3.3V), which are connected directly to the Cyclone V SoC HPS.
Figure 4-4 shows the signals connected between the HPS and the HPS 3.3V GPIO.
The HPS I/O pins are configured by software executing in the HPS. Software executing on the HPS
accesses control registers in the system manager to assign HPS I/O pins to the available HPS
modules. Each HPS I/O corresponds to different HPS peripheral controllers, users can set these
peripheral controllers through the Qsys built in Quartus software.
25 HPS I/Os of TSoM module are connected to the 260-pin edge connector, then users can connect
the HPS peripherals to the main board according to their own design requirements, such as UART,
I2C, CAN and HPS GPIO interface. Users can choose the HPS peripherals according to Table 4-4,
then connect to the right HPS I/Os on the main board.
Table 4-4 lists the pin assignment of HPS 3.3V GPIO pins to the HPS.
Figure 4-4 Connections between the HPS and the HPS 3.3V GPIO

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Table 4-4 Pin Assignment of HPS 3.3V GPIO
260-Pin
Edge
Connector
Pin Num
Signal Name
FPGAPin
Num
HPS Pin Mux
Select 3
HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
61
HPS_V3P3_GPIO0
PIN_C21
TRACE_CLK
-
-
HPS_GPIO48
63
HPS_V3P3_GPIO1
PIN_A22
TRACE_D0
SPIS0_CLK
UART0_RX
HPS_GPIO49
65
HPS_V3P3_GPIO2
PIN_B21
TRACE_D1
SPIS0_MOSI
UART0_TX
HPS_GPIO50
67
HPS_V3P3_GPIO3
PIN_A21
TRACE_D2
SPIS0_MISO
I2C1_SDA
HPS_GPIO51
69
HPS_V3P3_GPIO4
PIN_K18
TRACE_D3
SPIS0_SS0
I2C1_SCL
HPS_GPIO52
71
HPS_V3P3_GPIO5
PIN_A20
TRACE_D4
SPIS1_CLK
CAN1_RX
HPS_GPIO53
73
HPS_V3P3_GPIO6
PIN_J18
TRACE_D5
SPIS1_MOSI
CAN1_TX
HPS_GPIO54
75
HPS_V3P3_GPIO7
PIN_A19
TRACE_D6
SPIS1_SS0
I2C0_SDA
HPS_GPIO55
77
HPS_V3P3_GPIO8
PIN_C18
TRACE_D7
SPIS1_MISO
I2C0_SCL
HPS_GPIO56
79
HPS_V3P3_GPIO9
PIN_A18
SPIM0_CLK
I2C1_SDA
UART0_CTS
HPS_GPIO57
81
HPS_V3P3_GPIO10
PIN_C17
SPIM0_MOSI
I2C1_SCL
UART0_RTS
HPS_GPIO58
83
HPS_V3P3_GPIO11
PIN_B18
SPIM0_MISO
CAN1_RX
UART1_CTS
HPS_GPIO59
85
HPS_V3P3_GPIO12
PIN_J17
SPIM0_SS0
CAN1_TX
UART1_RTS
HPS_GPIO60
87
HPS_V3P3_GPIO13
PIN_A17
UART0_RX
CAN0_RX
SPIM0_SS1
HPS_GPIO61
89
HPS_V3P3_GPIO14
PIN_H17
UART0_TX
CAN0_TX
SPIM1_SS1
HPS_GPIO62
91
HPS_V3P3_GPIO15
PIN_C19
I2C0_SDA
UART1_RX
SPIM1_CLK
HPS_GPIO63
93
HPS_V3P3_GPIO16
PIN_B16
I2C0_SCL
UART1_TX
SPIM1_MOSI
HPS_GPIO64
95
HPS_V3P3_GPIO17
PIN_B19
CAN0_RX
UART0_RX
SPIM1_MISO
HPS_GPIO65
97
HPS_V3P3_GPIO18
PIN_C16
CAN0_TX
UART0_TX
SPIM1_SS0
HPS_GPIO66
99
HPS_V3P3_GPIO19
PIN_A8
QSPI_IO0
-
USB1_CLK
HPS_GPIO29
101
HPS_V3P3_GPIO20
PIN_H16
QSPI_IO1
-
USB1_STP
HPS_GPIO30
103
HPS_V3P3_GPIO21
PIN_A7
QSPI_IO2
-
USB1_DIR
HPS_GPIO31
105
HPS_V3P3_GPIO22
PIN_J16
QSPI_IO3
-
USB1_NXT
HPS_GPIO32
107
HPS_V3P3_GPIO23
PIN_A6
QSPI_SS0
-
-
HPS_GPIO33
109
HPS_V3P3_GPIO24
PIN_C14
QSPI_CLK
-
-
HPS_GPIO34

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4
4. .5 5 D DD DR R3 3
The board supports 1GB DDR3 SDRAM comprising of two x16 bit DDR3 devices on HPS side.
The signals are connected to the dedicated Hard Memory Controller for HPS I/O banks and the
target speed is 400 MHz. Figure 4-5 shows the connections between the DDR3 and the Cyclone V
SoC HPS. Table 4-5 lists the pin assignment of DDR3 and its pin description, as well as the I/O
standard.
Figure 4-5 Connections between the HPS and the DDR3
Table 4-5 Pin Assignment of DDR3 Memory
Signal Name
FPGA Pin No
Description
I/O Standard
HPS_DDR3_ADDR0
PIN_C28
HPS DDR3 Address[0]
SSTL-15 Class I
HPS_DDR3_ADDR1
PIN_B28
HPS DDR3 Address[1]
SSTL-15 Class I
HPS_DDR3_ADDR2
PIN_E26
HPS DDR3 Address[2]
SSTL-15 Class I
HPS_DDR3_ADDR3
PIN_D26
HPS DDR3 Address[3]
SSTL-15 Class I
HPS_DDR3_ADDR4
PIN_J21
HPS DDR3 Address[4]
SSTL-15 Class I
HPS_DDR3_ADDR5
PIN_J20
HPS DDR3 Address[5]
SSTL-15 Class I
HPS_DDR3_ADDR6
PIN_C26
HPS DDR3 Address[6]
SSTL-15 Class I
HPS_DDR3_ADDR7
PIN_B26
HPS DDR3 Address[7]
SSTL-15 Class I
HPS_DDR3_ADDR8
PIN_F26
HPS DDR3 Address[8]
SSTL-15 Class I
HPS_DDR3_ADDR9
PIN_F25
HPS DDR3 Address[9]
SSTL-15 Class I
HPS_DDR3_ADDR10
PIN_A24
HPS DDR3 Address[10]
SSTL-15 Class I
HPS_DDR3_ADDR11
PIN_B24
HPS DDR3 Address[11]
SSTL-15 Class I
HPS_DDR3_ADDR12
PIN_D24
HPS DDR3 Address[12]
SSTL-15 Class I
HPS_DDR3_ADDR13
PIN_C24
HPS DDR3 Address[13]
SSTL-15 Class I
HPS_DDR3_ADDR14
PIN_G23
HPS DDR3 Address[14]
SSTL-15 Class I
HPS_DDR3_ADDR15
PIN_F24
HPS DDR3 Address[15]
SSTL-15 Class I
HPS_DDR3_BA0
PIN_A27
HPS DDR3 Bank Address[0]
SSTL-15 Class I
HPS_DDR3_BA1
PIN_H25
HPS DDR3 Bank Address[1]
SSTL-15 Class I
HPS_DDR3_BA2
PIN_G25
HPS DDR3 Bank Address[2]
SSTL-15 Class I
HPS_DDR3_CAS_N
PIN_A26
DDR3 Column Address Strobe
SSTL-15 Class I
HPS_DDR3_CKE0
PIN_L28
HPS DDR3 Clock Enable
SSTL-15 Class I

TSoM User Manual
19
www.terasic.com
March 8, 2019
HPS_DDR3_CK_P
PIN_N21
HPS DDR3 Clock
Differential 1.5-V SSTL Class I
HPS_DDR3_CK_N
PIN_N20
HPS DDR3 Clock p
Differential 1.5-V SSTL Class I
HPS_DDR3_CS_N0
PIN_L21
HPS DDR3 Chip Select
SSTL-15 Class I
HPS_DDR3_DM0
PIN_G28
HPS DDR3 Data Mask[0]
SSTL-15 Class I
HPS_DDR3_DM1
PIN_P28
HPS DDR3 Data Mask[1]
SSTL-15 Class I
HPS_DDR3_DM2
PIN_W28
HPS DDR3 Data Mask[2]
SSTL-15 Class I
HPS_DDR3_DM3
PIN_AB28
HPS DDR3 Data Mask[3]
SSTL-15 Class I
HPS_DDR3_DQ0
PIN_J25
HPS DDR3 Data[0]
SSTL-15 Class I
HPS_DDR3_DQ1
PIN_J24
HPS DDR3 Data[1]
SSTL-15 Class I
HPS_DDR3_DQ2
PIN_E28
HPS DDR3 Data[2]
SSTL-15 Class I
HPS_DDR3_DQ3
PIN_D27
HPS DDR3 Data[3]
SSTL-15 Class I
HPS_DDR3_DQ4
PIN_J26
HPS DDR3 Data[4]
SSTL-15 Class I
HPS_DDR3_DQ5
PIN_K26
HPS DDR3 Data[5]
SSTL-15 Class I
HPS_DDR3_DQ6
PIN_G27
HPS DDR3 Data[6]
SSTL-15 Class I
HPS_DDR3_DQ7
PIN_F28
HPS DDR3 Data[7]
SSTL-15 Class I
HPS_DDR3_DQ8
PIN_K25
HPS DDR3 Data[8]
SSTL-15 Class I
HPS_DDR3_DQ9
PIN_L25
HPS DDR3 Data[9]
SSTL-15 Class I
HPS_DDR3_DQ10
PIN_J27
HPS DDR3 Data[10]
SSTL-15 Class I
HPS_DDR3_DQ11
PIN_J28
HPS DDR3 Data[11]
SSTL-15 Class I
HPS_DDR3_DQ12
PIN_M27
HPS DDR3 Data[12]
SSTL-15 Class I
HPS_DDR3_DQ13
PIN_M26
HPS DDR3 Data[13]
SSTL-15 Class I
HPS_DDR3_DQ14
PIN_M28
HPS DDR3 Data[14]
SSTL-15 Class I
HPS_DDR3_DQ15
PIN_N28
HPS DDR3 Data[15]
SSTL-15 Class I
HPS_DDR3_DQ16
PIN_N24
HPS DDR3 Data[16]
SSTL-15 Class I
HPS_DDR3_DQ17
PIN_N25
HPS DDR3 Data[17]
SSTL-15 Class I
HPS_DDR3_DQ18
PIN_T28
HPS DDR3 Data[18]
SSTL-15 Class I
HPS_DDR3_DQ19
PIN_U28
HPS DDR3 Data[19]
SSTL-15 Class I
HPS_DDR3_DQ20
PIN_N26
HPS DDR3 Data[20]
SSTL-15 Class I
HPS_DDR3_DQ21
PIN_N27
HPS DDR3 Data[21]
SSTL-15 Class I
HPS_DDR3_DQ22
PIN_R27
HPS DDR3 Data[22]
SSTL-15 Class I
HPS_DDR3_DQ23
PIN_V27
HPS DDR3 Data[23]
SSTL-15 Class I
HPS_DDR3_DQ24
PIN_R26
HPS DDR3 Data[24]
SSTL-15 Class I
HPS_DDR3_DQ25
PIN_R25
HPS DDR3 Data[25]
SSTL-15 Class I
HPS_DDR3_DQ26
PIN_AA28
HPS DDR3 Data[26]
SSTL-15 Class I
HPS_DDR3_DQ27
PIN_W26
HPS DDR3 Data[27]
SSTL-15 Class I
HPS_DDR3_DQ28
PIN_R24
HPS DDR3 Data[28]
SSTL-15 Class I
HPS_DDR3_DQ29
PIN_T24
HPS DDR3 Data[29]
SSTL-15 Class I
HPS_DDR3_DQ30
PIN_Y27
HPS DDR3 Data[30]
SSTL-15 Class I
HPS_DDR3_DQ31
PIN_AA27
HPS DDR3 Data[31]
SSTL-15 Class I
HPS_DDR3_DQS_N0
PIN_R16
HPS DDR3 Data Strobe n[0]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N1
PIN_R18
HPS DDR3 Data Strobe n[1]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N2
PIN_T18
HPS DDR3 Data Strobe n[2]
Differential 1.5-V SSTL Class I