Terasic DE0-Nano-SoC User manual

DE0-Nano-SoC
My First FPGA
i
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May 18, 2015
CONTENTS
Chapter 1 Introduction ........................................................1
1.1 Design Flow........................................................................................................................... 1
1.2 Before You Begin................................................................................................................... 2
1.3 What You Will Learn ............................................................................................................. 6
Chapter 2 Assign The Device ..................................................7
2.1 Assign The Device ................................................................................................................. 7
Chapter 3 Design Entry .......................................................11
3.1 Add a PLL Megafunction......................................................................................................11
3.2 Add a Multiplexer................................................................................................................ 26
3.3 Assign the Pins..................................................................................................................... 33
3.4 Create a Default TimeQuest SDC File................................................................................. 35
Chapter 4 Compile and Verify Your Design ......................................37
4.1 Compile Your Design........................................................................................................... 37
4.2 Program the FPGA Device................................................................................................... 39
4.3 Verify The Hardware............................................................................................................ 45
Chapter 5 Appendix ..........................................................48
5.1 Headquarter & Branches...................................................................................................... 48

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Chapter 1
Introduction
This tutorial provides comprehensive information that will help you understand how to create a
FPGA design and run it on your DE0-Nano-SoC development board. The following sections
provide a quick overview of the design flow, explain what you need to get started, and describe
what you will learn.
1
1. .1 1 D De es si ig gn n F Fl lo ow w
Figure 1-1shows the FPGAdesign flow block diagram.
The standard FPGA design flow starts with design entry using schematics or a hardware description
language (HDL), such as Verilog HDL or VHDL. In this step, you can create a digital circuit that is
implemented inside the FPGA. The flow then proceeds through compilation, simulation,
programming, and verification in the FPGA hardware.
Figure 1-1 Design Flow
This tutorial guides you through all of the steps except for simulation. Although it is not covered in
this document, simulation is very important to learn, and there are entire applications devoted to
simulating hardware designs. There are two types of simulation, Functional and Timing Functional
simulation allows you to verify that your code is manipulating the inputs and outputs appropriately.
Timing (or post place-and-route) simulation verifies that the design meets timing and functions
appropriately in the device.

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1
1. .2 2 B Be ef fo or re e Y Yo ou u B Be eg gi in n
This tutorial assumes the following prerequisites
■You generally know what a FPGA is. This tutorial does not explain the basic concepts of
programmable logic.
■You are somewhat familiar with digital circuit design and electronic design automation (EDA)
tools.
■You have installed the Altera Quartus II 14.1 software on your computer. If you do not have
the Quartus II software, you can download it from the Altera web site at www.altera.com/download.
■You have a DE0-Nano-SoC Development Board on which you will test your project. Using a
development board helps you to verify whether your design is really working.
■You have gone through the quick start guide and/or the getting started user guide for your
development kit. These documents ensure that you have:
Installed the required software.
Determined that the development board functions properly and is connected to your
computer.
Next step you should installed the USB-BlasterII driver, Plug in the 5-volt adapter to provide power
to the board. Use the USB cable to connect the leftmost USB connector on the DE0-NANO-SoC
board to a USB port on a computer that runs the Quartus II software. Turn on the power switch on
the DE0-NANO-SoC board.
The computer will recognize the new hardware connected to its USB port and Power on the board
as shown in Figure 1-2, but it will be unable to proceed if it does not have the required driver
already installed. The DE0-Nano-SoC board is programmed by using Altera USB-Blaster II
mechanism. If the USB-BlasterII driver is not already installed, the Driver Software Installation in
Figure 1-3 will appear.Click close.

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Figure 1-2 Connection Setup
Figure 1-3 Driver Software Installation
Since the desired driver is not available on the Windows Update Web site, open the Computer
Management and select the Device Manager. This leads to the window in Figure 1-4.

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Figure 1-4 Device Manager
Right click Other devices>Unknown device and select Update Driver Software…This leads to the window in
Figure 1-5.
Figure 1-5 Update Driver Software

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The driver is available within the Quartus II software. Hence, click Browse my computer for device software to
get to Figure 1-6.
.
Figure 1-6 Specify the location of the driver
Now, click Browse to get to the pop-up box in Figure 1-7 Find the desired driver, which is at
location C:\altera\14.1\quartus\drivers\usb-blaster-ii. Click OK and then upon returning to Figure
1-6.click Next.
Figure 1-7 Browse to find the location
The driver will now be installed as indicated in Figure 1-8 Click close and you can start using the
DE0-Nano-SoC board.

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Figure 1-8 The driver is installed
1
1. .3 3 W Wh ha at t Y Yo ou u W Wi il ll l L Le ea ar rn n
In this tutorial you will perform the following tasks:
Create a design that causes LEDs on the development board to blink at a speed that is controlled by
an input key —This design is easy to create and gives you visual feedback that the design works.
Of course, you can use your DE0-Nano-SoC board to run other designs as well. For the LED design,
you will write Verilog HDL code for a simple 32-bit counter, add a phase-locked loop (PLL)
megafunction as the clock source, and add a 2-input multiplexer megafunction. When the design is
running on the board, you can press an input switch to multiplex the counter bits that drive the
output LEDs.
Becoming familiar with Quartus II design tools—This tutorial will not make you an expert, but at
the end, you will understand basic concepts about Quartus II projects, such as entering a design
using a schematic editor and HDL, compiling your design, and downloading it into the FPGA on
your DE0-Nano-SoC development board.
Develop a foundation to learn more about FPGAs —For example, you can create and download
digital signal processing (DSP) functions onto a single chip, or build a multi-processor system, or
create anything else you can imagine all on the same chip. You don’t have to scour data books to
find the perfect logic device or create your own ASIC. All you need is your computer, your
imagination, and an DE0-Nano-SoC FPGA development board.

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Chapter 2
Assign The Device
You begin this tutorial by creating a new Quartus II project. A project is a set of files that maintain
information about your FPGA design. The Quartus II Settings File (.qsf) and Quartus II Project File
(.qpf) files are the primary files in a Quartus II project. To compile a design or make pin
assignments, you must first create a project.
2
2. .1 1 A As ss si ig gn n T Th he e D De ev vi ic ce e
1. In the Quartus II software, select File > New Project Wizard. The Introduction page opens. See
Figure 2-1.
Figure 2-1 New Project Wizard introduction

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2. Click Next.
3. Enter the following information about your project:
a. What is the working directory for this project? Enter a directory in which you will store your
Quartus II project files for this design.
b. For example, C:\My_design\my_first_fpga.
c. File names, project names, and directories in the Quartus II software cannot contain spaces.
d. What is the name of this project? Type my_first_fpga.
e. What is the name of the top-level design entity for this project? Type my_first_fpga. See
Figure 2-2.
Figure 2-2 Project information
f. Click Next.

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g. You will assign a specific FPGA device to the design and make pin assignments. See Figure
2-3.
Figure 2-3 Specify the Device Example
h. Click Finish.
4. When prompted, choose Yes to create the my_first_fpga project directory. You just created
your first Quartus II FPGA project. See Figure 2-4.

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Figure 2-4 my_first_fpga project

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Chapter 3
Design Entry
3
3. .1 1 A Ad dd d a a P PL LL L M Me eg ga af fu un nc ct ti io on n
This section describes How to Add a PLL Megafunction
In the design entry step you create a schematic or Block Design File (.bdf) that is the top-level
design. You will add library of parameterized modules (LPM) functions and use Verilog HDL code
to add a logic block. When creating your own designs, you can choose any of these methods or a
combination of them.
1. Choose File > New > Block Diagram/Schematic File (see Figure 3-1 to create a new file,
Block1.bdf, which you will save as the top-level design.
Figure 3-1 New BDF
2. Click OK.

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3. Choose File > Save As and enter the following information.
File name: my_first_fpga
Save as type: Block Diagram/Schematic File (*.bdf)
4. Click Save. The new design file appears in the Block Editor (see Figure 3-2).
Figure 3-2 Bank BDF
5. Add HDL code to the blank block diagram by choosing File > New > Verilog HDL File.
6. Click OK to create a new file Verilog1.v, which you will save as simple_counter.v.
7. Select File > Save As and enter the following information (see Figure 3-3).
File name: simple_counter.v
Save as type: Verilog HDL File (*.v, *.vlg, *.verilog)

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Figure 3-3 Saving the Verilog HDL file
The resulting empty file is ready for you to enter the Verilog HDL code.
8. Type the following Verilog HDL code into the blank simple_counter.v file (see Figure 3-4 The
Verilog File of simple_counter.v).
//It has a single clock input and a 32-bit output port
module simple_counter (
CLOCK_50,
counter_out
);
input CLOCK_50 ;
output [31:0] counter_out;
reg [31:0] counter_out;
always @ (posedge CLOCK_50) // on positive clock edge

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begin
counter_out <= #1 counter_out + 1;// increment counter
end
endmodule // end of module counter
Figure 3-4 The Verilog File of simple_counter.v
9. Save the file by choosing File > Save, pressing Ctrl + s, or by clicking the floppy disk icon.
10. Choose File > Create/Update > Create Symbol Files for Current File to convert the
simple_counter.v file to a Symbol File (.sym).You use this Symbol File to add the HDL code to
your BDF schematic.
The Quartus II software creates a Symbol File and displays a message (see Figure 3-5).

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Figure 3-5 Create Symbol File was Successful
11. Click OK.
12. To add the simple_counter.v symbol to the top-level design, click the my_first_fpga.bdf tab.
13. Insert Symbol or click Add Symbol on the toolbar.
14. Double-click the Project directory to expand it.
15. Select the newly created simple_counter symbol by clicking it’s icon.
You can also double-click in a blank area of the BDF to open the Symbol dialog box (see Figure
3-6).
Figure 3-6 Adding the Symbol to the BDF
16. Click OK.
17. Move the cursor to the BDF grid; the symbol image moves with the cursor. Click to place the
simple_counter symbol onto the BDF. You can move the block after placing it by simply clicking

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and dragging it to where you want it and releasing the mouse button to place it. See Figure 3-7.
Figure 3-7 Placing the simple_counter symbol
18. Press the Esc key or click an empty place on the schematic grid to cancel placing further
instances of this symbol.
19. Save your project regularly.
Using Quartus Add a PLL Megafunction.
Megafunctions, such as the ones available in the LPM, are pre-designed modules that you can use in
FPGA designs. These Altera-provided megafunctions are optimized for speed, area, and device
family. You can increase efficiency by using a megafunction instead of writing the function yourself.
Altera also provides more complex functions, called MegaCore functions, which you can evaluate
for free but require a license file for use in production designs. This tutorial design uses a PLL clock
source to drive a simple counter. A PLL uses the on-board oscillator (DE0-Nano-SoC Board is 50
MHz) to create a constant clock frequency as the input to the counter. To create the clock source,
you will add a pre-built LPM megafunction named Altera PLL.
1. Choose Edit > Insert Symbol or click Add Symbol on the toolbar---
2. Tools > Click IP Catalog (see Figure 3-8).

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Figure 3-8 Tools Icon
3. Selecting IP Catalog.
4. Selection Altera PLL in the Library/Clocks/PLL , click "+Add" bar. See Figure 3-9
a. Under IP variation file type, Choose Verilog HDL.
b. Under IP variation file, Type pll.v at the end of the already create directory name.
c. Click OK.

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Figure 3-9 IP Catalog Selections
5. In the Altera PLL windows, make the following selections (see Figure 3-10).
a. The device speed grade choose 6 for DE0-Nano-SoC.
b. Set the frequency of the refclk input 50 MHz.