Texas Instruments TPA3200D1 User manual

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FEATURES DESCRIPTION
LRCK
1.0 mF
Control
Inputs
DGND
Gain Select
+5V
Channel Select
{
BCK
GAIN0
VCOM
DATA
FORMAT
SCLK
GAIN1
LR_SEL
VDD
SHUTDOWN
VCLAMP
PGND
Shutdown Control
+18V
MUTE
DEMP
ZERO
AVCC
10 mF
{
Zero Input Flag
FLT1
FLT2
22 nF
COSC
AGND
ROSC
VREF
BYPASS
220 pF
1mF
1mF
120 kW
0.22 mF
BSN
51 W
OUTN
0.22 mF
BSP
OUTP
51 W
PVCC
Digital Audio
Processor
TPA3200D1
I2S or 16-bit RJ
TAS3103
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
20-W MONO DIGITAL INPUT AUDIO AMPLIFIER
•Digital Interface
The TPA3200D1 is a 20-W (per channel) efficient,digital audio power amplifier for driving a bridged-tied– 24-bit Resolution
speaker. The TPA3200D1 can drive a speaker with– Supports I
2
S and 16-Bit Word
an impedance as low as 4 Ω. The high efficiency ofRight-Justified Digital Input Formats
the TPA3200D1 (85%) eliminates the need for an– Multiple Sampling Frequencies:
external heat sink.5 kHz – 200 kHz
The digital input accepts 16-24 bit data in I
2
S format– 8x Oversampling Digital Filter
or 16-bit word right-justified. A digital filter performs– Soft Mute
an 8x interpolation function. Other features includesoft mute, a zero input detect output flag for power•Power Amplifier
conscious designs, and power saving shutdown– 20-W into an 8- ΩLoad from an 18-V Supply
mode.– Efficient Operation Eliminates Need for HeatSinks
– Three Selectable, Fixed Gain Settings– Thermal and Short-Circuit Protection
Simplified Application Circuit
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICET
A
44-PIN (DCP)
(1)
–40 °C to 85 °C TPA3200D1DCP
(1) The DCP package is available taped and reeled. To order a tapedand reeled part, add the suffix R to the part number (e.g.,TPA3200D1DCPR).
over operating free-air temperature range (unless otherwise noted)
(1)
TPA3200D1 UNIT
Supply voltage, VCC, PVCC –0.3 to 21 VV
SS
Supply voltage, VDD –0.3 to 6.5 VR
L
Load Impedance ≥3.6 ΩSHUTDOWN – 0.3 to V
CC
+ 0.3 VVi GAIN0, GAIN1, BCK, SCLK, DATA, LRCK, LR_SEL
–0.3 to V
DD
+ 0.3 VFORMAT, MUTE, DEMPContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range –25 to 85 °CT
J
Operating junction temperature range –25 to 150 °CT
stg
Storage temperature range –65 to 150 °CLead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operations of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °C(1/ θ
JA
)
44-pin DCP 4.89 W 39.1 mW/ °C
(1)
3.13 W 2.54 W
(1) Based on a JEDEC high-K PCB with the PowerPAD™ soldered to a thermal land on the printed-circuit board. See the PowerPADThermally Enhanced Package technical brief, literature number SLMA0002. The PowerPAD must be soldered to the PCB.
2

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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
PARAMETER PIN NAME MIN MAX UNIT
PVCC, VCC 8 18V
SS
Supply voltage
VDD 4.5 5.5SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,V
IH
High-level input voltage 2LRCK, FORMAT, MUTE, DEMP
VSHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,V
IL
Low-level input voltage 0.8LRCK, FORMAT, MUTE, DEMPV
IH
High-level input voltage LR_SEL VDD x 0.7V
IL
Low-level input voltage LR_SEL VDD x 0.3SHUTDOWN: V
I
= VCC, VCC = 12 V 1GAIN0, GAIN1, LR_SEL: V
I
= VDD, VDD = 5 V 1I
IH
High-level input current
SCLK, BCK, DATA, LRCK: V
I
= VDD, VDD = 5 V 10FORMAT, MUTE, DEMP: V
I
= VDD, VDD = 5 V 100
µASHUTDOWN: V
I
= 0 V, VCC = 12 V 1GAIN0, GAIN1, LR_SEL: V
I
= 0 V, VDD = 5 V 1I
IL
Low-level input current
BCK, SCLK, DATA, LRCK, FORMAT, MUTE, DEMP:
10V
I
= 0 V, VDD = 5 VV
OH
High-level output voltage I
OH
= –1 mA, ZERO 2.4
VV
OL
Low-level output voltage I
OL
= 1 mA, ZERO 0.4f
OSC
Oscillator frequency 200 300 kHz
All specifications at T
A
= 25 °C, V
DD
= 5 V, f
S
= 44.1 kHz, system clock = 384 f
S
and 24-bit data, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY REQUIREMENTS
(1)
f
S
= 44.1 kHz 26 31I
DD
Supply current f
S
= 96 kHz 25 mAf
S
= 192 kHz 30
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS
Pass band ±0.04 dB 0.454 f
s
Stop band 0.546 f
s
Pass-band ripple ±0.04 dBStop-band attenuation Stop band = 0.546 f
S
–50 dB
ANALOG FILTER PERFORMANCE
At 20 kHz –0.03Frequency response dBAt 44 kHz –0.20
SAMPLING FREQUENCY
fs Sampling frequency 5 200 KHz
DYNAMIC PERFORMANCE
Channel separation f
S
= 44.1 KHz, 96 KHz, 192 KHz 100 dB
(1) Conditions in 192-kHz operation are system clock = 128 f
S
and oversampling rate = 64 f
S
of register 18.
3

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FORMAT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
All specifications at T
A
= 25 °C, V
DD
= 5 V, f
S
= 44.1 kHz, system clock = 384 f
S
and 24-bit data, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
Data
Audio-data interface format Audio I
2
S, standardAudio-data bit length Audio 16–24-bit (I
2
S), 16-bit (Right-justified)Audio data format MSB first, 2s complementSystem clock frequency 128 f
S,
192 f
S
, 256 f
S
, 384 f
S
,512 f
S
, 768 f
S
, 1152 f
S
at T
A
= 25 °C, PV
CC
= V
CC
= 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OS
| Output offset voltage (measured differentially) MUTE = 2 V A
V
= 12 dB 100 mVPSRR Power supply rejection ratio PV
CC
= 11.5 V to 12.5 V –73 dBV
REF
5 V regulator voltage I
L
= 10 mA, V
CC
= 8 V – 18 V 4.55 4.9 5.45 VSHUTDOWN = 2.0 V, No load 8 15 mAI
CC
Supply current
SHUTDOWN = V
CC
, V
CC
= 18 V, PO = 20 W, 1.3
AR
L
= 8 ΩI
CC(SD)
Supply current shutdown mode SHUTDOWN = 0.8 V 1 2 µAOutput transistor on resistance (high side andr
DS(on)
I
O
= 0.5 A, T
J
= 25 °C 0.5 0.6 0.7 Ωlow side)
GAIN1 = 0.8 V, GAIN0 = 0.8 V 10.9 12 13.1G Gain GAIN1 = 0.8 V, GAIN0 = 2 V 17.1 18 18.6 dBGAIN1 = 2 V, GAIN0 = 0.8 V 22.9 23.6 24.4
PV
CC
= V
CC
= 12 V, T
A
= 25 °C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Continuous output power at 10% THD+N f = 1 kHz, R
L
= 4 Ω12.8f = 1 kHz, R
L
= 8 Ω9P
O
WContinuous output power at 1% THD+N f = 1 kHz, R
L
= 4 Ω10.3f = 1 kHz, R
L
= 8 Ω7.5THD+N Total harmonic distortion plus noise P
O
= 10 W, R
L
= 4 Ω f = 20 Hz to 20 kHz 0.2%B
OM
Maximum output power bandwidth THD = 1% 20 kHzk
SVR
Supply ripple rejection ratio f = 1 kHz, C
(BYPASS)
= 1 µF –60
dBSNR Signal-to-noise ratio P
O
= 10 W, R
L
= 4 Ω95C
(BYPASS)
= 1 µF, f = 20 Hz to 22 kHz, 150 µV(rms)V
n
Noise output voltage
A-weighted filter Gain = 12 dB
–76.5 dBV
4

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Audio
Serial
Port
Serial
Control
Port
4x/8x
Oversampling
Digital
Filter
and
Function
Control Multi-Level
Delta-Sigma
Modulator
Audio
Serial
Port
System Clock
BCK
LRCK
DATA
FORMAT
MUTE
DEMP
SCLK
DAC and
2:1 Mux
LR_SEL
VCOM
Gain
Adjust
−
++
−
Gain
Adjust
FLT1
FLT2 _
+
_
+
_
+
_
+
Deglitch
Logic
Deglitch
Logic
Gate
Drive
Gate
Drive
Clamp
Reference
Short-Circuit
Detect
Start-Up
Protection
Logic
Thermal VCC OK
SD
Gain
SHUTDOWN
GAIN0
GAIN1 2Biases
and
References Ramp
Generator
VREF AGND AVCC
VREF AVCC
Power Supply
Zero Detect
COSC
ROSC
BYPASS
ZERO
VDD
DGND
VCLAMP
BSN
PVCC
OUTN
PGND
BSP
OUTP
PGND
PVCC
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Functional Block Diagram
5

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1
BCK SCLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
LRCK
DATA
DGND
VDD
LR_SEL
VDD
DGND
VCOM
GAIN0
GAIN1
SHUTDOWN
PGND
VCLAMP
NC
BSN
PVCC
OUTN
OUTN
PGND
PGND
FORMAT
MUTE
DEMP
DGND
ZERO
DGND
FLT1
FLT2
VCC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PVCC
OUTP
OUTP
PGND
PGND
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
DCP
(TOP VIEW)
6

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TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Terminal Functions
TERMINAL
I/O DESCRIPTIONNO. NAME
1 BCK I Bit clock input for audio data3 DATA I Audio data input4 LRCK I Left and right channel audio data latch enable inputSelect left-channel or right-channel data7 LR_SEL I HIGH: Left channel activeLOW: Right channel active11 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to 5 V.12 GAIN1 I Gain select most significant bit. TTL logic levels with compliance to 5 V.Shutdown signal for IC (low = shutdown, high = operational).13 SHUTDOWN I
TTL logic levels with compliance to 18 V.5, 9, 38, 40 DGND - Digital ground6, 8 VDD - Digital power supply (4.5 V – 5.5 V)15 VCLAMP - Internally generated voltage supply for bootstrap capacitor17 BSN I/O Bootstrap I/O, negative high-side FET28 BSP I/O Bootstrap I/O, positive high-side FET2, 16 NC - No internal connection31 ROSC I/O I/O for current setting resistor for ramp generator32 COSC I/O I/O for charge/discharging currents onto capacitor for ramp generator creation33 BYPASS O Midrail analog reference voltage34 VREF O Analog 5-V regulated output. Not to be used for powering external circuitry.35 VCC - High-voltage analog power supply (8 V to 18 V).19, 20 OUTN O Class-D 1/2-H-bridge negative outputZero flag outputHIGH: No input present39 ZERO O
LOW: Data present at inputThis can be used to shutdown the device when no data is present at input.De-emphasis control.41 DEMP I HIGH: 44.1 kHz De-emphasis ONLOW: 44.1 kHz De-emphasis OFFSoft mute control42 MUTE I HIGH: Mute ONLOW: Mute OFFAudio data format select43 FORMAT I HIGH: 16-bit right justifiedLOW: 16- to 24-bit, I
2
S format44 SCLK I System clock input18, 27 PVCC - Power supply for H-bridge (8 V to 18 V)25, 26 OUTP O Class-D 1/2-H-bridge positive output29, 30 AGND - Analog ground14, 21, 22, 23, 24 PGND - Power ground for H-bridge10 VCOM - Midrail digital reference voltage36 FLT2 I/O
Noise-filter terminals. Connect capacitor across pins 36 and 3737 FLT1 I/O
Connect to AGND and PGND - should be the center point for both grounds.Thermal Pad
Internal esistive connection to AGND.
7

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TYPICAL CHARACTERISTICS
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 10100m 200m 1 2
Total Hormonic Distortion Plus Noise − %
PO− Output Power − W
20 Hz
1 kHz
10 kHz
VCC = 12 V
RL= 8 
Gain = 18 dB
fS= 48 kHz
24−bit, I2S format
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 10100m 200m 1 2
Total Hormonic Distortion Plus Noise − %
PO− Output Power − W
20 Hz
1 kHz
10 kHz
VCC = 12 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 20100m 200m 110
THD+N - T
otal Harmonic Distortion + Noise - %
PO- Output Power - W
10 kHz
1 kHz
R = 4 ,
LÙ
Gain = 18 dB,
f = 48 kHz,
s
24-bit, I S format
2
V = 12 V
CC
20 Hz
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 20 100m 200m 110
2
Total Hormonic Distortion Plus Noise − %
PO− Output Power − W
20 Hz
1 kHz
10 kHz
VCC = 18 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noisevs vsOutput Power Output Power
Figure 1. Figure 2.
Harmonic Distortion Plus Noise Total Harmonic Distortionvs vsOutput Power Power
Figure 3. Figure 4.
8

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0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
PO= 1 W
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
VCC = 12 V
RL= 8 
Gain = 18 dB
fS= 48 kHz
24−bit, I2S format
PO= 5 W
PO= 500 mW
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
PO= 500 mW
PO= 1 W
PO= 5 W
VCC = 12 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
PO= 500 mW
PO= 1 W
PO= 5 W
VCC = 18 V
RL= 8 
Gain = 18 dB
fS= 48 kHz
24−bit, I2S format
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
PO= 500 mW
PO= 1 W
PO= 5 W
VCC = 18 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noisevs vsFrequency Frequency
Figure 5. Figure 6.
Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noisevs vsFrequency Frequency
Figure 7. Figure 8.
9

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0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k50 100 200 500 1k 2k 5k 10k
THD + N - Total Harmonic Distortion + Noise - %
f - Frequency - Hz
V = 12 V
CC
R = 4
LÙ
Gain = 18 dB
f = 48 kHz
S
24-Bit, I S format
2
P = 2 W
o
P = 200 mW
o
P = 7.5 W
o
−70
−60
−50
−40
−30
−20
−10
0
20 100 1 k 10 k 20 k
f − Frequency − Hz
PSRR − Power Supply Rejecyion Ratio − dB
VCC = 12 V
V(RIPPLE) = 200 mVPP
RL= 8 
Gain = 18 dB
0
10
20
30
40
50
60
70
80
90
0 2 4 6 8 10 12 14
PO− Output Power − W
4 Ω
8 Ω
Efficiency − %
VCC = 12 V
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
TA= 25°C,
10% THD Maximum
ZL− Load Impedance − Ω
− Output Power − WPO
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Total Harmonic Distortion Power Supply Voltage Rejection Ratiovs vsFrequency Frequency
Figure 9. Figure 10.
Efficiency Output Powervs vsOutput Power Load Impedance
Figure 11. Figure 12.
10

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5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
− Maximum Output Power − WPO
ZL− Load Impedance − Ω
TA= 45°C
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
− Maximum Output Power − WPO
ZL− Load Impedance − Ω
TA= 60°C
f – Frequency – kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14 16 18 20
De-emphasis Level – dB
fS= 44.1 kHz
f – Frequency – kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14 16 18 20
De-emphasis Error – dB
fS= 44.1 kHz
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Maximum Output Power Maximum Output Powervs vsLoad Impedance Load Impedance
Figure 13. Figure 14.
De-emphasis Level De-emphasis Errorvs vsFrequency Frequency
Figure 15. Figure 16.
11

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APPLICATION INFORMATION
1mF
1mF
220 pF
VCC
PGND and DGND
connected at
power supply
Shutdown Control
{
VDD
GAIN0
VCOM
GAIN1
VCC
120 kW
NC
DGND
VDD
LRCK
DGND
BCK
DATA
LR_SEL
VDD
SHUTDOWN
PGND
PGND
VCLAMP
BSN
OUTN
OUTN
PGND
PVCC
NC
0.1 mF
1mF
51 W0.22 mF
OUTN
Ferrite
Bead
1 nF
OUTP
Ferrite
Bead
Ferrite
Bead
1 nF
0.22 mF
22 mF
FORMAT
SCLK
COSC
PGND
AGND
BSP
OUTP
OUTP
ROSC
PVCC
AGND
MUTE
DGND
DEMP
DGND
FLT1
ZERO
FLT2
VCC
VREF
BYPASS
PGND
10 mF
10 Fm
22 nF
Gain Control
{
I2S/RJ Clocks
& Data
51 W
}Control
Inputs
Zero Flag Output
PGND DGND
1mF1mF
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Figure 17. Typical Application Circuit
12

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SYSTEM CLOCK INPUT
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2.0 V
0.8 V
H
L
AUDIO SERIAL INTERFACE
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
APPLICATION INFORMATION (continued)
The TPA3200D1 requires a system clock for operating the digital interpolation filters and multilevel delta-sigmamodulators. The system clock is applied at the SCLK input (pin 44). Table 1 shows examples of system clockfrequencies for common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important touse a clock source with low phase-jitter and noise. TI’s PLL170x family of multiclock generators is an excellentchoice for providing the TPA3200D1 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLE SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)FREQUENCY
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
1152f
S
8 kHz 1.0240 1.5360 2.0480 3.0720 4.0960 6.1440 9.216016 kHz 2.0480 3.0720 4.0960 6.1440 8.1920 12.2880 18.432032 kHz 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 36.864044.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 (1)48 kHz 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 (1)88.2 kHz 11.2896 16.9344 22.5792 33.8688 45.1584 (1) (1)96 kHz 12.2880 18.4320 24.5760 36.8640 49.1520 (1) (1)192 kHz 24.5760 36.8640 49.1520 See
(1)
(1) (1) (1)
(1) This system clock rate is not supported for the given sampling frequency.
Figure 18. System Clock Input Timing
PARAMETERS SYMBOL MIN TYP MAX UNITS
System clock pulse duration, high t
(SCKH)
7System clock pulse duration, low t
(SCKL)
nsSystem clock pulse cycle time t
(SCY)
7 See
(1)
(1) 1/128 f
S
, 1/256 f
S
, 1/384 f
S
, 1/512 f
S
, 1/768 f
S
, or 1/1152 f
S
The audio serial interface for the TPA3200D1 consists of a 3-wire synchronous serial port. It includes LRCK (pin4), BCK (pin 1), and DATA (pin 3). BCK is the serial audio bit clock, and it is used to clock the serial data presenton DATA into the serial shift register of the audio interface. Serial data is clocked into the TPA3200D1 on therising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the internalregisters of the serial audio interface.
Both LRCK and BCK should be synchronous to the system clock. Ideally, it is recommended that LRCK and BCKbe derived from the system clock input, SCK. LRCK is operated at the sampling frequency, f
S
. BCK can beoperated at 32, 48, or 64 times the sampling frequency for standard and left-justified formats. BCK can beoperated at 48 or 64 times the sampling frequency for the I
2
S format.
Internal operation of the TPA3200D1 is synchronized with LRCK. Accordingly, internal operation is held when thesampling rate clock of LRCK is changed or when SCK and/or BCK is interrupted for a 3-bit clock cycle or longer.If SCK, BCK, and LRCK are provided continuously after this held condition, the internal operation isre-synchronized automatically in a period of less than 3/f
S
. External resetting is not required.
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AUDIO DATA FORMATS AND TIMING
DATA
t(BCH)
1.4 V
BCK
LRCK
t(BCL) t(LB)
t(BCY)
t(DS) t(DH)
1.4 V
1.4 V
t(BL)
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
The TPA3200D1 supports I
2
S and 16-bit-word right-justified. The data formats are shown in Figure 20 . Dataformats are selected using the FORMAT pin on the TPA3200D1. All formats require binary 2s-complement,MSB-first audio data. Figure 19 shows a detailed timing diagram for the serial audio interface.
Figure 19. Audio Interface Timing
PARAMETERS SYMBOL MIN TYP MAX UNITS
BCK pulse cycle time t
(BCY)
1/(32 f
S
), 1/(48 f
S
), 1/(64 f
S
)
(1)
BCK high-level time t
(BCH)
35BCK low-level time t
(BCL)
35BCK rising edge to LRCK edge t
(BL)
10 nsLRCK falling edge to BCK rising edge t
(LB)
10DATA setup time t
(DS)
10DATA hold time t
(DH)
10
(1) f
S
is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.).
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LRCK
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
(= 32 fS, 48 fS, or 64 fS)
(1) 16-Bit-Word Right Justified
1/fS
(= 48 fSor 64 fS)
MSB LSB
16-Bit Right-Justified, BCK = 32 fS
16-Bit Right-Justified, BCK = 48 fSor 64 fS
MSB LSB
L-Channel R-Channel
BCK
DATA 14 15 16 1 2 3 14 15 16
14 15 16 1 2 3 14 15 16DATA
MSB LSB
MSB LSB
1 2 3 14 15 16
1 2 3 14 15 16
L-Channel R-ChannelLRCK
BCK
DATA 1 2 3 1 2
MSB
N–2 N N–1
LSB
123
MSB
N–2 N N–1
LSB
ZERO FLAG
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Figure 20. Audio Data Input Formats
ZERO (pin 39) is the L-channel and R-channel common zero flag pin. If the data for L-channel and R-channelremains at a 0 level for 1024 sampling periods (or LRCK clock periods), the ZERO flag output is set to a logic 1state.
The ZERO-pin output can be inverted using a standard logic gate or transistor, and connected to theSHUTDOWN terminal (pin 13). This places the TPA3200D1 into a low-current state, conserving power, anddisables the switching outputs.
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REGISTER CONTROL
OVERSAMPLING RATE CONTROL
VCOM OUTPUT
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
The digital functions of the TPA3200D1 are controlled by 4 terminals. Table 2 shows selectable data formats,Table 3 shows de-emphasis control, Table 4 shows mute control, and Table 5 shows channel-output select.
Table 2. Data Format Select
FMT (PIN 43) DATA FORMAT
LOW 16- to 24-bit, I
2
S formatHIGH 16-bit right-justified
Table 3. De-Emphasis Control
DEMP (PIN 41 ) DE-EMPHASIS FUNCTION
LOW 44.1 kHz de-emphasis OFFHIGH 44.1 kHz de-emphasis ON
Table 4. Mute Control
MUTE (PIN 42 ) MUTE
LOW Mute OFFHIGH Mute ON
Table 5. Channel Output Select
LR_SEL (PIN 7 ) ACTIVE CHANNEL
(1)
LOW RightHIGH Left
(1) A digital data stream consists of two channels of data. In an I
2
S orright-justified data stream, the left-channel data precedes theright-channel data (See Figure 20 ). The LR_SEL input selects thechannel to send to the mono output.
The TPA3200D1 automatically controls the oversampling rate of the delta-sigma D/A converters with the systemclock rate. The oversampling rate is set to 64× oversampling with every system clock and sampling frequency.
One unbuffered common-mode voltage output pin, VCOM (pin 10) is brought out for decoupling purposes. Thispin is nominally biased to a dc voltage level equal to 0.5 × V
DD
. This pin cannot be used to bias external circuits.
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CLASS-D OPERATION
Traditional Class-D Modulation Scheme
0 V
−12 V
+12 V
Current
OUTP
Differential Voltage
Across Load
OUTN
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
This section focuses on the class-D operation of the TPA3200D1.
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential outputwhere each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,the differential pre-filtered output varies between positive and negative V
CC
, where filtered 50% duty cycle yields0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown inFigure 31. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,causing high loss, thus causing a high supply current.
Figure 21. Traditional Class-D Modulation Scheme’s Output Voltage and Current Waveforms Into anInductive Load With No Input
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TPA3200D1 Modulation Scheme
0 V
−12 V
+12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
0 V
−12 V
+12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
Output > 0 V
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
The TPA3200D1 uses a modulation scheme that still has each output switching from ground to V
CC
. However,OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50%and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN isgreater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of theswitching period, greatly reducing the switching current, which reduces any I
2
R losses in the load. (SeeFigure 22 .)
Figure 22. The TPA3200D1 Output Voltage and Current Waveforms Into an Inductive Load
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Maximum Allowable Output Power (Safe Operating Area)
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
TA= 25°C,
10% THD Maximum
ZL− Load Impedance − Ω
− Output Power − W
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
PO
Driving The Output Into Clipping
PO(10% THD) PO(1% THD) 1.25
(1)
Output Filter Considerations
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
The TPA3200D1 can drive load impedances as low as 3.6 Ωfrom power supply voltages ranging from 8 V to 18V. To prevent device failure, however, the output power of the TPA3200D1 must be limited. Figure 23 shows themaximum allowable output power versus load impedance for three power supply voltages at an ambienttemperature of 25°C.
Figure 23. Output Power
The output of the TPA3200D1 may be driven into clipping to attain a higher output power than is possible with nodistortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power intothe load may be calculated with Equation 1 .
For example, consider an application in which the TPA3200D1 drives an 8- Ωspeaker from an 18-V powersupply. The maximum output power with no distortion (less than 1% THD) is 16 W, which corresponds to amaximum peak output voltage of 16 V. For the same output voltage level driven into clipping (10% THD), theoutput power is increased to 20 W.
A ferrite bead filter (shown in Figure 24 ) should be used in order to pass FCC and/or CE radiated emissionsspecifications and if a frequency sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reducesEMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selectinga ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.
Use an additional LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are longwires (greater than 11 inches) from the amplifier to the speaker, as shown in Figure 25 and Figure 26 .
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1 nF
Ferrite
Chip Bead
OUTP
OUTN
Ferrite
Chip Bead
1 nF
4 or GreaterW
0.22 µF
15 µH
15 µH
OUTP
OUTN
4 Ω
Ferrite
Chip Bead
Ferrite
Chip Bead
1 nF
1 nF
0.22 µF
1 µF
0.1 µF
0.1 µF
33 µH
33 µH
OUTP
OUTN
8 Ω
Ferrite
Chip Bead
Ferrite
Chip Bead
1 nF
1 nF
0.47 µF
SHORT-CIRCUIT PROTECTION
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Figure 24. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
Figure 25. Typical LC Output Filter for 4- ΩSpeaker, Cutoff Frequency of 41 kHz
Figure 26. Typical LC Output Filter for 8- ΩSpeaker, Cutoff Frequency of 41 kHz
The TPA3200D1 has short circuit protection circuitry on the outputs that prevents damage to the device duringoutput-to-output shorts, output-to-GND shorts, and output-to-V
CC
shorts. When a short-circuit is detected on theoutputs, the part immediately disables the output drive and enters into shutdown mode. This is a latched faultand must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high statefor normal operation. This will clear the short-circuit flag and allow for normal operation if the short was removed.If the short was not removed, the protection circuitry will again activate.
Two Schottky diodes are required to provide short-circuit protection. The diodes should be placed as close to theTPA3200D1 as possible, with the anodes connected to PGND and the cathodes connected to OUTP and OUTNas shown in the application circuit schematic. The diodes should have a forward voltage rating of 0.5 V at aminimum of 1 A output current and a dc blocking voltage rating of at least 30 V. The diodes must also be rated tooperate at a junction temperature of 150°C.
If short-circuit protection is not required, the Schottky diodes may be omitted.
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