Texas Instruments TPA3200D1 User manual

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FEATURES DESCRIPTION
LRCK
1.0 mF
Control
Inputs
DGND
Gain Select
+5V
Channel Select
{
BCK
GAIN0
VCOM
DATA
FORMAT
SCLK
GAIN1
LR_SEL
VDD
SHUTDOWN
VCLAMP
PGND
Shutdown Control
+18V
MUTE
DEMP
ZERO
AVCC
10 mF
{
Zero Input Flag
FLT1
FLT2
22 nF
COSC
AGND
ROSC
VREF
BYPASS
220 pF
1mF
1mF
120 kW
0.22 mF
BSN
51 W
OUTN
0.22 mF
BSP
OUTP
51 W
PVCC
Digital Audio
Processor
TPA3200D1
I2S or 16-bit RJ
TAS3103
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
20-W MONO DIGITAL INPUT AUDIO AMPLIFIER
•Digital Interface
The TPA3200D1 is a 20-W (per channel) efficient,digital audio power amplifier for driving a bridged-tied– 24-bit Resolution
speaker. The TPA3200D1 can drive a speaker with– Supports I
2
S and 16-Bit Word
an impedance as low as 4 Ω. The high efficiency ofRight-Justified Digital Input Formats
the TPA3200D1 (85%) eliminates the need for an– Multiple Sampling Frequencies:
external heat sink.5 kHz – 200 kHz
The digital input accepts 16-24 bit data in I
2
S format– 8x Oversampling Digital Filter
or 16-bit word right-justified. A digital filter performs– Soft Mute
an 8x interpolation function. Other features includesoft mute, a zero input detect output flag for power•Power Amplifier
conscious designs, and power saving shutdown– 20-W into an 8- ΩLoad from an 18-V Supply
mode.– Efficient Operation Eliminates Need for HeatSinks
– Three Selectable, Fixed Gain Settings– Thermal and Short-Circuit Protection
Simplified Application Circuit
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICET
A
44-PIN (DCP)
(1)
–40 °C to 85 °C TPA3200D1DCP
(1) The DCP package is available taped and reeled. To order a tapedand reeled part, add the suffix R to the part number (e.g.,TPA3200D1DCPR).
over operating free-air temperature range (unless otherwise noted)
(1)
TPA3200D1 UNIT
Supply voltage, VCC, PVCC –0.3 to 21 VV
SS
Supply voltage, VDD –0.3 to 6.5 VR
L
Load Impedance ≥3.6 ΩSHUTDOWN – 0.3 to V
CC
+ 0.3 VVi GAIN0, GAIN1, BCK, SCLK, DATA, LRCK, LR_SEL
–0.3 to V
DD
+ 0.3 VFORMAT, MUTE, DEMPContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range –25 to 85 °CT
J
Operating junction temperature range –25 to 150 °CT
stg
Storage temperature range –65 to 150 °CLead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operations of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °C(1/ θ
JA
)
44-pin DCP 4.89 W 39.1 mW/ °C
(1)
3.13 W 2.54 W
(1) Based on a JEDEC high-K PCB with the PowerPAD™ soldered to a thermal land on the printed-circuit board. See the PowerPADThermally Enhanced Package technical brief, literature number SLMA0002. The PowerPAD must be soldered to the PCB.
2

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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
PARAMETER PIN NAME MIN MAX UNIT
PVCC, VCC 8 18V
SS
Supply voltage
VDD 4.5 5.5SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,V
IH
High-level input voltage 2LRCK, FORMAT, MUTE, DEMP
VSHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,V
IL
Low-level input voltage 0.8LRCK, FORMAT, MUTE, DEMPV
IH
High-level input voltage LR_SEL VDD x 0.7V
IL
Low-level input voltage LR_SEL VDD x 0.3SHUTDOWN: V
I
= VCC, VCC = 12 V 1GAIN0, GAIN1, LR_SEL: V
I
= VDD, VDD = 5 V 1I
IH
High-level input current
SCLK, BCK, DATA, LRCK: V
I
= VDD, VDD = 5 V 10FORMAT, MUTE, DEMP: V
I
= VDD, VDD = 5 V 100
µASHUTDOWN: V
I
= 0 V, VCC = 12 V 1GAIN0, GAIN1, LR_SEL: V
I
= 0 V, VDD = 5 V 1I
IL
Low-level input current
BCK, SCLK, DATA, LRCK, FORMAT, MUTE, DEMP:
10V
I
= 0 V, VDD = 5 VV
OH
High-level output voltage I
OH
= –1 mA, ZERO 2.4
VV
OL
Low-level output voltage I
OL
= 1 mA, ZERO 0.4f
OSC
Oscillator frequency 200 300 kHz
All specifications at T
A
= 25 °C, V
DD
= 5 V, f
S
= 44.1 kHz, system clock = 384 f
S
and 24-bit data, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY REQUIREMENTS
(1)
f
S
= 44.1 kHz 26 31I
DD
Supply current f
S
= 96 kHz 25 mAf
S
= 192 kHz 30
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS
Pass band ±0.04 dB 0.454 f
s
Stop band 0.546 f
s
Pass-band ripple ±0.04 dBStop-band attenuation Stop band = 0.546 f
S
–50 dB
ANALOG FILTER PERFORMANCE
At 20 kHz –0.03Frequency response dBAt 44 kHz –0.20
SAMPLING FREQUENCY
fs Sampling frequency 5 200 KHz
DYNAMIC PERFORMANCE
Channel separation f
S
= 44.1 KHz, 96 KHz, 192 KHz 100 dB
(1) Conditions in 192-kHz operation are system clock = 128 f
S
and oversampling rate = 64 f
S
of register 18.
3

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FORMAT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
All specifications at T
A
= 25 °C, V
DD
= 5 V, f
S
= 44.1 kHz, system clock = 384 f
S
and 24-bit data, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
Data
Audio-data interface format Audio I
2
S, standardAudio-data bit length Audio 16–24-bit (I
2
S), 16-bit (Right-justified)Audio data format MSB first, 2s complementSystem clock frequency 128 f
S,
192 f
S
, 256 f
S
, 384 f
S
,512 f
S
, 768 f
S
, 1152 f
S
at T
A
= 25 °C, PV
CC
= V
CC
= 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OS
| Output offset voltage (measured differentially) MUTE = 2 V A
V
= 12 dB 100 mVPSRR Power supply rejection ratio PV
CC
= 11.5 V to 12.5 V –73 dBV
REF
5 V regulator voltage I
L
= 10 mA, V
CC
= 8 V – 18 V 4.55 4.9 5.45 VSHUTDOWN = 2.0 V, No load 8 15 mAI
CC
Supply current
SHUTDOWN = V
CC
, V
CC
= 18 V, PO = 20 W, 1.3
AR
L
= 8 ΩI
CC(SD)
Supply current shutdown mode SHUTDOWN = 0.8 V 1 2 µAOutput transistor on resistance (high side andr
DS(on)
I
O
= 0.5 A, T
J
= 25 °C 0.5 0.6 0.7 Ωlow side)
GAIN1 = 0.8 V, GAIN0 = 0.8 V 10.9 12 13.1G Gain GAIN1 = 0.8 V, GAIN0 = 2 V 17.1 18 18.6 dBGAIN1 = 2 V, GAIN0 = 0.8 V 22.9 23.6 24.4
PV
CC
= V
CC
= 12 V, T
A
= 25 °C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Continuous output power at 10% THD+N f = 1 kHz, R
L
= 4 Ω12.8f = 1 kHz, R
L
= 8 Ω9P
O
WContinuous output power at 1% THD+N f = 1 kHz, R
L
= 4 Ω10.3f = 1 kHz, R
L
= 8 Ω7.5THD+N Total harmonic distortion plus noise P
O
= 10 W, R
L
= 4 Ω f = 20 Hz to 20 kHz 0.2%B
OM
Maximum output power bandwidth THD = 1% 20 kHzk
SVR
Supply ripple rejection ratio f = 1 kHz, C
(BYPASS)
= 1 µF –60
dBSNR Signal-to-noise ratio P
O
= 10 W, R
L
= 4 Ω95C
(BYPASS)
= 1 µF, f = 20 Hz to 22 kHz, 150 µV(rms)V
n
Noise output voltage
A-weighted filter Gain = 12 dB
–76.5 dBV
4

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Audio
Serial
Port
Serial
Control
Port
4x/8x
Oversampling
Digital
Filter
and
Function
Control Multi-Level
Delta-Sigma
Modulator
Audio
Serial
Port
System Clock
BCK
LRCK
DATA
FORMAT
MUTE
DEMP
SCLK
DAC and
2:1 Mux
LR_SEL
VCOM
Gain
Adjust
−
++
−
Gain
Adjust
FLT1
FLT2 _
+
_
+
_
+
_
+
Deglitch
Logic
Deglitch
Logic
Gate
Drive
Gate
Drive
Clamp
Reference
Short-Circuit
Detect
Start-Up
Protection
Logic
Thermal VCC OK
SD
Gain
SHUTDOWN
GAIN0
GAIN1 2Biases
and
References Ramp
Generator
VREF AGND AVCC
VREF AVCC
Power Supply
Zero Detect
COSC
ROSC
BYPASS
ZERO
VDD
DGND
VCLAMP
BSN
PVCC
OUTN
PGND
BSP
OUTP
PGND
PVCC
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Functional Block Diagram
5

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1
BCK SCLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
LRCK
DATA
DGND
VDD
LR_SEL
VDD
DGND
VCOM
GAIN0
GAIN1
SHUTDOWN
PGND
VCLAMP
NC
BSN
PVCC
OUTN
OUTN
PGND
PGND
FORMAT
MUTE
DEMP
DGND
ZERO
DGND
FLT1
FLT2
VCC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PVCC
OUTP
OUTP
PGND
PGND
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
DCP
(TOP VIEW)
6

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TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Terminal Functions
TERMINAL
I/O DESCRIPTIONNO. NAME
1 BCK I Bit clock input for audio data3 DATA I Audio data input4 LRCK I Left and right channel audio data latch enable inputSelect left-channel or right-channel data7 LR_SEL I HIGH: Left channel activeLOW: Right channel active11 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to 5 V.12 GAIN1 I Gain select most significant bit. TTL logic levels with compliance to 5 V.Shutdown signal for IC (low = shutdown, high = operational).13 SHUTDOWN I
TTL logic levels with compliance to 18 V.5, 9, 38, 40 DGND - Digital ground6, 8 VDD - Digital power supply (4.5 V – 5.5 V)15 VCLAMP - Internally generated voltage supply for bootstrap capacitor17 BSN I/O Bootstrap I/O, negative high-side FET28 BSP I/O Bootstrap I/O, positive high-side FET2, 16 NC - No internal connection31 ROSC I/O I/O for current setting resistor for ramp generator32 COSC I/O I/O for charge/discharging currents onto capacitor for ramp generator creation33 BYPASS O Midrail analog reference voltage34 VREF O Analog 5-V regulated output. Not to be used for powering external circuitry.35 VCC - High-voltage analog power supply (8 V to 18 V).19, 20 OUTN O Class-D 1/2-H-bridge negative outputZero flag outputHIGH: No input present39 ZERO O
LOW: Data present at inputThis can be used to shutdown the device when no data is present at input.De-emphasis control.41 DEMP I HIGH: 44.1 kHz De-emphasis ONLOW: 44.1 kHz De-emphasis OFFSoft mute control42 MUTE I HIGH: Mute ONLOW: Mute OFFAudio data format select43 FORMAT I HIGH: 16-bit right justifiedLOW: 16- to 24-bit, I
2
S format44 SCLK I System clock input18, 27 PVCC - Power supply for H-bridge (8 V to 18 V)25, 26 OUTP O Class-D 1/2-H-bridge positive output29, 30 AGND - Analog ground14, 21, 22, 23, 24 PGND - Power ground for H-bridge10 VCOM - Midrail digital reference voltage36 FLT2 I/O
Noise-filter terminals. Connect capacitor across pins 36 and 3737 FLT1 I/O
Connect to AGND and PGND - should be the center point for both grounds.Thermal Pad
Internal esistive connection to AGND.
7

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TYPICAL CHARACTERISTICS
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 10100m 200m 1 2
Total Hormonic Distortion Plus Noise − %
PO− Output Power − W
20 Hz
1 kHz
10 kHz
VCC = 12 V
RL= 8 
Gain = 18 dB
fS= 48 kHz
24−bit, I2S format
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 10100m 200m 1 2
Total Hormonic Distortion Plus Noise − %
PO− Output Power − W
20 Hz
1 kHz
10 kHz
VCC = 12 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 20100m 200m 110
THD+N - T
otal Harmonic Distortion + Noise - %
PO- Output Power - W
10 kHz
1 kHz
R = 4 ,
LÙ
Gain = 18 dB,
f = 48 kHz,
s
24-bit, I S format
2
V = 12 V
CC
20 Hz
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 20 100m 200m 110
2
Total Hormonic Distortion Plus Noise − %
PO− Output Power − W
20 Hz
1 kHz
10 kHz
VCC = 18 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noisevs vsOutput Power Output Power
Figure 1. Figure 2.
Harmonic Distortion Plus Noise Total Harmonic Distortionvs vsOutput Power Power
Figure 3. Figure 4.
8

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0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
PO= 1 W
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
VCC = 12 V
RL= 8 
Gain = 18 dB
fS= 48 kHz
24−bit, I2S format
PO= 5 W
PO= 500 mW
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
PO= 500 mW
PO= 1 W
PO= 5 W
VCC = 12 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
PO= 500 mW
PO= 1 W
PO= 5 W
VCC = 18 V
RL= 8 
Gain = 18 dB
fS= 48 kHz
24−bit, I2S format
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20 20k100 200 1k 2k 10k
Total Hormonic Distortion Plus Noise − %
f − Frequency − Hz
PO= 500 mW
PO= 1 W
PO= 5 W
VCC = 18 V
RL= 8 
Gain = 23.6 dB
fS= 48 kHz
24−bit, I2S format
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noisevs vsFrequency Frequency
Figure 5. Figure 6.
Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noisevs vsFrequency Frequency
Figure 7. Figure 8.
9

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0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k50 100 200 500 1k 2k 5k 10k
THD + N - Total Harmonic Distortion + Noise - %
f - Frequency - Hz
V = 12 V
CC
R = 4
LÙ
Gain = 18 dB
f = 48 kHz
S
24-Bit, I S format
2
P = 2 W
o
P = 200 mW
o
P = 7.5 W
o
−70
−60
−50
−40
−30
−20
−10
0
20 100 1 k 10 k 20 k
f − Frequency − Hz
PSRR − Power Supply Rejecyion Ratio − dB
VCC = 12 V
V(RIPPLE) = 200 mVPP
RL= 8 
Gain = 18 dB
0
10
20
30
40
50
60
70
80
90
0 2 4 6 8 10 12 14
PO− Output Power − W
4 Ω
8 Ω
Efficiency − %
VCC = 12 V
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
TA= 25°C,
10% THD Maximum
ZL− Load Impedance − Ω
− Output Power − WPO
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Total Harmonic Distortion Power Supply Voltage Rejection Ratiovs vsFrequency Frequency
Figure 9. Figure 10.
Efficiency Output Powervs vsOutput Power Load Impedance
Figure 11. Figure 12.
10