Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP Multichannel BufferedSerial Port (McBSP)
Reference Guide
Literature Number: SPRU580EDecember 2005

2 SPRU580E – December 2005

Contents
Preface ............................................................................................................................... 9
1 Multichannel Buffered Serial Port (McBSP) .................................................................. 111.1 Features ............................................................................................................ 12
2 McBSP Interface ....................................................................................................... 132.1 McBSP Interface .................................................................................................. 14
3 McBSP Overview ...................................................................................................... 173.1 Resetting the Serial Port: RRST, XRST, GRST, and RESET ............................................... 183.2 Determining Ready Status ....................................................................................... 193.2.1 Receive Ready Status: REVT, RINT, and RRDY .................................................... 193.2.2 Transmit Ready Status: XEVT, XINT, and XRDY ................................................... 193.3 CPU Interrupts: RINT, XINT ..................................................................................... 193.4 Frame and Clock Configuration ................................................................................. 20
4 Clocks, Frames, and Data .......................................................................................... 214.1 Frame and Clock Operation ..................................................................................... 224.2 Sample Rate Generator Clocking and Framing ............................................................... 234.3 Data Clock Generation ........................................................................................... 244.3.1 Input Clock Source Mode: CLKSM .................................................................... 244.3.2 Sample Rate Generator Data Bit Clock Rate: CLKGDV ............................................ 254.3.3 Bit Clock Polarity: CLKSP ............................................................................... 254.3.4 Bit Clock and Frame Synchronization ................................................................. 254.3.5 Digital Loopback Mode: DLB ........................................................................... 274.3.6 Receive Clock Selection: DLB, CLKRM ............................................................... 274.3.7 Transmit Clock Selection: CLKXM ..................................................................... 274.3.8 Stopping Clocks .......................................................................................... 274.4 Frame Sync Generation .......................................................................................... 284.4.1 Frame Period (FPER) and Frame Width (FWID) .................................................... 284.4.2 Receive Frame Sync Selection: DLB, FSRM, GSYNC ............................................. 294.4.3 Transmit Frame Sync Selection: FSXM, FSGM ..................................................... 304.4.4 Frame Detection for Initialization ....................................................................... 304.5 Data and Frames .................................................................................................. 304.5.1 Frame Synchronization Phases ........................................................................ 304.5.2 Frame Length: RFRLEN1/2, XFRLEN1/2 ............................................................. 314.5.3 Element Length: RWDLEN1/2, XWDLEN1/2 ......................................................... 314.5.4 Data Packing using Frame Length and Element Length ........................................... 324.5.5 Data Delay: RDATDLY, XDATDLY .................................................................... 334.5.6 Receive Data Justification and Sign Extension: RJUST ............................................ 344.5.7 32-Bit Bit Reversal: RWDREVRS, XWDREVRS ..................................................... 344.6 Clocking and Framing Examples ................................................................................ 354.6.1 Multiphase Frame Example: AC97 .................................................................... 354.6.2 Double-Rate ST-BUS Clock ............................................................................ 354.6.3 Single-Rate ST-BUS Clock ............................................................................. 374.6.4 Double-Rate Clock ....................................................................................... 38
5 McBSP Standard Operation ....................................................................................... 39
SPRU580E – December 2005 Contents 3

5.1 Receive Operation ................................................................................................ 405.2 Transmit Operation ................................................................................................ 415.3 Maximum Frame Frequency ..................................................................................... 415.4 Frame Synchronization Ignore................................................................................... 425.4.1 Frame Sync Ignore and Unexpected Frame Sync Pulses .......................................... 425.4.2 Data Packing using Frame Sync Ignore Bits ......................................................... 435.5 Serial Port Exception Conditions ................................................................................ 445.5.1 Receive Overrun: RFULL ............................................................................... 445.5.2 Unexpected Receive Frame Synchronization: RSYNCERR ....................................... 455.5.3 Transmit With Data Overwrite .......................................................................... 475.5.4 Transmit Empty: XEMPTY .............................................................................. 475.5.5 Unexpected Transmit Frame Synchronization: XSYNCERR ....................................... 48
6 µ-Law/A-Law Companding Hardware Operation ........................................................... 516.1 Companding Internal Data ....................................................................................... 526.2 Bit Ordering ........................................................................................................ 53
7 McBSP Initialization Procedure .................................................................................. 557.1 General Initialization Procedure ................................................................................. 567.2 Special Case: External Device is the Transmit Frame Master .............................................. 57
8 Multichannel Selection Operation ............................................................................... 618.1 Enabling Multichannel Selection ................................................................................ 628.2 Enabling and Masking of Channels in Normal Multichannel Selection Mode ............................. 628.3 Changing Element Selection ..................................................................................... 658.4 End-of-Subframe Interrupt ....................................................................................... 658.5 Enhanced Multichannel Selection Mode (C64x and C645x DSPs only) ................................... 658.6 DX Enabler: DXENA .............................................................................................. 67
9 SPI Protocol: CLKSTP ............................................................................................... 699.1 McBSP Operation as the SPI Master ........................................................................... 729.2 McBSP Operation as the SPI Slave ............................................................................ 729.3 McBSP Initialization for SPI Mode .............................................................................. 73
10 McBSP Pins as General-Purpose I/O ........................................................................... 75
11 Registers ................................................................................................................. 7711.1 Data Receive Register (DRR) ................................................................................... 8111.2 Data Transmit Register (DXR) ................................................................................... 8211.3 Serial Port Control Register (SPCR) ............................................................................ 8311.4 Receive Control Register (RCR) ................................................................................ 8611.5 Transmit Control Register (XCR) ................................................................................ 8811.6 Sample Rate Generator Register (SRGR) ..................................................................... 9011.7 Multichannel Control Register (MCR)........................................................................... 9111.8 Receive Channel Enable Register (RCER) .................................................................... 9311.9 Transmit Channel Enable Registers (XCER) .................................................................. 9411.10 Enhanced Receive Channel Enable Registers (RCERE0-3) ............................................... 9511.10.1 RCEREs Used in the Receive Multichannel Selection Mode ................................... 9611.11 Enhanced Transmit Channel Enable Registers (XCERE0-3) .............................................. 9811.11.1 XCEREs Used in a Transmit Multichannel Selection Mode ..................................... 9811.12 Pin Control Register (PCR) .................................................................................... 101
A Revision History ..................................................................................................... 103
Contents 4 SPRU580E – December 2005

List of Figures
2-1 McBSP Block Diagram .................................................................................................... 143-1 Frame and Clock Operation .............................................................................................. 204-1 Clock and Frame Generation ............................................................................................. 224-2 Receive Data Clocking .................................................................................................... 234-3 Transmit Data Clocking .................................................................................................... 234-4 Sample Rate Generator ................................................................................................... 244-5 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 .............................. 264-6 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 .............................. 264-7 Programmable Frame Period and Width ................................................................................ 294-8 Dual-Phase Frame Example .............................................................................................. 314-9 Single-Phase Frame and Four 8-Bit Elements ......................................................................... 324-10 Single-Phase Frame of One 32-Bit Element ............................................................................ 334-11 Data Delay .................................................................................................................. 334-12 Bit Data Delay Used to Discard Framing Bit ............................................................................ 344-13 AC97 Dual-Phase Frame Format ........................................................................................ 354-14 AC97 Bit Timing Near Frame Synchronization ......................................................................... 354-15 McBSP to ST-BUS Block Diagram ....................................................................................... 364-16 Double-Rate ST-BUS Clock Example ................................................................................... 364-17 Single-Rate ST-BUS Clock Example .................................................................................... 374-18 Double-Rate Clock Example .............................................................................................. 385-1 McBSP Standard Operation .............................................................................................. 405-2 Receive Operation ......................................................................................................... 405-3 Transmit Operation ......................................................................................................... 415-4 Maximum Frame Frequency for Transmit and Receive ............................................................... 415-5 Unexpected Frame Synchronization With (R/X) FIG = 0 ............................................................. 425-6 Unexpected Frame Synchronization With (R/X)FIG = 1 .............................................................. 435-7 Maximum Frame Frequency Operation with 8-Bit Data ............................................................... 435-8 Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 ................................................... 445-9 Serial Port Overrun ......................................................................................................... 455-10 Serial Port Receive Overrun Avoided ................................................................................... 455-11 Decision Tree Response to Receive Frame Synchronization Pulse ................................................ 465-12 Unexpected Receive Synchronization Pulse ........................................................................... 465-13 Transmit With Data Overwrite ............................................................................................ 475-14 Transmit Empty ............................................................................................................. 485-15 Transmit Empty Avoided .................................................................................................. 485-16 Decision Tree Response to Transmit Frame Synchronization Pulse ................................................ 495-17 Unexpected Transmit Frame Synchronization Pulse .................................................................. 496-1 Companding Flow .......................................................................................................... 526-2 Companding Data Formats ............................................................................................... 526-3 Transmit Data Companding Format in DXR ............................................................................ 526-4 Companding of Internal Data ............................................................................................. 538-1 Element Enabling by Subframes in Partitions A and B ................................................................ 638-2 XMCM = 00b FOR XMCM Operation .................................................................................... 648-3 XMCM - 01b, XPABLK = 00b, XCER = 1010b for XMCM Operation ............................................... 648-4 XMCM = 10b, XPABLK = 00b, XCER = 1010b for XMCM Operation ............................................... 648-5 XMCM = 11b, RPABLK = 00b, XPABLK = X, RCER = 1010b, XCER = 1000b for XMCM Operation .......... 658-6 DX Timing for Multichannel Operation ................................................................................... 679-1 SPI Configuration: McBSP as the Master ............................................................................... 709-2 Configuration: McBSP as the Slave ..................................................................................... 709-3 SPI Transfer with CLKSTP = 10b ........................................................................................ 719-4 SPI Transfer with CLKSTP = 11b ........................................................................................ 7111-1 Data Receive Register (DRR) ............................................................................................ 81
SPRU580E – December 2005 List of Figures 5

11-2 Data Transmit Register (DXR) ............................................................................................ 8211-3 Serial Port Control Register (SPCR) ..................................................................................... 8311-4 Receive Control Register (RCR) ......................................................................................... 8611-5 Transmit Control Register (XCR) ......................................................................................... 8811-6 Sample Rate Generator Register (SRGR) .............................................................................. 9011-7 Multichannel Control Register (MCR).................................................................................... 9111-8 Receive Channel Enable Register (RCER) ............................................................................. 9311-9 Transmit Channel Enable Registers (XCER) ........................................................................... 9411-10 Enhanced Receive Channel Enable Registers (RCERE0-3) ......................................................... 9511-11 Enhanced Transmit Channel Enable Registers (XCERE0-3) ........................................................ 9811-12 Pin Control Register (PCR) .............................................................................................. 101
List of Figures6 SPRU580E – December 2005

List of Tables
1-1 Enhanced Features on TMS320C6000 McBSP ........................................................................ 122-1 McBSP Interface Pins ..................................................................................................... 153-1 Reset State of McBSP Pins ............................................................................................... 184-1 Receive Clock Selection ................................................................................................... 274-2 Transmit Clock Selection .................................................................................................. 274-3 Receive Frame Synchronization Selection.............................................................................. 294-4 Transmit Frame Synchronization Selection ............................................................................. 304-5 RCR/XCR Fields Controlling Elements per Frame and Bits per Element .......................................... 314-6 Receive/Transmit Frame Length Configuration ........................................................................ 314-7 Receive/Transmit Element Length Configuration ...................................................................... 324-8 Effect of RJUST Bit Values With 12-Bit Example Data ABCh ........................................................ 344-9 Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh .................................................... 346-1 Justification of Expanded Data in DRR .................................................................................. 527-1 Receiver Clock and Frame Configurations ............................................................................. 567-2 Transmitter Clock and Frame Configurations .......................................................................... 569-1 SPI-Mode Clock Stop Scheme ........................................................................................... 7010-1 Configuration of Pins as General Purpose I/O ......................................................................... 7511-1 McBSP Registers for C620x/C670x DSP ............................................................................... 7711-2 McBSP Registers for C621x/C671x DSP ............................................................................... 7811-3 McBSP Registers for C64x DSP ......................................................................................... 7911-4 McBSP Registers for the C645x DSP ................................................................................... 8011-5 Data Receive Register (DRR) Field Descriptions ...................................................................... 8111-6 Data Transmit Register (DXR) Field Descriptions ..................................................................... 8211-7 Serial Port Control Register (SPCR) Field Descriptions .............................................................. 8311-8 Receive Control Register (RCR) Field Descriptions .................................................................. 8611-9 Transmit Control Register (XCR) Field Descriptions ................................................................. 8811-10 Sample Rate Generator Register (SRGR) Field Descriptions ........................................................ 9011-11 Multichannel Control Register (MCR) Field Descriptions ............................................................ 9111-12 Receive Channel Enable Register (RCER) Field Descriptions ....................................................... 9311-13 Transmit Channel Enable Register (XCER) Field Descriptions ...................................................... 9411-14 Enhanced Receive Channel Enable Registers (RCERE0-3) Field Descriptions ................................... 9511-15 Use of the Enhanced Receive Channel Enable Registers ............................................................ 9611-16 Enhanced Transmit Channel Enable Registers (XCERE0-3) Field Descriptions .................................. 9811-17 Use of the Enhanced Transmit Channel Enable Registers ........................................................... 9911-18 Pin Control Register (PCR) Field Descriptions ....................................................................... 101A-1 Document Revision History ............................................................................................. 103
SPRU580E – December 2005 List of Tables 7

List of Tables8 SPRU580E – December 2005

PrefaceSPRU580E – December 2005
Read This First
About This Manual
This document describes the operation of the multichannel buffered serial port (McBSP) in the digitalsignal processors (DSPs) of the TMS320C6000™ DSP family.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the C6000™ devices and related support tools. Copies of thesedocuments are available on the Internet at www.ti.com. Tip: Enter the literature number in the search boxprovided at www.ti.com.
TMS3206000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes theTMS320C6000™ CPU architecture, instruction set, pipeline, and interrupts for these digital signalprocessors.
TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x™and TMS320C67x™ DSPs, development tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the TMS320C64x™ DSP anddiscusses the application areas that are enhanced by the TMS320C64x VelociTI™.
TMS320C6455 Technical Reference (literature number SPRU965) gives an introduction to theTMS320C6455™ DSP and discusses the application areas that are enhanced.
TMS320C6000 Programmer's Guide (literature number SPRU198 ) describes ways to optimize C andassembly code for the TMS320C6000™ DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301 ) introduces the CodeComposer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference Guide (literature numberSPRU321 ) describes the Code Composer Studio™ application programming interface (API), which allowsyou to program custom plug-ins for Code Composer.
TMS320C6000 Chip Support Library API Reference Guide (literature number SPRU401 ) describes aset of application programming interfaces (APIs) used to configure and control the on-chip peripherals.
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 ) describes theTMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal directmemory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,bandwidth management, and the memory and cache.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190 ) provides abrief description of the peripherals available on the TMS320C6000 digital signal processors (DSPs).
SPRU580E – December 2005 Read This First 9

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Related Documentation From Texas Instruments
TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234 ) is a download with the latestchip support libraries.
Read This First10 SPRU580E – December 2005

Chapter 1SPRU580E – December 2005
Multichannel Buffered Serial Port (McBSP)
This document describes the operation of the multichannel buffered serial port(McBSP) in the digital signal processors (DSPs) of the TMS320C6000™ DSP family.
Topic .................................................................................................. Page
1.1 Features ................................................................................... 12
TMS320C6000, C6000, TMS320C62x, TMS320C67x, TMS320C64x, VelociTI, TMS320C6455, Code Composer Studio, ST-BUS aretrademarks of Texas Instruments.SPI is a trademark of Motorola, Inc..
SPRU580E – December 2005 Multichannel Buffered Serial Port (McBSP) 11

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1.1 Features
Features
The McBSP provides these functions:•Full-duplex communication•Double-buffered data registers, which allow a continuous data stream•Independent framing and clocking for receive and transmit•Direct interface to industry-standard codecs, analog interface chips (AICs), and other seriallyconnected analog-to-digital (A/D) and digital-to-analog (D/A) devices•External shift clock or an internal, programmable frequency shift clock for data transfer
In addition, the McBSP has the following capabilities:•Direct interface to:– T1/E1 framers– MVIP switching compatible and ST-BUS compliant devices including:•MVIP framers•H.100 framers•SCSA framers– IOM-2 compliant devices– AC97 compliant devices (The necessary multi phase frame synchronization capability is provided.)– IIS compliant devices– SPI™ devices•Multichannel transmit and receive of up to 128 channels•A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits•µ-Law and A-Law companding•8-bit data transfers with the option of LSB or MSB first•Programmable polarity for both frame synchronization and data clocks•Highly programmable internal clock and frame generation
All C6000™ devices have the same McBSP. However, the C621x/C671x and C64x McBSP haveadditional features and enhancements that are summarized in Table 1-1 .
Table 1-1. Enhanced Features on TMS320C6000 McBSP
Features C620x/C670x C621x/C671x McBSP C64x McBSP C645x McBSP
DX Enabler (DXENA) No Yes Yes Yes32-bit data reversal No Yes Yes Yes(RWDREVRS/XWDREVRS)
Enhanced multichannel selection No No Yes Yesmode (RMCME/XMCME)
Emulation control (FREE, SOFT) No Yes Yes Yes
12 Multichannel Buffered Serial Port (McBSP) SPRU580E – December 2005

Chapter 2SPRU580E – December 2005
McBSP Interface
The McBSP consists of a data path and a control path that connect to external devices.
Topic .................................................................................................. Page
2.1 McBSP Interface ....................................................................... 14
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2.1 McBSP Interface
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RBR
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CLKS
FSR
FSX
CLKR
CLKX
DX
DR
XEVT
REVT
XINT
RINT
events to DMA
Synchronization
Interrupts to CPU
bus
peripheral
32-bit
McBSP
Compand
XSR
RSR
Compress
Expand DRR
DXR
Multichannel
selection
and control
generation
frame sync
Clock and
PCR
XCER
RCER
MCR
XCR
SPCR
RCR
McBSP Interface
The McBSP consists of a data path and a control path that connect to external devices. Separate pins fortransmission and reception communicate data to these external devices. Four other pins communicatecontrol information (clocking and frame synchronization). The device communicates to the McBSP using32-bit-wide control and data registers accessible via the internal peripheral bus.
On C645x DSPs, the CPU accesses the control and data registers via a configuration bus. The EDMA3controller uses its dedicated bus, the EDMA bus, to access the data registers.
The McBSP consists of a data path and control path, as shown in Figure 2-1 . Seven pins, listed inTable 2-1 , connect the control and data paths to external devices.
Figure 2-1. McBSP Block Diagram
A On C645x DSPs, the CPU accesses the control and data registers via a configuration bus. The EDMA3 controlleruses its dedicated bus, the EDMA bus, to access the data registers.
Data is communicated to devices interfacing to the McBSP via the data transmit (DX) pin for transmissionand via the data receive (DR) pin for reception. Control information (clocking and frame synchronization) iscommunicated via CLKS, CLKX, CLKR, FSX, and FSR. The C6000 CPU communicates with the McBSPby reading or writing to its 32-bit-wide control registers. Non-32-bit write accesses to control registers canresult in corrupting the control register value. This is because undefined values are written to non-enabledbytes. However, non-32-bit read accesses return the correct value.
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McBSP InterfaceEither the CPU or the DMA/EDMA controller reads the received data from the data receive register (DRR)and writes the data to be transmitted to the data transmit register (DXR). Data written to DXR is shifted outto DX via the transmit shift register (XSR). Similarly, receive data on the DR pin is shifted into the receiveshift register (RSR) and copied into the receive buffer register (RBR). RBR is then copied to DRR, whichcan be read by the CPU or the DMA/EDMA controller. This allows simultaneous internal data movementand external data communications. For information on registers, see Chapter 11 .
Table 2-1. McBSP Interface Pins
Pin I/O/Z Description
CLKR I/O/Z Receive clockCLKX I/O/Z Transmit clockCLKS I External clockDR I Received serial dataDX O/Z Transmitted serial dataFSR I/O/Z Receive frame synchronizationFSX I/O/Z Transmit frame synchronization
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McBSP Interface
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Chapter 3SPRU580E – December 2005
McBSP Overview
As shown in Figure 2-1 , the receive operation is triple-buffered and the transmitoperation is double-buffered. Receive data arrives on the DR and is shifted into theRSR. Once a full element (8, 12, 16, 20, 24, or 32 bits) is received, the RSR is copiedto the receive buffer register (RBR) only if the RBR is not full. The RBR is then copiedto DRR unless the DRR has not been read by the CPU or the DMA/EDMA controller.
The CPU or the DMA/EDMA controller writes transmit data to DXR. If there is no datain XSR, the value in DXR is copied to XSR. Otherwise, the DXR is copied to XSR whenthe last bit of data is shifted out on the DX. After transmit frame synchronization, XSRbegins shifting out the transmit data on the DX.
Topic .................................................................................................. Page
3.1 Resetting the Serial Port: RRST, XRST, GRST, and RESET ............ 183.2 Determining Ready Status .......................................................... 193.3 CPU Interrupts: RINT, XINT ........................................................ 193.4 Frame and Clock Configuration .................................................. 20
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3.1 Resetting the Serial Port: RRST, XRST, GRST, and RESET
Resetting the Serial Port: RRST, XRST, GRST, and RESET
The serial port can be reset in two ways:•Device reset ( RESET pin is low) places the receiver, the transmitter, and the sample rate generator inreset. If it is removed ( RESET = 1), FRST = GRST = RRST = XRST = 0, the entire serial port is kept inthe reset state.•The serial port transmitter and receiver can be independently reset by the XRST and RRST bits in theserial port control register (SPCR). The sample rate generator is reset by the GRST bit in SPCR.
Table 3-1 shows the state of the McBSP pins when the serial port is reset by these methods.
Table 3-1. Reset State of McBSP Pins
Device ResetPin Direction ( RESET = 0) McBSP Reset
Receiver Reset (RRST = 0 and GRST = 1)
DR I Input InputCLKR I/O/Z Input CLKRM bit determines if CLKR pin is input or output; if configured asoutput, pin is driven by CLKRFSR I/O/Z Input FSRM bit determines if FSR pin is input or output; if configured as output,FSR is driven inactive as specified by FSRPCLKS I Input Input
Transmitter Reset (XRST = 0 and GRST = 1)
DX O/Z High impedance High impedanceCLKX I/O/Z Input CLKXM bit determines if CLKX pin is input or output; if configured asoutput, pin is driven by CLKXFSX I/O/Z Input FSXM bit determines if FSX pin is input or output; if configured as output,FSX is driven inactive as specified by FSXPCLKS I Input Input
•Device reset or McBSP reset: Resetting the McBSP by device or McBSP reset also resets the statemachine to its initial state, and resets all counters and status bits. This includes the receive status bits(RFULL, RRDY, RSYNCERR), and the transmit status bits (XEMPTY, XRDY, XSYNCERR).•Device reset: When the McBSP is reset by device reset, the entire serial port (including thetransmitter, receiver, and the sample rate generator) is reset. All input-only pins and 3-state pinsshould be in a known state. The output-only pin, DX, is in the high-impedance state. See Section 4.2for more information on the sample rate generator. When the device is pulled out of reset, the serialport remains in the reset condition (RRST = XRST = FRST = GRST = 0). In this reset condition, theserial port pins can be used as general-purpose I/O (see Chapter 10 ).•McBSP reset: When the receiver and transmitter reset bits (RRST, XRST), are cleared, the respectiveportions of the McBSP are reset and activity in the corresponding section stops. All input-only pins,such as DR and CLKS, and all other pins that are configured as inputs are in a known state. FS(R/X)is driven to its inactive state if it is an output, as well as its polarity bit, FS(R/X)P. CLKG drivesCLK(R/X) provided that GRST = 1 and they are programmed as outputs. The DX pin is in thehigh-impedance state when the transmitter is reset. During normal operation, clearing GRST resets thesample rate generator. GRST should be low only when neither the transmitter nor the receiver is usingthe sample rate generator. In this case, the internal sample rate generator clock CLKG, and its framesync signal (FSG) are driven inactive (low). When the sample rate generator is not in the reset state(GRST = 1), FSR and FSX are in an inactive state when RRST = 0 and XRST = 0, respectively, even ifthey are outputs driven by FSG. Thus, when only one portion of the McBSP is in reset, the otherportion can continue operation when FRST = 1 and frame sync is driven by FSG. After reset in C645xdevices, McBSP will disregard the first frame sync, and the data in XSR will be shifted out at thesecond frame sync. During that time, the data write by the DMA will be ready for transmit.•Sample-rate generator reset: The sample rate generator is reset when the device is reset or when itsreset bit, GRST, is cleared.
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3.2 Determining Ready Status
3.2.1 Receive Ready Status: REVT, RINT, and RRDY
3.2.2 Transmit Ready Status: XEVT, XINT, and XRDY
3.3 CPU Interrupts: RINT, XINT
Determining Ready Status
A transmit frame sync error (XSYNCERR) may occur the first time the transmitter is enabled (XRST = 1)after a device reset (Chapter 7 ).
The RRDY and XRDY bits in SPCR indicate the ready state of the McBSP receiver and transmitter,respectively. Writes and reads from the serial port can be synchronized by any of the following methods:•Polling RRDY and XRDY bits•Using the events sent to the DMA or EDMA controller (REVT and XEVT)•Using the interrupts to the CPU (RINT and XINT) that the events generate
Reading DRR and writing to DXR affects RRDY and XRDY, respectively.
RRDY = 1 indicates that the RBR contents have been copied to DRR and that the data can now be readby either the CPU or the DMA/EDMA controller. Once that data has been read by either the CPU or theDMA/EDMA controller, RRDY is cleared to 0. Also, at device reset or serial port receiver reset (RRST =0), the RRDY bit is cleared to 0 to indicate that no data has been received and loaded into DRR. RRDYdirectly drives the McBSP receive event to the DMA/EDMA controller (via REVT). Also, the McBSPreceive interrupt (RINT) to the CPU can be driven by RRDY, if RINTM = 00b (default value) in SPCR.
XRDY = 1 indicates that the DXR contents have been copied to XSR and that DXR is ready to be loadedwith a new data word. When the transmitter transitions from reset to non-reset (XRST transitions from 0 to1), XRDY also transitions from 0 to 1 indicating that DXR is ready for new data. Once new data is loadedby the CPU or the DMA/EDMA controller, the XRDY bit is cleared to 0. However, once this data is copiedfrom DXR to XSR, the XRDY bit transitions again from 0 to 1. The CPU or the DMA/EDMA controller canwrite to DXR although XSR has not yet been shifted out on DX. XRDY directly drives the transmitsynchronization event to the DMA/EDMA controller (via XEVT). Also, the McBSP transmit interrupt (XINT)to the CPU can be driven by XRDY, if XINTM = 00b (default value) in SPCR.
Note: If the polling method is used to service the transmitter, the CPU should wait for oneMcBSP bit clock (CLKX) before polling again to write the next element in DXR. This isbecause XRDY transitions occur based on bit clock and not CPU clock. The CPU clock ismuch faster and can cause false XRDY status, leading to data errors due to over-writes.
The receive interrupt (RINT) and transmit interrupt (XINT) signals inform the CPU of changes to the serialport status. Four options exist for configuring these interrupts. These options are set by thereceive/transmit interrupt mode bits (RINTM and XINTM) in SPCR. The possible values of the mode, andthe configurations they represent, are:•(R/X)INTM = 00b. Interrupt on every serial element by tracking the (R/X)RDY bits in SPCR.•(R/X)INTM = 01b. Interrupt at the end of a subframe (16 elements or less) within a frame (Section 8.4 ).•(R/X)INTM = 10b. Interrupt on detection of frame synchronization pulses. This generates an interrupteven when the transmitter/receiver is in reset. This is done by synchronizing the incoming frame syncpulse to the CPU clock and sending it to the CPU via (R/X)INT (Section 4.4.4 ).•(R/X)INTM = 11b. Interrupt on frame synchronization error. If any of the other interrupt modes areselected, (R/X)SYNCERR may be read when servicing the interrupts to detect this condition(Section 5.5.2 and Section 5.5.5 ).
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3.4 Frame and Clock Configuration
D(R/X)
FS(R/X)
CLK(R/X)
B3 B2 B1 B0B5 B4B6B7A0A1
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Frame and Clock Configuration
Figure 3-1 shows typical operation of the McBSP clock and frame sync signals. Serial clocks CLKR andCLKX define the boundaries between bits for receive and transmit, respectively. Similarly, frame syncsignals FSR and FSX define the beginning of an element and/or frame transfer. The McBSP allowsconfiguration of the following parameters for data and frame synchronization:•Polarities of FSR, FSX, CLKX, and CLKR•A choice of single- or dual-phase frames•For each phase, the number of elements per frame•For each phase, the number of bits per element•Whether subsequent frame synchronization restarts the serial data stream or is ignored•The data delay from frame synchronization to first data bit which can be 0-, 1-, or 2-bit delays•Right or left justification as well as sign extension or zero filling for receive data.
The configuration is independent for receive and transmit.
Figure 3-1. Frame and Clock Operation
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