Texas Instruments TMS320C6711D User manual

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DExcellent-Price/Performance Floating-Point
Digital Signal Processor (DSP):
TMS320C6711D
− Eight 32-Bit Instructions/Cycle
− 167-, 200-, 250-MHz Clock Rates
− 6-, 5-, 4-ns Instruction Cycle Time
− 1000, 1200, 1500 MFLOPS
DAdvanced Very Long Instruction Word
(VLIW) C67xDSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
DInstruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
DL1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
DDevice Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
DEnhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
D16-Bit Host-Port Interface (HPI)
DTwo Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
DTwo 32-Bit General-Purpose Timers
DFlexible Software Configurable PLL-Based
Clock Generator Module
DA Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins
DIEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
D272-Pin Ball Grid Array (BGA) Package
(GDP and ZDP Suffixes)
DCMOS Technology
− 0.13-µm/6-Level Copper Metal Process
D3.3-V I/O, 1.4-V Internal (−250)
D3.3-V I/O, 1.20-V Internal ‡
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
   ! "#$ !  %#&'" ($)
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TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡These values are compatible with existing 1.26V designs.

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Table of Contents
EMIF big endian mode correctness 60. . . . . . . . . . . . . . . .
bootmode 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range 62. . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 62. . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature 63.
parameter measurement information 64. . . . . . . . . . . . . . .
signal transition levels 64. . . . . . . . . . . . . . . . . . . . . . . . . .
timing parameters and board routing analysis 66. . . . . .
input and output clocks 68. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 71. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 74. . . . . . . . . . . . . . . . .
synchronous DRAM timing 76. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 82. . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUSREQ timing 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 86. . . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface timing 87. . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing 91. . . . . . . . . . . . .
timer timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
general-purpose input/output (GPIO) port timing 101. . . .
JTAG test-port timing 102. . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
revision history 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GDP and ZDP BGA packages (bottom view) 4. . . . . . . . . . . .
description 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device compatibility 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block and CPU (DSP core) diagram 8. . . . . . . . . . .
CPU (DSP core) description 9. . . . . . . . . . . . . . . . . . . . . . . . . .
memory map summary 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
peripheral register descriptions 12. . . . . . . . . . . . . . . . . . . . . . .
signal groups description 17. . . . . . . . . . . . . . . . . . . . . . . . . . . .
device configurations 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
terminal functions 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device support 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU CSR register description 40. . . . . . . . . . . . . . . . . . . . . . . .
cache configuration (CCFG) register description 42. . . . . . . .
interrupt sources and interrupt selector 43. . . . . . . . . . . . . . . .
EDMA module and EDMA selector 44. . . . . . . . . . . . . . . . . . . .
PLL and PLL controller 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
general-purpose input/output (GPIO) 53. . . . . . . . . . . . . . . . . .
power-down mode logic 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing 56. . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply decoupling 58. . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 JTAG compatibility statement 58. . . . . . . . . . . . .
EMIF device speed 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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REVISION HISTORY
The TMS320C6711D device-specific documentation has been split from TMS320C6711, TMS320C6711B,
TMS320C6711C, TMS320C6711D Floating−Point Digital Signal Processors, literature number SPRS088N, into a
separate Data Sheet, literature number SPRS292. It also highlights technical changes made to SPRS292 to gen-
erate SPRS292A; these changes are marked by “[Revision A]” in the Revision History table below.
Scope: Updated information on McBSP and JTAG for clarification. Changed Pin Description for A12 and B11
(Revisions SPRS292 and SPRS292A). Updated Nomenclature figure by adding device−specific information for
the ZDP package. Updated Characteristics of the Processor table with device−specific information (footnote) for
the ZDP package
TI Recommends for new designs that the following pins be configured as such:
DPin A12 connected directly to CVDD (core power)
DPin B11 connected directly to Vss (ground)
PAGE(S)
NO. ADDITIONS/CHANGES/DELETIONS
21 Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:
Removed “CE1 width 32−bit” from Functional Description for “00” in HD[4:3](BOOTMODE) Configuration Pin
25 Terminal Functions, Resets and Interrupts section:
Updated IPU/IPD for RESET Signal Name from “IPU” to “−−”
26 Terminal Functions, Host Port Interface section:
Removed “CE1 width 32−bit” from Description for “00” in Bootmode HD[4:3]
31 Terminal Functions, Reserved for Test section:
Updated Description for RSV Signal Name, A12 GDP/ZDP
Updated Description for RSV Signal Name, B11 GDP/ZDP
31 Terminal Functions, Reserved for Test section:
Updated/changed Description for RSV Signal Name, A12 GDP (to “recommended”) − [Revision A]
Updated/changed Description for RSV Signal Name, B11 GDP (to “recommended”) − [Revision A]
38 Device Support, device and development-support tool nomenclature:
Updated figure for clarity
39 Device Support, documentation support section:
Updated paragraphs for clarity
58 IEEE 1149.1 JTAG Compatibility Statement section:
Updated/added paragraphs for clarity
62 Recommended Operating Conditions:
Added VOS, Maximum voltage during overshoot row and associated footnote
Added VUS, Maximum voltage during undershoot row and associated footnote
65 Parameter Measurement Information:
AC transient rise/fall time specifications section:
Added AC Transient Specification Rise Time figure
Added AC Transient Specification Fall Time figure
93 MULTICHANNEL BUFFERED SERIAL PORT TIMING:
switching characteristics over recommended operating conditions for McBSP section:
Updated McBSP Timings figure for clarification

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GDP and ZDP BGA packages (bottom view)
GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGES†
(BOTTOM VIEW)
2468 201816141210
M
E
A
1
C
B
D
G
F
H
K
J
L
W
R
N
P
U
T
V
Y
357911 171513 19
†The ZDP mechanical package designator represents the version of the GDP package with lead−free balls. For more detailed information, see
the Mechanical Data section of this document.

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description
The TMS320C67xDSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D
devices†) compose the floating-point DSP family in the TMS320C6000DSP platform. The C6711, C6711B,
C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word
(VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for
multichannel and multifunction applications.
With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of
200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective
solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational
flexibility of high-speed controllers and the numerical capability of array processors. This processor has
32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight
functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point
multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS.
The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals.
The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs),
two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF)
capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windowsdebugger interface for visibility into source code
execution.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
†Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated
as C6711D or 11D.

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device characteristics
Table 1 provides an overview of the C6711D DSP. The table shows significant features of the device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more
details on the C6000DSP device part numbers and part numbering, see Figure 5.
Table 1. Characteristics of the C6711D Processor
HARDWARE FEATURES INTERNAL CLOCK
SOURCE C6711D FLOATING-POINT DSP
EMIF
ECLKIN
EMIF SYSCLK3 or ECLKIN 1
EDMA CPU clock frequency 1
HPI
CPU/2 clock frequency
Peripherals
HPI SYSCLK2 1
Peripherals
McBSPs
CPU/2 clock frequency
McBSPs SYSCLK2 2
32-Bit Timers
CPU/4 clock frequency —
32-Bit Timers 1/2 of SYSCLK2 2
GPIO Module SYSCLK2 1
Size (Bytes) 72K
On-Chip Memory Organization
4K-Byte (4KB) L1 Program
(L1P) Cache
4KB L1 Data (L1D) Cache
64KB Unified Mapped
RAM/Cache (L2)
CPU ID+
CPU Rev ID Control Status Register (CSR.[31:16]) 0x0203
Frequency MHz 167, 200, 250
Cycle Time ns
4 ns (C6711DGDP-250)
5 ns (C6711DGDP−200
and C6711DZDP−200)
6 ns (C6711DGDPA−167
and C6711DZDPA−167)
Voltage
Core (V) 1.20†
1.4 (−250)
Voltage
I/O (V) 3.3
PLL Options CLKIN frequency multiplier −
Clock Generator Options Prescaler
Multiplier
Postscaler
/1, /2, /3, ..., /32
x4, x5, x6, ..., x25
/1, /2, /3, ..., /32
BGA Package 27 x 27 mm 272-Pin BGA
(GDP and ZDP)§
Process Technology µm0.13 µm
Product Status
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD‡
†These values are compatible with existing 1.26−V designs.
‡PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
§The ZDP package devices are supported in the same speed grades as the GDP package devices (available upon request).
C6000 is a trademark of Texas Instruments.

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device compatibility
The TMS320C6211/C6211B and C6711/C6711B devices are pin-compatible and have the same peripheral set;
thus, making new system designs easier and providing faster time to market. The following list summarizes the
device characteristic differences among the C6211, C6211B, C6711, C6711B, C6711C, and C6711D devices:
DThe C6211 and C6211B devices have a fixed-point C62x CPU, while the C6711, C6711B, C6711C, and
C6711D devices have a floating-point C67x CPU.
DThe C6211/C6211B device runs at -167 and -150 MHz clock speeds (with a C6211BGFNA extended
temperature device that also runs at -150 MHz), while the C6711/C6711B device runs at -150 and -100 MHz
(with a C6711BGFNA extended temperature device that also runs at -100 MHz) and the C6711C and
C6711D devices run at -200 clock speed (with a C6711CGDPA and C6711DGDPA extended temperature
devices that also run at -167 MHz).
DThe C6211/C6211B, C6711-100, and C6711B devices have a core voltage of 1.8 V, the C6711-150 device
core voltage is 1.9 V, and the C6711C and C6711D devices operate with a core voltage of 1.20†V.
DThere are several enhancements and features that are only available on the C6711C and C6711D devices,
such as: the CLKOUT3 signal, a software programmable PLL and PLL Controller, and a GPIO peripheral
module. The C6711D device also has additional enhancements such as: EMIF Big Endian mode
correctness EMIFBE and the L1D requestor priority to L2 bit [“P” bit] in the cache configuration (CCFG)
register.
For more detailed discussion on the migration of a C6211, C6211B, C6711, C6711B device to a TMS320C6711C
device, see the Migrating from TMS320C6211B/6711B to TMS320C6711C application report (literature number
SPRA837).
For a more detailed discussion on the similarities/differences between the C6211 and C6711 devices, see the
How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development with the
TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively).
†This value is compatible with existing 1.26V designs.

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functional block and CPU (DSP core) diagram
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Test
C6000CPU (DSP Core)
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-Down
Logic
.L1†.S1†.M1†.D1 .D2 .M2†.S2†.L2†
32
SDRAM
ROM/FLASH
SBSRAM
I/O Devices
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control
Logic
L1D Cache
2-Way Set
Associative
4K Bytes Total
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Digital Signal Processor
†In addition to fixed-point instructions, these functional units execute floating-point instructions.
‡The device has a software-configurable PLL (with x4 through x25 multiplier and /1 through /32 divider).
Enhanced
DMA
Controller
(16 channel)
16
L2
Memory
4 Banks
64K Bytes
Total
PLL‡
Timer 0
External
Memory
Interface
(EMIF)
Multichannel
Buffered
Serial Port 1
(McBSP1)
Multichannel
Buffered
Serial Port 0
(McBSP0)
Host Port
Interface
(HPI)
SRAM
Timer 1
Boot
Configuration
Interrupt
Selector
GPIO

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CPU (DSP core) description
The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit
instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by
which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit
of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous
instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch
packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute
packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and
Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all the registers on the other side, by which
the two sets of functional units can access data from the register files on the opposite side. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight
functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two
functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
10 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443
CPU (DSP core) description (continued)
8
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8
long src
dst
src2
src1
src1
src1
src1
src1
src1
src1
src1
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
long src
long dst
long dst
long src
8
8
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2X
1X
.L2†
.S2†
.M2†
.D2
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.M1†
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Control
Register File
Á
DA1
DA2
ST1
LD1 32 LSB
LD2 32 LSB
LD2 32 MSB
32
32
Data Path A
Data Path B
Register
File A
(A0−A15)
Register
File B
(B0−B15)
LD1 32 MSB
32
ST2 32
8
8
8
Á
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†In addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 1. TMS320C67xCPU (DSP Core) Data Paths

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
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memory map summary
Table 2 shows the memory map address ranges of the device. Internal memory is always located at address
0 and can be used as both program and data memory. The configuration registers for the common peripherals
are located at the same hex address ranges. The external memory address ranges in the device begin at the
address location 0x8000 0000.
Table 2. TMS320C6711D Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
Internal RAM (L2) 64K 0000 0000 – 0000 FFFF
Reserved 24M – 64K 0001 0000 – 017F FFFF
External Memory Interface (EMIF) Registers 256K 0180 0000 – 0183 FFFF
L2 Registers 256K 0184 0000 – 0187 FFFF
HPI Registers 256K 0188 0000 – 018B FFFF
McBSP 0 Registers 256K 018C 0000 – 018F FFFF
McBSP 1 Registers 256K 0190 0000 – 0193 FFFF
Timer 0 Registers 256K 0194 0000 – 0197 FFFF
Timer 1 Registers 256K 0198 0000 – 019B FFFF
Interrupt Selector Registers 512 019C 0000 – 019C 01FF
Device Configuration Registers 4019C 0200 – 019C 0203
Reserved 256K − 516 019C 0204 – 019F FFFF
EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF
Reserved 768K 01A4 0000 – 01AF FFFF
GPIO Registers 16K 01B0 0000 – 01B0 3FFF
Reserved 480K 01B0 4000 – 01B7 BFFF
PLL Controller Registers 8K 01B7 C000 – 01B7 DFFF
Reserved 4M + 520K 01B7 E000 – 01FF FFFF
QDMA Registers 52 0200 0000 – 0200 0033
Reserved 736M – 52 0200 0034 – 2FFF FFFF
McBSP 0 Data/Peripheral Data Bus 64M 3000 0000 – 33FF FFFF
McBSP 1 Data/Peripheral Data Bus 64M 3400 0000 – 37FF FFFF
Reserved 64M 3800 0000 – 3BFF FFFF
Reserved 1G + 64M 3C00 0000 – 7FFF FFFF
EMIF CE0†256M 8000 0000 – 8FFF FFFF
EMIF CE1†256M 9000 0000 – 9FFF FFFF
EMIF CE2†256M A000 0000 – AFFF FFFF
EMIF CE3†256M B000 0000 – BFFF FFFF
Reserved 1G C000 0000 – FFFF FFFF
†The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. To get 256MB of
addressable memory, additional general-purpose output pin or external logic is required.

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
12 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443
peripheral register descriptions
Table 3 through Table 14 identify the peripheral registers for the device by their register names, acronyms, and
hex address or hex address range. For more detailed information on the register contents, bit names, and their
descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview
Reference Guide (literature number SPRU190).
Table 3. EMIF Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0180 0000 GBLCTL EMIF global control
0180 0004 CECTL1 EMIF CE1 space control
0180 0008 CECTL0 EMIF CE0 space control
0180 000C − Reserved
0180 0010 CECTL2 EMIF CE2 space control
0180 0014 CECTL3 EMIF CE3 space control
0180 0018 SDCTL EMIF SDRAM control
0180 001C SDTIM EMIF SDRAM refresh control
0180 0020 SDEXT EMIF SDRAM extension
0180 0024 − 0183 FFFF − Reserved
Table 4. L2 Cache Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 0000 CCFG Cache configuration register
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback-invalidate base address register
0184 4014 L2WIWC L2 writeback-invalidate word count register
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback-invalidate base address register
0184 4034 L1DWIWC L1D writeback-invalidate word count register
0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback-invalidate all register
0184 8200 MAR0 Controls CE0 range 8000 0000 − 80FF FFFF
0184 8204 MAR1 Controls CE0 range 8100 0000 − 81FF FFFF
0184 8208 MAR2 Controls CE0 range 8200 0000 − 82FF FFFF
0184 820C MAR3 Controls CE0 range 8300 0000 − 83FF FFFF
0184 8240 MAR4 Controls CE1 range 9000 0000 − 90FF FFFF
0184 8244 MAR5 Controls CE1 range 9100 0000 − 91FF FFFF
0184 8248 MAR6 Controls CE1 range 9200 0000 − 92FF FFFF
0184 824C MAR7 Controls CE1 range 9300 0000 − 93FF FFFF
0184 8280 MAR8 Controls CE2 range A000 0000 − A0FF FFFF
0184 8284 MAR9 Controls CE2 range A100 0000 − A1FF FFFF
0184 8288 MAR10 Controls CE2 range A200 0000 − A2FF FFFF
0184 828C MAR11 Controls CE2 range A300 0000 − A3FF FFFF
0184 82C0 MAR12 Controls CE3 range B000 0000 − B0FF FFFF
0184 82C4 MAR13 Controls CE3 range B100 0000 − B1FF FFFF
0184 82C8 MAR14 Controls CE3 range B200 0000 − B2FF FFFF
0184 82CC MAR15 Controls CE3 range B300 0000 − B3FF FFFF
0184 82D0 − 0187 FFFF − Reserved

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
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peripheral register descriptions (continued)
Table 5. Interrupt Selector Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10−15
(INT10−INT15)
019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4−9
(INT04−INT09)
019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts
(EXT_INT4−EXT_INT7)
019C 000C − 019F FFFF − Reserved
Table 6. Device Registers
HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION
019C 0200 DEVCFG Device Configuration This register allows the user control of the EMIF input
clock source. For more detailed information on the
device configuration register, see the Device
Configurations section of this data sheet.
019C 0204 − 019F FFFF − Reserved
N/A CSR CPU Control Status Register
Identifies which CPU and defines the silicon revision of
the CPU. This register also offers the user control of
device operation.
For more detailed information on the CPU Control
Status Register, see the CPU CSR Register
Description section of this data sheet.
Table 7. EDMA Parameter RAM†
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0000 − 01A0 0017 −Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event
01A0 0018 − 01A0 002F −Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event
01A0 0030 − 01A0 0047 −Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event
01A0 0048 − 01A0 005F −Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event
01A0 0060 − 01A0 0077 −Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event
01A0 0078 − 01A0 008F −Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event
01A0 0090 − 01A0 00A7 −Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event
01A0 00A8 − 01A0 00BF −Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event
01A0 00C0 − 01A0 00D7 −Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event
01A0 00D8 − 01A0 00EF −Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event
01A0 00F0 − 01A0 00107 −Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event
01A0 0108 − 01A0 011F −Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event
01A0 0120 − 01A0 0137 −Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event
01A0 0138 − 01A0 014F −Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event
01A0 0150 − 01A0 0167 −Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event
01A0 0168 − 01A0 017F −Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event
01A0 0180 − 01A0 0197 −Reload/link parameters for Event 0−15
01A0 0198 − 01A0 01AF −Reload/link parameters for Event 0−15
... ...
01A0 07E0 − 01A0 07F7 −Reload/link parameters for Event 0−15
01A0 07F8 − 01A0 07FF −Scratch pad area (2 words)
†The device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.


   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
14 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443
peripheral register descriptions (continued)
For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2.
31 0 EDMA Parameter
Word 0 EDMA Channel Options Parameter (OPT) OPT
Word 1 EDMA Channel Source Address (SRC) SRC
Word 2 Array/Frame Count (FRMCNT) Element Count (ELECNT) CNT
Word 3 EDMA Channel Destination Address (DST) DST
Word 4 Array/Frame Index (FRMIDX) Element Index (ELEIDX) IDX
Word 5 Element Count Reload (ELERLD) Link Address (LINK) RLD
Figure 2. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event
Table 8. EDMA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0800 − 01A0 FEFC − Reserved
01A0 FF00 ESEL0 EDMA event selector 0
01A0 FF04 ESEL1 EDMA event selector 1
01A0 FF08 − 01A0 FF0B − Reserved
01A0 FF0C ESEL3 EDMA event selector 3
01A0 FF1F − 01A0 FFDC − Reserved
01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPR Channel interrupt pending register
01A0 FFE8 CIER Channel interrupt enable register
01A0 FFEC CCER Channel chain enable register
01A0 FFF0 ER Event register
01A0 FFF4 EER Event enable register
01A0 FFF8 ECR Event clear register
01A0 FFFC ESR Event set register
01A1 0000 − 01A3 FFFF – Reserved
Table 9. Quick DMA (QDMA) and Pseudo Registers†
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0200 0000 QOPT QDMA options parameter register
0200 0004 QSRC QDMA source address register
0200 0008 QCNT QDMA frame count register
0200 000C QDST QDMA destination address register
0200 0010 QIDX QDMA index register
0200 0014 − 0200 001C − Reserved
0200 0020 QSOPT QDMA pseudo options register
0200 0024 QSSRC QDMA pseudo source address register
0200 0028 QSCNT QDMA pseudo frame count register
0200 002C QSDST QDMA pseudo destination address register
0200 0030 QSIDX QDMA pseudo index register
†All the QDMA and Pseudo registers are write-accessible only

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
15
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443
peripheral register descriptions (continued)
Table 10. PLL Controller Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B7 C000 PLLPID Peripheral identification register (PID) [0x00010801 for PLL Controller]
01B7 C004 − 01B7 C0FF − Reserved
01B7 C100 PLLCSR PLL control/status register
01B7 C104 − 01B7 C10F − Reserved
01B7 C110 PLLM PLL multiplier control register
01B7 C114 PLLDIV0 PLL controller divider 0 register
01B7 C118 PLLDIV1 PLL controller divider 1 register
01B7 C11C PLLDIV2 PLL controller divider 2 register
01B7 C120 PLLDIV3 PLL controller divider 3 register
01B7 C124 OSCDIV1 Oscillator divider 1 register
01B7 C128 − 01B7 DFFF − Reserved
Table 11. GPIO Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B0 0000 GPEN GPIO enable register
01B0 0004 GPDIR GPIO direction register
01B0 0008 GPVAL GPIO value register
01B0 000C − Reserved
01B0 0010 GPDH GPIO delta high register
01B0 0014 GPHM GPIO high mask register
01B0 0018 GPDL GPIO delta low register
01B0 001C GPLM GPIO low mask register
01B0 0020 GPGC GPIO global control register
01B0 0024 GPPOL GPIO interrupt polarity register
01B0 0028 − 01B0 3FFF − Reserved
Table 12. HPI Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
−HPID HPI data register Host read/write access only
−HPIA HPI address register Host read/write access only
0188 0000 HPIC HPI control register Both Host/CPU read/write access
0188 0001 − 018B FFFF − Reserved


   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
16 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443
peripheral register descriptions (continued)
Table 13. Timer 0 and Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
TIMER 0 TIMER 1
ACRONYM
REGISTER NAME
COMMENTS
0194 0000 0198 0000 CTLx Timer x control register Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
0194 0004 0198 0004 PRDx Timer x period register Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
0194 0008 0198 0008 CNTx Timer x counter register Contains the current value of
the incrementing counter.
0194 000C − 0197 FFFF 0198 000C − 019B FFFF − Reserved −
Table 14. McBSP0 and McBSP1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER DESCRIPTION
McBSP0 McBSP1
ACRONYM
REGISTER DESCRIPTION
018C 0000 0190 0000 DRRx McBSPx data receive register via Configuration Bus
The CPU and EDMA controller can only read this register;
they cannot write to it.
3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DRRx McBSPx data receive register via Peripheral Data Bus
018C 0004 0190 0004 DXRx McBSPx data transmit register via Configuration Bus
3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DXRx McBSPx data transmit register via Peripheral Data Bus
018C 0008 0190 0008 SPCRx McBSPx serial port control register
018C 000C 0190 000C RCRx McBSPx receive control register
018C 0010 0190 0010 XCRx McBSPx transmit control register
018C 0014 0190 0014 SRGRx McBSPx sample rate generator register
018C 0018 0190 0018 MCRx McBSPx multichannel control register
018C 001C 0190 001C RCERx McBSPx receive channel enable register
018C 0020 0190 0020 XCERx McBSPx transmit channel enable register
018C 0024 0190 0024 PCRx McBSPx pin control register
018C 0028 − 018F FFFF 0190 0028 − 0193 FFFF − Reserved

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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443
signal groups description
HHWIL
HCNTL0
HCNTL1
TRST
EXT_INT7‡
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Data
Register Select
Half-Word
Select
Reset and
Interrupts
Control
HPI
(Host-Port Interface)
16
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
HD[15:0]
NMI
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
EXT_INT6‡
EXT_INT5‡
EXT_INT4‡
RESET
RSV
RSV
RSV
RSV
RSV
Clock/PLL
CLKIN
CLKOUT2†
CLKMODE0
CLKOUT3
EMU2
EMU3
EMU4
EMU5
RSV
PLLHV
•
•
•
†For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin. Default function is CLKOUT2. To use this pin as GPIO, the
GP2EN bit in the GPEN register and the GP2DIR bit in the GPDIR register must be properly configured.
‡For this device, the external interrupts (EXT_INT[7−4]) go through the general-purpose input/output (GPIO) module. When used
as interrupt inputs, the GP[7−4] pins must be configured as inputs (via the GPDIR register) and enabled (via the GPEN register)
in addition to enabling the interrupts in the interrupt enable register (IER).
Figure 3. CPU (DSP Core) and Peripheral Signals

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
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signal groups description (continued)
CE3
ECLKOUT
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1†
CLKS1†
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
ARDY
TOUT0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Address
Byte Enables
32
20
Memory
Control
EMIF
(External Memory Interface)
Timer 1
Receive Receive
Timer 0
Timers
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
ECLKIN
HOLD
HOLDA
BUSREQ
Bus
Arbitration
ARE/SDCAS/SSADS
†For proper device operation, these pins must be externally pulled up with a 10-kΩ resistor.
Figure 4. Peripheral Signals

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443
signal groups description (continued)
General-Purpose Input/Output (GPIO) Port
GP[7](EXT_INT7)
GP[6](EXT_INT6)
GP[5](EXT_INT5)
GP[4](EXT_INT4)
CLKOUT2/GP[2]
GPIO
Figure 4. Peripheral Signals (Continued)

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
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DEVICE CONFIGURATIONS
On this device, bootmode and certain device configurations/peripheral selections are determined at device
reset. Also, other device configurations (e.g., EMIF input clock source) are software-configurable via the device
configurations register (DEVCFG) [address location 0x019C0200] after device reset.
device configurations at device reset
Table 15 describes the C6711D device configuration pins, which are set up via internal or external
pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, HD12) and CLKMODE0 pin. These
configuration pins must be in the desired state until reset is released.
For proper device operation, do not oppose the internal pulldowns/pullups in the HD [14, 13, 11:9, 7, 1, 0] pins
with the external pullups/pulldowns or by driving them at reset.
For more details on these device configuration pins, see the Terminal Functions table of this data sheet.