Texas Instruments TLV320DAC3203 User manual

TLV320DAC3203 Applications
Reference Guide
Literature Number: SLAU434
May 2012

Contents
1 TLV320DAC3203 Overview ................................................................................................. 10
1.1 Description ................................................................................................................. 10
1.2 Typical Circuit Configuration ............................................................................................. 11
2 TLV320DAC3203 Application .............................................................................................. 12
2.1 Terminal Descriptions ..................................................................................................... 12
2.1.1 Digital Pins ........................................................................................................ 12
2.1.2 Analog Pins ........................................................................................................ 12
2.1.3 Multifunction Pins ................................................................................................. 12
2.1.4 Register Settings for Multifunction Pins ....................................................................... 14
2.2 Analog Audio I/O .......................................................................................................... 15
2.2.1 Analog Low Power Bypass ...................................................................................... 15
2.2.2 Headphone Output ............................................................................................... 16
2.3 Digital Microphone Input/Decimation Filter ............................................................................. 21
2.3.1 Digital Microphone Interface .................................................................................... 21
2.3.2 Digital Volume Control ........................................................................................... 22
2.3.3 Digital Microphone Decimation Filtering and Signal Processing Overview ............................... 22
2.4 DAC ......................................................................................................................... 35
2.4.1 Processing Blocks – Details ..................................................................................... 36
2.4.2 User Programmable Filters ...................................................................................... 39
2.4.3 Interpolation Filters ............................................................................................... 42
2.4.4 DAC Gain Setting ................................................................................................. 44
2.4.5 DAC Special Functions .......................................................................................... 47
2.4.6 DAC Setup ........................................................................................................ 48
2.5 PowerTune ................................................................................................................. 49
2.5.1 PowerTune Modes ............................................................................................... 49
2.5.2 DAC Power Consumption ....................................................................................... 51
2.6 Audio Digital I/O Interface ................................................................................................ 56
2.6.1 Right Justified Mode ............................................................................................. 57
2.6.2 Left Justified Mode ............................................................................................... 58
2.6.3 I2S Mode ........................................................................................................... 59
2.6.4 DSP Mode ......................................................................................................... 60
2.6.5 Secondary I2S..................................................................................................... 61
2.7 Clock Generation and PLL ............................................................................................... 62
2.7.1 PLL ................................................................................................................. 65
2.8 Control Interfaces .......................................................................................................... 66
2.8.1 I2C Control Mode ................................................................................................. 66
2.8.2 SPI Digital Interface .............................................................................................. 68
2.9 Power Supply .............................................................................................................. 69
2.9.1 System Level Considerations ................................................................................... 69
2.10 Reference Voltage ......................................................................................................... 70
2.11 Device Special Functions ................................................................................................. 71
2.11.1 Interrupts ......................................................................................................... 71
3 Device Initialization ............................................................................................................ 72
3.1 Reset ........................................................................................................................ 73
3.2 Device Startup Lockout Times ........................................................................................... 73
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3.3 Analog and Reference Startup .......................................................................................... 73
3.4 PLL Startup ................................................................................................................. 73
3.5 Setting Device Common Mode Voltage ................................................................................ 73
4 Example Setups ................................................................................................................ 74
4.1 Stereo DAC Playback with 48ksps Sample Rate and High Performance. ......................................... 74
4.2 Stereo DAC Playback with 48ksps Sample Rate and Low Power Mode .......................................... 75
4.3 DAC Playback with 48ksps Sample Rate through Class-D Headphone Amplifiers .............................. 75
4.4 ADC Record through Digital Microphone with 44.1ksps Sample Rate ............................................. 77
4.5 Register Script for Mono DAC playback with 48ksps on Differential Headphone with Offset Calibration ..... 77
5 Register Map ..................................................................................................................... 79
5.1 Register Map Summary ................................................................................................... 79
5.2 Page 0 Registers .......................................................................................................... 79
5.2.1 Page 0 / Register 0: Page Select Register - 0x00 / 0x00 ............................................... 79
5.2.2 Page 0 / Register 1: Software Reset Register - 0x00 / 0x01 ............................................ 79
5.2.3 Page 0 / Register 2: Reserved Register - 0x00 / 0x02 .................................................. 79
5.2.4 Page 0 / Register 3: Reserved Register - 0x00 / 0x03 .................................................. 80
5.2.5 Page 0 / Register 4: Clock Setting Register 1, Multiplexers - 0x00 / 0x04 ............................ 80
5.2.6 Page 0 / Register 5: Clock Setting Register 2, PLL P&R Values - 0x00 / 0x05 ...................... 80
5.2.7 Page 0 / Register 6: Clock Setting Register 3, PLL J Values - 0x00 / 0x06 .......................... 80
5.2.8 Page 0 / Register 7: Clock Setting Register 4, PLL D Values (MSB) - 0x00 / 0x07 ................. 80
5.2.9 Page 0 / Register 8: Clock Setting Register 5, PLL D Values (LSB) - 0x00 / 0x08 .................. 81
5.2.10 Page 0 / Register 9-10: Reserved Register - 0x00 / 0x09-0x0A ........................................ 81
5.2.11 Page 0 / Register 11: Clock Setting Register 6, NDAC Values - 0x00 / 0x0B ........................ 81
5.2.12 Page 0 / Register 12: Clock Setting Register 7, MDAC Values - 0x00 / 0x0C ....................... 81
5.2.13 Page 0 / Register 13: DAC OSR Setting Register 1, MSB Value - 0x00 / 0x0D ..................... 82
5.2.14 Page 0 / Register 14: DAC OSR Setting Register 2, LSB Value - 0x00 / 0x0E ...................... 82
5.2.15 Page 0 / Register 15: Reserved Register - 0x00 / 0x0F ................................................. 82
5.2.16 Page 0 / Register 16: Reserved Register - 0x00 / 0x10 ................................................. 82
5.2.17 Page 0 / Register 17: Reserved Register - 0x00 / 0x11 ................................................. 82
5.2.18 Page 0 / Register 18: Reserved Register - 0x00 / 0x12 ................................................. 82
5.2.19 Page 0 / Register 19: Reserved Register - 0x00 / 0x13 ................................................. 82
5.2.20 Page 0 / Register 20: ADC Oversampling (AOSR) Register - 0x00 / 0x14 ........................... 83
5.2.21 Page 0 / Register 21: Reserved Register - 0x00 / 0x15 ................................................. 83
5.2.22 Page 0 / Register 22: Reserved Register - 0x00 / 0x16 ................................................. 83
5.2.23 Page 0 / Register 23: Reserved Register - 0x00 / 0x17 ................................................. 83
5.2.24 Page 0 / Register 24: Reserved Register - 0x00 / 0x18 ................................................. 83
5.2.25 Page 0 / Register 25: Clock Setting Register 8, Multiplexers - 0x00 / 0x19 .......................... 83
5.2.26 Page 0 / Register 26: Clock Setting Register 9, CLKOUT M divider value - 0x00 / 0x1A .......... 83
5.2.27 Page 0 / Register 27: Audio Interface Setting Register 1 - 0x00 / 0x1B ............................... 84
5.2.28 Page 0 / Register 28: Audio Interface Setting Register 2, Data offset setting - 0x00 / 0x1C ....... 84
5.2.29 Page 0 / Register 29: Audio Interface Setting Register 3 - 0x00 / 0x1D .............................. 84
5.2.30 Page 0 / Register 30: Clock Setting Register 10, BCLK N Divider - 0x00 / 0x1E .................... 84
5.2.31 Page 0 / Register 31: Audio Interface Setting Register 4, Secondary Audio Interface - 0x00 / 0x1F
................................................................................................................... 85
5.2.32 Page 0 / Register 32: Audio Interface Setting Register 5 - 0x00 / 0x20 ............................... 85
5.2.33 Page 0 / Register 33: Audio Interface Setting Register 6 - 0x00 / 0x21 ............................... 85
5.2.34 Page 0 / Register 34: Digital Interface Misc. Setting Register - 0x00 / 0x22 ......................... 86
5.2.35 Page 0 / Register 35-36: Reserved Register - 0x00 / 0x23-0x24 ...................................... 86
5.2.36 Page 0 / Register 37: DAC Flag Register 1 - 0x00 / 0x25 .............................................. 86
5.2.37 Page 0 / Register 38: DAC Flag Register 2 - 0x00 / 0x26 .............................................. 86
5.2.38 Page 0 / Register 39-41: Reserved Register - 0x00 / 0x27-0x29 ...................................... 87
5.2.39 Page 0 / Register 42: Sticky Flag Register 1 - 0x00 / 0x2A ............................................. 87
5.2.40 Page 0 / Register 43: Interrupt Flag Register 1 - 0x00 / 0x2B .......................................... 87
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5.2.41 Page 0 / Register 44: Sticky Flag Register 2 - 0x00 / 0x2C ............................................. 87
5.2.42 Page 0 / Register 45: Reserved Register - 0x00 / 0x2D ................................................. 88
5.2.43 Page 0 / Register 46: Interrupt Flag Register 2 - 0x00 / 0x2E .......................................... 88
5.2.44 Page 0 / Register 47: Reserved Register - 0x00 / 0x2F ................................................. 88
5.2.45 Page 0 / Register 48: INT1 Interrupt Control Register - 0x00 / 0x30 .................................. 88
5.2.46 Page 0 / Register 49: INT2 Interrupt Control Register - 0x00 / 0x31 .................................. 89
5.2.47 Page 0 / Register 50-51: Reserved Register - 0x00 / 0x32-0x33 ...................................... 89
5.2.48 Page 0 / Register 52: GPIO/MFP5 Control Register (** Availble only for WCSP Package) - 0x00 /
0x34 ............................................................................................................. 89
5.2.49 Page 0 / Register 53: MFP2 Function Control Register - 0x00 / 0x35 ................................. 90
5.2.50 Page 0 / Register 54: DIN/MFP1 Function Control Register - 0x00 / 0x36 ........................... 90
5.2.51 Page 0 / Register 55: MISO/MFP4 Function Control Register - 0x00 / 0x37 ......................... 90
5.2.52 Page 0 / Register 56: SCLK/MFP3 Function Control Register - 0x00 / 0x38 ......................... 91
5.2.53 Page 0 / Register 57-59: Reserved Registers - 0x00 / 0x39-0x3B ..................................... 91
5.2.54 Page 0 / Register 60: DAC Signal Processing Block Control Register - 0x00 / 0x3C ............... 91
5.2.55 Page 0 / Register 61: Reserved Register - 0x00 / 0x3D ................................................. 91
5.2.56 Page 0 / Register 62: Reserved Register - 0x00 / 0x3E ................................................. 92
5.2.57 Page 0 / Register 63: DAC Channel Setup Register 1 - 0x00 / 0x3F .................................. 92
5.2.58 Page 0 / Register 64: DAC Channel Setup Register 2 - 0x00 / 0x40 .................................. 92
5.2.59 Page 0 / Register 65: Left DAC Channel Digital Volume Control Register - 0x00 / 0x41 ........... 93
5.2.60 Page 0 / Register 66: Right DAC Channel Digital Volume Control Register - 0x00 / 0x42 ......... 93
5.2.61 Page 0 / Register 67: Headset Detection Configuration Register - 0x00 / 0x43 ..................... 93
5.2.62 Page 0 / Register 68: DRC Control Register 1 - 0x00 / 0x44 ........................................... 94
5.2.63 Page 0 / Register 69: DRC Control Register 2 - 0x00 / 0x45 ........................................... 94
5.2.64 Page 0 / Register 70: DRC Control Register 3 - 0x00 / 0x46 ........................................... 94
5.2.65 Page 0 / Register 71: Beep Generator Register 1 - 0x00 / 0x47 ....................................... 95
5.2.66 Page 0 / Register 72: Beep Generator Register 2 - 0x00 / 0x48 ....................................... 95
5.2.67 Page 0 / Register 73: Beep Generator Register 3 - 0x00 / 0x49 ....................................... 95
5.2.68 Page 0 / Register 74: Beep Generator Register 4 - 0x00 / 0x4A ....................................... 95
5.2.69 Page 0 / Register 75: Beep Generator Register 5 - 0x00 / 0x4B ....................................... 95
5.2.70 Page 0 / Register 76: Beep Generator Register 6 - 0x00 / 0x4C ....................................... 96
5.2.71 Page 0 / Register 77: Beep Generator Register 7 - 0x00 / 0x4D ....................................... 96
5.2.72 Page 0 / Register 78: Beep Generator Register 8 - 0x00 / 0x4E ....................................... 96
5.2.73 Page 0 / Register 79: Beep Generator Register 9 - 0x00 / 0x4F ....................................... 96
5.2.74 Page 0 / Register 80: Reserved Register - 0x00 / 0x50 ................................................. 96
5.2.75 Page 0 / Register 82: Reserved Register - 0x00 / 0x52 ................................................. 97
5.2.76 Page 0 / Register 83: Left ADC Channel Volume Control Register - 0x00 / 0x53 ................... 97
5.2.77 Page 0 / Register 84: Right ADC Channel Volume Control Register - 0x00 / 0x54 ................. 97
5.2.78 Page 0 / Register 85: ADC Phase Adjust Register - 0x00 / 0x55 ...................................... 98
5.2.79 Page 0 / Register 80-127: Reserved Register - 0x00 / 0x50-0x7F ..................................... 98
5.3 Page 1 Registers .......................................................................................................... 98
5.3.1 Page 1 / Register 0: Page Select Register - 0x01 / 0x00 ............................................... 98
5.3.2 Page 1 / Register 1: Power Configuration Register - 0x01 / 0x01 ...................................... 98
5.3.3 Page 1 / Register 2: LDO Control Register - 0x01 / 0x02 ............................................... 98
5.3.4 Page 1 / Register 3: Playback Configuration Register 1 - 0x01 / 0x03 ................................ 99
5.3.5 Page 1 / Register 4: Playback Configuration Register 2 - 0x01 / 0x04 ................................ 99
5.3.6 Page 1 / Register 5-8: Reserved Register - 0x01 / 0x05-0x08 ......................................... 99
5.3.7 Page 1 / Register 9: Output Driver Power Control Register - 0x01 / 0x09 ............................ 99
5.3.8 Page 1 / Register 10: Common Mode Control Register - 0x01 / 0x0A ................................ 99
5.3.9 Page 1 / Register 11: Over Current Protection Configuration Register - 0x01 / 0x0B ............. 100
5.3.10 Page 1 / Register 12: HPL Routing Selection Register - 0x01 / 0x0C ............................... 100
5.3.11 Page 1 / Register 13: HPR Routing Selection Register - 0x01 / 0x0D ............................... 100
5.3.12 Page 1 / Register 14-15: Reserved Register - 0x01 / 0x0E-0x0F .................................... 100
5.3.13 Page 1 / Register 16: HPL Driver Gain Setting Register - 0x01 / 0x10 .............................. 100
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5.3.14 Page 1 / Register 17: HPR Driver Gain Setting Register - 0x01 / 0x11 .............................. 101
5.3.15 Page 1 / Register 18-19: Reserved Register - 0x01 / 0x12-0x13 ..................................... 101
5.3.16 Page 1 / Register 20: Headphone Driver Startup Control Register - 0x01 / 0x14 .................. 101
5.3.17 Page 1 / Register 21: Reserved Register - 0x01 / 0x15 ............................................... 102
5.3.18 Page 1 / Register 22: INL to HPL Volume Control Register - 0x01 / 0x16 .......................... 102
5.3.19 Page 1 / Register 23: INR to HPR Volume Control Register - 0x01 / 0x17 ......................... 104
5.3.20 Page 1 / Register 24-50: Reserved Register - 0x01 / 0x18-0x32 ..................................... 106
5.3.21 Page 1 / Register 51: MICBIAS Configuration Register - 0x01 / 0x33 ............................... 106
5.3.22 Page 1 / Register 52-57: Reserved Register - 0x01 / 0x34-0x39 ..................................... 107
5.3.23 Page 1 / Register 58: Analog Input Settings - 0x01 / 0x3A ............................................ 107
5.3.24 Page 1 / Register 59-62: Reserved Register - 0x01 / 0x3B-0x3E .................................... 107
5.3.25 Page 1 / Register 63: DAC Analog Gain Control Flag Register - 0x01 / 0x3F ...................... 107
5.3.26 Page 1 / Register 64-70: Reserved Register - 0x01 / 0x40-0x46 ..................................... 107
5.3.27 Page 1 / Register 71: Analog Input Quick Charging Configuration Register - 0x01 / 0x47 ........ 108
5.3.28 Page 1 / Register 72-122: Reserved Register - 0x01 / 0x48-0x7A ................................... 108
5.3.29 Page 1 / Register 123: Reference Power-up Configuration Register - 0x01 / 0x7B ................ 108
5.3.30 Page 1 / Register 124: Reserved Register - 0x01 / 0x7C .............................................. 108
5.3.31 Page 1 / Register 125: Offset Callibration Register - 0x01 / 0x7D .................................... 108
5.3.32 Page 1 / Register 126-127: Reserved Register - 0x01 / 0x7E-0x7F ................................. 108
5.4 Page 8 Registers ......................................................................................................... 109
5.4.1 Page 8 / Register 0: Page Select Register - 0x08 / 0x00 .............................................. 109
5.4.2 Page 8 / Register 1: ADC Adaptive Filter Configuration Register - 0x08 / 0x01 .................... 109
5.4.3 Page 8 / Register 2-7: Reserved - 0x08 / 0x02-0x07 ................................................... 109
5.4.4 Page 8 / Register 8-127: ADC Coefficients Buffer-A C(0:29) - 0x08 / 0x08-0x7F .................. 109
5.5 Page 9 Registers ......................................................................................................... 109
5.5.1 Page 9 / Register 0: Page Select Register - 0x09 / 0x00 .............................................. 109
5.5.2 Page 9 / Register 1-7: Reserved - 0x09 / 0x01-0x07 ................................................... 109
5.5.3 Page 9 / Register 8-15: ADC Coefficients Buffer-A C(30:31) - 0x09 / 0x08-0x0F .................. 110
5.5.4 Page 9 / Register 16-31: Reserved - 0x09 / 0x10-0x1F ................................................ 110
5.5.5 Page 9 / Register 32-127: ADC Coefficients Buffer-A C(36:59) - 0x09 / 0x20-0x7F ............... 110
5.6 Page 10 Registers ....................................................................................................... 110
5.6.1 Page 10 / Register 0: Page Select Register - 0x0A / 0x00 ............................................ 110
5.6.2 Page 10 / Register 1-7: Reserved - 0x0A / 0x01-0x07 ................................................. 110
5.6.3 Page 10 / Register 8-23: ADC Coefficients Buffer-A C(60:63) - 0x0A / 0x08-0x17 ................ 110
5.6.4 Page 10 / Register 24-127: Reserved - 0x0A / 0x18-0x7F ............................................ 110
5.7 Page 26 Registers ....................................................................................................... 110
5.7.1 Page 26 / Register 0: Page Select Register - 0x1A / 0x00 ............................................ 110
5.7.2 Page 26 / Register 1-7: Reserved. - 0x1A / 0x01-0x07 ................................................ 111
5.7.3 Page 26 / Register 8-127: ADC Coefficients Buffer-B C(0:29) - 0x1A / 0x08-0x7F ................ 111
5.8 Page 27 Registers ....................................................................................................... 111
5.8.1 Page 27 / Register 0: Page Select Register - 0x1B / 0x00 ............................................ 111
5.8.2 Page 27 / Register 1-7: Reserved. - 0x1B / 0x01-0x07 ................................................ 111
5.8.3 Page 27 / Register 8-15: ADC Coefficients Buffer-B C(30:31) - 0x1B / 0x08-0x0F ................ 111
5.8.4 Page 27 / Register 16-31: Reserved. - 0x1B / 0x10-0x1F ............................................. 111
5.8.5 Page 27 / Register 32-127: ADC Coefficients Buffer-B C(36:59) - 0x1B / 0x20-0x7F ............. 111
5.9 Page 28 Registers ....................................................................................................... 111
5.9.1 Page 28 / Register 0: Page Select Register - 0x1C / 0x00 ............................................ 111
5.9.2 Page 28 / Register 1-7: Reserved. - 0x1C / 0x01-0x07 ................................................ 112
5.9.3 Page 28 / Register 8-23: ADC Coefficients Buffer-B C(60:63) - 0x1C / 0x08-0x17 ................ 112
5.9.4 Page 28 / Register 24-127: Reserved. - 0x1C / 0x18-0x7F ........................................... 112
5.10 Page 44 Registers ....................................................................................................... 112
5.10.1 Page 44 / Register 0: Page Select Register - 0x2C / 0x00 ............................................ 112
5.10.2 Page 44 / Register 1: DAC Adaptive Filter Configuration Register - 0x2C / 0x01 .................. 112
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5.10.3 Page 44 / Register 2-7: Reserved - 0x2C / 0x02-0x07 ................................................. 112
5.10.4 Page 44 / Register 8-11: DAC Coefficients Buffer-A C(0:29) - 0x2C / 0x08-0x0B ................. 112
5.11 Page 45 Registers ....................................................................................................... 113
5.11.1 Page 45 / Register 0: Page Select Register - 0x2D / 0x00 ............................................ 113
5.11.2 Page 45 / Register 1-7: Reserved - 0x2D / 0x01-0x07 ................................................. 113
5.11.3 Page 45 / Register 8-11: DAC Coefficients Buffer-A C(30) - 0x2D / 0x08-0x0B .................... 113
5.11.4 Page 45 / Register 12-15: Reserved - 0x2D / 0x0C-0x0F ............................................. 113
5.11.5 Page 45 / Register 16-127: DAC Coefficients Buffer-A C(32:59) - 0x2D / 0x10-0x7F ............. 113
5.12 Page 46 Registers ....................................................................................................... 113
5.12.1 Page 46 / Register 0: Page Select Register - 0x2E / 0x00 ............................................ 113
5.12.2 Page 46 / Register 1-7: Reserved - 0x2E / 0x01-0x07 ................................................. 113
5.12.3 Page 46 / Register 8-19: DAC Coefficients Buffer-A C(60:62) - 0x2E / 0x08-0x13 ................ 113
5.12.4 Page 46 / Register 20-27: Reserved - 0x2E / 0x14-0x1B .............................................. 114
5.12.5 Page 46 / Register 28-75: DAC Coefficients Buffer-A C(65:76) - 0x2E / 0x1C-0x4B .............. 114
5.12.6 Page 46 / Register 76-127: Reserved - 0x2E / 0x4C-0x7F ............................................ 114
5.13 Page 62 Registers ....................................................................................................... 114
5.13.1 Page 62 / Register 0: Page Select Register - 0x3E / 0x00 ............................................ 114
5.13.2 Page 62 / Register 1-7: Reserved. - 0x3E / 0x01-0x07 ................................................ 114
5.13.3 Page 62 / Register 8-127: DAC Coefficients Buffer-B C(0:29) - 0x3E / 0x08-0x7F ................ 114
5.14 Page 63 Registers ....................................................................................................... 114
5.14.1 Page 63 / Register 0: Page Select Register - 0x3F / 0x00 ............................................ 114
5.14.2 Page 63 / Register 1-7: Reserved. - 0x3F / 0x01-0x07 ................................................ 114
5.14.3 Page 63 / Register 8-11: DAC Coefficients Buffer-B C(30) - 0x3F / 0x08-0x0B .................... 115
5.14.4 Page 63 / Register 12-15: Reserved. - 0x3F / 0x0C-0x0F ............................................. 115
5.14.5 Page 63 / Register 16-127: DAC Coefficients Buffer-B C(32:59) - 0x3F / 0x10-0x7F ............. 115
5.15 Page 63 Registers ....................................................................................................... 115
5.15.1 Page 63 / Register 0: Page Select Register - 0x3F / 0x00 ............................................ 115
5.15.2 Page 63 / Register 1-7: Reserved - 0x3F / 0x01-0x07 ................................................. 115
5.15.3 Page 63 / Register 8-19: DAC Coefficients Buffer-B C(60:62) - 0x3F / 0x08-0x13 ................ 115
5.15.4 Page 63 / Register 20-27: Reserved - 0x3F / 0x14-0x1B .............................................. 115
5.15.5 Page 63 / Register 28-75: DAC Coefficients Buffer-B C(65:76) - 0x3F / 0x1C-0x4B .............. 115
5.15.6 Page 63 / Register 76-127: Reserved - 0x3F / 0x4C-0x7F ............................................ 116
5.16 ADC Coefficients A+B ................................................................................................... 116
5.17 ADC Coefficient Default Values ........................................................................................ 116
5.18 DAC Coefficients A+B ................................................................................................... 117
5.19 DAC Coefficient Default Values ........................................................................................ 118
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List of Figures
1-1. Simplified Block Diagram................................................................................................. 10
1-2. Typical Circuit Configuration ............................................................................................. 11
2-1. Low Power Analog Bypass............................................................................................... 16
2-2. Stereo Headphone Configuration ....................................................................................... 16
2-3. Conceptual Circuit for Pop-Free Power-up ............................................................................ 17
2-4. Low Power Mono DAC to Differential Headphone.................................................................... 19
2-5. Configuration for Using Headphone Amplifier in Class-D Mode .................................................... 20
2-6. Digital Microphone in TLV320DAC3203 ............................................................................... 21
2-7. Timing Diagram for Digital Microphone Interface ..................................................................... 22
2-8. Signal Chain for PRB_R1 and PRB_R4................................................................................ 24
2-9. Signal Chain PRB_R2 and PRB_R5.................................................................................... 24
2-10. Signal Chain for PRB_R3 and PRB_R6................................................................................ 24
2-11. Signal Chain for PRB_R7 and PRB_R10 .............................................................................. 24
2-12. Signal Chain for PRB_R8 and PRB_R11 .............................................................................. 25
2-13. Signal Chain for PRB_R9 and PRB_R12 .............................................................................. 25
2-14. Signal Chain for PRB_R13 and PRB_R16............................................................................. 25
2-15. Signal Chain for PRB_R14 and PRB_R17............................................................................. 25
2-16. Signal for PRB_R15 and PRB_R18..................................................................................... 26
2-17. Decimation Filter A, Frequency Response............................................................................ 30
2-18. Decimation Filter B, Frequency Response............................................................................. 31
2-19. Decimation Filter C, Frequency Response............................................................................. 32
2-20. Signal Chain for PRB_P1 and PRB_P4................................................................................ 36
2-21. Signal Chain for PRB_P2, PRB_P5, PRB_P10 and PRB_P15 ..................................................... 37
2-22. Signal Chain for PRB_P3, PRB_P6, PRB_P11 and PRB_P16 ..................................................... 37
2-23. Signal Chain for PRB_P7, PRB_P12, PRB_P17 and PRB_P20.................................................... 37
2-24. Signal Chain for PRB_P8 and PRB_P13............................................................................... 37
2-25. Signal Chain for PRB_P9 and PRB_P14............................................................................... 37
2-26. Signal Chain for PRB_P18 and PRB_P21............................................................................. 38
2-27. Signal Chain for PRB_P19 and PRB_P22............................................................................. 38
2-28. Signal Chain for PRB_P23............................................................................................... 38
2-29. Signal Chain for PRB_P24............................................................................................... 39
2-30. Signal Chain for PRB_P25............................................................................................... 39
2-31. DAC Interpolation Filter A, Frequency Response..................................................................... 42
2-32. Channel Interpolation Filter B, Frequency Response................................................................. 43
2-33. DAC Interpolation Filter C, Frequency Response .................................................................... 43
2-34. Timing Diagram for Right-Justified Mode .............................................................................. 57
2-35. Timing Diagram for Left-Justified Mode ................................................................................ 58
2-36. Timing Diagram for Left-Justified Mode with Offset=1................................................................ 58
2-37. Timing Diagram for Left-Justified Mode with Offset=0 and inverted bit clock ..................................... 58
2-38. Timing Diagram for I2S Mode ............................................................................................ 59
2-39. Timing Diagram for I2S Mode with offset=2............................................................................ 59
2-40. Timing Diagram for I2S Mode with offset=0 and bit clock invert..................................................... 59
2-41. Timing Diagram for DSP Mode.......................................................................................... 60
2-42. Timing Diagram for DSP Mode with offset = 1 ........................................................................ 60
2-43. Timing Diagram for DSP Mode with offset = 0 and bit clock inverted.............................................. 60
2-44. Audio Serial Interface Multiplexing...................................................................................... 61
2-45. Clock Distribution Tree.................................................................................................... 62
7
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2-46. BCLK Output Options..................................................................................................... 63
2-47. General Purpose Clock Output Options................................................................................ 64
2-48. I2C Write .................................................................................................................... 67
2-49. I2C Read .................................................................................................................... 67
2-50. SPI Timing Diagram for Register Write................................................................................. 68
2-51. SPI Timing Diagram for Register Read................................................................................. 69
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List of Tables
2-1. Multifunction Pin Assignments........................................................................................... 12
2-2. Multifunction Pin Register Configuration ............................................................................... 14
2-3. Rpop Values ................................................................................................................. 17
2-4. Digital Volume Control for ADC.......................................................................................... 22
2-5. Processing Blocks......................................................................................................... 23
2-6. First-Order IIR Filter Coefficients........................................................................................ 27
2-7. Biquad Filter Coefficients................................................................................................. 28
2-8. FIR Filter Coefficients..................................................................................................... 29
2-9. Decimation Filter A, Specification ....................................................................................... 30
2-10. Decimation Filter B, Specifications ..................................................................................... 31
2-11. Decimation Filter C, Specifications ..................................................................................... 32
2-12. MICBIAS Voltage Control ................................................................................................ 33
2-13. Overview – DAC Predefined Processing Blocks ..................................................................... 36
2-14. DAC IIR Filter Coefficients ............................................................................................... 40
2-15. DAC Biquad Filter Coefficients .......................................................................................... 40
2-16. DAC Interpolation Filter A, Specification ............................................................................... 42
2-17. DAC Interpolation Filter B, Specification ............................................................................... 42
2-18. DAC Interpolation Filter C, Specification ............................................................................... 43
2-19. DRC HPF and LPF Coefficients......................................................................................... 44
2-20. CODEC CLKIN Clock Dividers .......................................................................................... 63
2-21. Maximum TLV320DAC3203 Clock Frequencies ...................................................................... 64
2-22. PLL_CLK Frequency Range............................................................................................. 65
2-23. PLL Example Configurations............................................................................................. 66
2-24. SPI Command Word ...................................................................................................... 68
3-1. Input Common Mode voltage and Input Signal Swing................................................................ 73
5-1. Summary of Register Map ............................................................................................... 79
5-2. ADC Coefficient Buffer-A Map ......................................................................................... 116
5-3. ADC Coefficient Buffer-B Map ......................................................................................... 116
5-4. Default values of ADC Coefficients in Buffers A and B............................................................. 116
5-5. DAC Coefficient Buffer-A Map ......................................................................................... 117
5-6. DAC Coefficient Buffer-B Map ......................................................................................... 117
5-7. Default values of DAC Coefficients in Buffers A and B............................................................. 118
9
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Micbias
Supplies
SCL/SSZ SDA/MOSI MCLK DOUT/MFP2 DIN/MFP1 BCLK WCLK GPIO (WCSP Only)
Ref
Data Interface
Dig Mic
Interface
Chapter 1
SLAU434–May 2012
TLV320DAC3203 Overview
1.1 Description
Features Applications
• Stereo Audio DAC with 100dB SNR • Headsets
• 4.1mW Stereo 48ksps Playback • Handset Accessories
• PowerTune™ • Communication
• Extensive Signal Processing Options • Portable Computing
• Stereo Digital Microphone Input –
• Stereo Headphone Outputs •Chapter 1: Device Overview
• Low Power Analog Bypass Mode •Chapter 2: TLV320DAC3203 Application
• Programmable PLL •Chapter 3: Device Initialization
• Integrated LDO •Chapter 4: Example Setups
• 4mm × 4mm QFN and 2.7mm × 2.7mm •Chapter 5: Register Map and Descriptions
WCSPPackage
The TLV320DAC3203 (sometimes referred to as the DAC3203) is a flexible, low-power, low-voltage
stereo audio codec with programmable outputs, PowerTune capabilities, fixed predefined and
parameterizable signal processing blocks, integrated PLL, integrated LDO and flexible digital interfaces.
Extensive register-based control of power, input/output channel configuration, gains, effects, pin-
multiplexing and clocks is included, allowing the device to be precisely targeted to its application.
Figure 1-1. Simplified Block Diagram
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www.ti.com Typical Circuit Configuration
Combined with the advanced PowerTune technology, the device can cover operations from 8kHz mono
voice playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and
telephony applications.
The record path of the TLV320DAC3203 consists of a stereo digital microphone PDM interface (not
available when using SPI control interface) typically used at 64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects, true differential output signal,
flexible mixing of DAC and analog input signals as well as programmable volume controls. The
TLV320DAC3203 contains two high-power output drivers which can be configured in multiple ways,
including stereo, and mono BTL. The integrated PowerTune technology allows the device to be tuned to
just the right power-performance trade-off. Mobile applications frequently have multiple use cases
requiring very low-power operation while being used in a mobile environment. When used in a docked
environment power consumption typically is less of a concern while lowest possible noise is important.
With PowerTune the TLV320DAC3203 can address both cases.
The voltage supply range for the TLV320DAC3203 for analog is 1.5V–1.95V, and for digital it is
1.26V–1.95V. To ease system-level design, a low-dropout regulator (LDO) is integrated to generate the
appropriate analog supply from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are
supported in the range of 1.1V–3.6V.
The required internal clock of the TLV320DAC3203 can be derived from multiple sources, including the
MCLK, BCLK or GPIO pins or the output of the internal PLL, where the input to the PLL again can be
derived from the MCLK, BCLK or GPIO pins. Although using the internal, fractional PLL ensures the
availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is
highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.
The device is available in the 4mm × 4mm QFN and 2.7mm × 2.7mm WCSPpackage.
1.2 Typical Circuit Configuration
Figure 1-2. Typical Circuit Configuration
11
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Chapter 2
SLAU434–May 2012
TLV320DAC3203 Application
2.1 Terminal Descriptions
2.1.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins
have a default function, and also can be reprogrammed to cover alternative functions for various
applications.
The fixed-function pins are Reset and the SPI_Select pin, which are HW control pins. Depending on the
state of SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI
protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Section 2.1.3.
2.1.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog
blocks are powered down by default. The blocks can be powered up with fine granularity according to the
application needs.
2.1.3 Multifunction Pins
Table 2-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Table 2-1. Multifunction Pin Assignments
1 2 3 4 5 6 7 8
Pin Function MCLK BCLK WCLK DIN DOUT MFP3/ MFP4/ GPIO
MFP1 MFP2 SCLK MISO MFP5
APLL Input S(1) S(2) E S(3)
BCodec Clock Input S(1) ,D(4) S(2) S(3)
CI2S BCLK input S(2),D
DI2S BCLK output E(5)
EI2S WCLK input E, D
FI2S WCLK output E
GI2S ADC word clock input E E
HI2S ADC WCLK out E E
II2S DIN E, D
JI2S DOUT E, D
KGeneral Purpose Output I E
KGeneral Purpose Output II E
(1) S(1): The MCLK pin can be used to drive the PLL and Codec Clock inputs simultaneously
(2) S(2): The BCLK pin can be used to drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously
(3) S(3): The GPIO/MFP5 pin can be used to drive the PLL and Codec Clock inputs simultaneously
(4) D: Default Function
(5) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if GPIO/MFP5 has
been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)
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Table 2-1. Multifunction Pin Assignments (continued)
1 2 3 4 5 6 7 8
Pin Function MCLK BCLK WCLK DIN DOUT MFP3/ MFP4/ GPIO
MFP1 MFP2 SCLK MISO MFP5
KGeneral Purpose Output III E
LGeneral Purpose Input I E
LGeneral Purpose Input II E
LGeneral Purpose Input III E
MINT1 output E E E
NINT2 output E E E
QSecondary I2S BCLK input E E
RSecondary I2S WCLK in E E
SSecondary I2S DIN E E
TSecondary I2S DOUT E
USecondary I2S BCLK OUT E E E
VSecondary I2S WCLK OUT E E E
XAux Clock Output E E E
13
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2.1.4 Register Settings for Multifunction Pins
To configure the settings seen in Table 2-1, please see the letter/number combination in for the
appropriate registers to modify. In , the letter/number combination represents the row and the column
number from Table 2-1 in bold type.
Please be aware that more settings may be necessary to obtain a full interface definition matching the
application requirement (e.g. register Page 0 / Register 25 to 33).
Table 2-2. Multifunction Pin Register Configuration
Required Register
Description Required Register Setting Description Setting
Page 0 / Register 4, Bits D3- Page 0 / Register 53,Bits
A1 PLL Input on MCLK N5 INT2 output DOUT/MFP2
D2=00 D3-D1=101
Page 0 / Register 4, Bits D3- INT2 output on Page 0 / Register 55, Bits
A2 PLL Input on BCLK N7
D2=01 MISO/MFP4 D4-D1=0101
Page 0 / Register 54, Bits
D2-D1=01 INT2 output on Page 0 / Register 52, Bits
A4 PLL Input on DIN/MFP1 N8
Page 0 / Register 4, Bits D3- GPIO/MFP5 D5-D2=0110
D2=11
Page 0 / Register 52, Bits Page 0 / Register 54, Bits
D5-D2=0001 Digital Microphone Data D2-D1=01
A8 PLL Input on GPIO/MFP5 O4
Page 0 / Register 4, Bits D3- Input on DIN/MFP1 Page 0 / Register 81, Bits
D2=10 D5-D4=10
Page 0 / Register 56, Bits
Codec Clock Input on Page 0 / Register 4, Bits D1- Digital Microphone Data D2-D1=01
B1 O6
MCLK D0=00 Input on SCLK/MFP3 Page 0 / Register 81, Bits
D5-D4=01
Page 0 / Register 52, Bits
Codec Clock Input on Page 0 / Register 4, Bits D1- Digital Microphone Data D5-D2=0001
B2 O8
BCLK D0=01 Input on GPIO/MFP5 Page 0 / Register 81, Bits
D5-D4=00
Page 0 / Register 52, Bits
Codec Clock Input on D5-D2=0001 Digital Microphone Clock Page 0 / Register 55, Bits
B8 P7
GPIO/MPF5 Page 0 / Register 4, Bits D1- Output on MISO/MFP4 D4-D1=0111
D0=10
Page 0 / Register 27, Bit Digital Microphone Clock Page 0 / Register 52, Bits
C2 I2S BCLK input on BCLK P8
D3=0 Output on GPIO/MFP5 D5-D2=1010
Page 0 / Register 56, Bits
Page 0 / Register 27, Bit Secondary I2S BCLK input D2-D1=01
D2 I2S BCLK output on BCLK Q6
D3=1 on SCLK/MFP3 Page 0 / Register 31, Bits
D6-D5=01
Page 0 / Register 52, Bits
Page 0 / Register 27, Bit Secondary I2S BCLK input D5-D2=0001
E3 I2S WCLK input on WCLK Q8
D2=0 on GPIO/MFP5 Page 0 / Register 31, Bits
D6-D5=00
Page 0 / Register 56, Bits
Page 0 / Register 27, Bit Secondary I2S WCLK in on D2-D1=01
F3 I2S WCLK output WCLK R6
D2=1 SCLK/MFP3 Page 0 / Register 31, Bits
D4-D3=01
Page 0 / Register 56, Bits Page 0 / Register 52, Bits
I2S ADC word clock input D2-D1=01 Secondary I2S WCLK in on D5-D2=0001
G6 R8
on SCLK/MFP3 Page 0 / Register 31, Bits GPIO/MFP50 Page 0 / Register 31, Bits
D2-D1=01 D4-D3=0
Page 0 / Register 52, Bits Page 0 / Register 56, Bits
I2S ADC word clock input D5-D2=0001 Secondary I2S DIN on D2-D1=01
G8 S6
on GPIO/MFP5 Page 0 / Register 31, Bits SCLK/MFP3 Page 0 / Register 31, Bit
D2-D1=00 D0=1
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Table 2-2. Multifunction Pin Register Configuration (continued)
Required Register
Description Required Register Setting Description Setting
Page 0 / Register 52, Bits
I2S ADC WCLK out on Page 0 / Register 55, Bits Secondary I2S DIN on D5-D2=0001
H7 S8
MISO/MFP4 D4-D1=0110 GPIO/MFP5 Page 0 / Register 31, Bit
D0=0
I2S ADC WCLK out on Page 0 / Register 52, Bits Secondary I2S DOUT on Page 0 / Register 55, Bits
H8 T7
GPIO/MFP5 D5-D2=0111 MISO/MFP4 D4-D1=1000
Page 0 / Register 54, Bits Secondary I2S BCLK OUT Page 0 / Register 53, Bits
I4 I2S DIN on DIN/MFP1 U5
D2-D1=01 on DOUT/MFP2 D3-D1=110
I2S DOUT on Page 0 / Register 53, Bits Secondary I2S BCLK OUT Page 0 / Register 55, Bits
J5 U7
DOUT/MFP2 D3-D1=001 on MISO/MFP4 D4-D1=1001
General Purpose Out I on Page 0 / Register 53, Bits Secondary I2S BCLK OUT Page 0 / Register 52, Bits
K5 U8
DOUT/MFP2 D3-D1=010 on GPIO/MFP5 D5-D2=1000
General Purpose Out II Page 0 / Register 55, Bits Secondary I2S WCLK OUT Page 0 / Register 53, Bits
K7 V5
on MISO/MFP4 D4-D1=0010 on SCLK/MFP3 D3-D1=111
General Purpose Out III Page 0 / Register 52, Bits Secondary I2S WCLK OUT Page 0 / Register 55, Bits
K8 V7
on GPIO/MFP5 D5-D2=0011 on MISO/MFP4 D4-D1=1010
General Purpose In I on Page 0 / Register 54, Bits Secondary I2S WCLK OUT Page 0 / Register 52, Bits
L4 V8
DIN/MFP1 D2-D1=10 on GPIO/MFP5 D5-D2=1001
Page 0 / Register 56, Bits
General Purpose In II on Page 0 / Register 56, Bits Headset Detect Input on D2-D1=00
L6 W6
SCLK/MFP3 D2-D1=10 SCLK/MFP3 Page 0 / Register 67, Bit
D7=1
General Purpose In III on Page 0 / Register 52, Bits Aux Clock Output on Page 0 / Register 53, Bits
L8 X5
GPIO/MFP5 D5-D2=0010 DOUT/MFP2 D3-D1=011
INT1 output on Page 0 / Register 53, Bits Aux Clock Output on Page 0 / Register 55, Bits
M5 X7
DOUT/MFP2 D3-D1=100 MISO/MFP4 D4-D1=0011
INT1 output on Page 0 / Register 55, Bits Aux Clock Output on Page 0 / Register 52, Bits
M7 X8
MISO/MFP4 D4-D1=0100 GPIO/MFP5 D5-D2=0100
INT1 output on Page 0 / Register 52, Bits
M8 GPIO/MFP5 D5-D2=0101
2.2 Analog Audio I/O
The analog I/O path of the TLV320DAC3203 offers a variety of options for signal conditioning and routing:
• 2 headphone amplifier outputs
• Analog gain setting
• Single ended and differential modes
2.2.1 Analog Low Power Bypass
The TLV320DAC3203 offers an analog-bypass mode. An analog signal can be routed from the analog
input pin to the output amplifier. Neither the digital-input processing blocks nor the DAC resources are
required for such operation; this supports low-power operation during analog-bypass mode.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs INL to
the left headphone amplifier (HPL) and INR to HPR.
15
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HPL
HPR
LEFT
DAC
RIGHT
DAC
LEFT
HEADPHONE
AMP
RIGHT
HEADPHONE
AMP
INL
INR
Page 1 / Register 12
Page 1 / Register 13
D3
D2
D3
D2
Left
DAC +
+
Right
DAC
-6...+29dB
1dB steps
-6...+29dB
1dB steps
HPL
HPR
INL
INR
Analog Audio I/O www.ti.com
Figure 2-1. Low Power Analog Bypass
2.2.2 Headphone Output
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ωin
single-ended AC-coupled headphone configurations, or loads down to 32Ωin differential mode, where a
speaker is connected between HPL and HPR. In single-ended drive configuration these drivers can drive
up to 15mW power into each headphone channel while operating from 1.8V analog supplies. While
running from the AVdd supply, the output common-mode of the headphone driver is set by the common-
mode setting of analog inputs to allow maximum utilization of the analog supply range while
simultaneously providing a higher output-voltage swing. In cases when higher output-voltage swing is
required, the headphone amplifiers can run directly from the higher supply voltage on LDOIN input (up to
3.6V). To use the higher supply voltage for higher output signal swing, the output common-mode can be
adjusted to either 1.25V, 1.5V or 1.65V. When the common-mode voltage is configured at 1.65V and
LDOIN supply is 3.3V, the headphones can each deliver up to 40mW power into a 16Ωload.
The headphone drivers are capable of driving a mixed combination of DAC signal and bypass from analog
input INL and INR. The analog input signals can be attenuated up to 72dB before routing. The level of the
DAC signal can be controlled using the digital volume control of the DAC. To control the output-voltage
swing of headphone drivers, the digital volume control provides a range of –6.0dB to +29.0dB (1) in steps
of 1dB. These level controls are not meant to be used as dynamic volume control, but more to set output
levels during initial device configuration. Refer to for recommendations for using headphone volume
control for achieving 0dB gain through the DAC channel with various configurations.
2.2.2.1 Stereo Single Ended Configuration
Figure 2-2. Stereo Headphone Configuration
(1) If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute.
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cm
popload
load
load V
RR
R
V´
+
=
Rload
Rpop
Cc
Output
Driver
PAD
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The left and right DAC channels are routed to the corresponding left and right headphone amplifier. This
configuration is also used to drive line-level loads.
The TLV320DAC3203 headphone drivers support pop-free operation. Because the HPL and HPR are
high-power drivers, pop can result due to sudden transient changes in the output drivers if care is not
taken. The most critical care is required while using the drivers as stereo single-ended capacitively-
coupled drivers as shown in Figure 2-2. The output drivers achieve pop-free power-up by using slow
power-up modes. Conceptually, the circuit during power-up can be visualized as
Figure 2-3. Conceptual Circuit for Pop-Free Power-up
The value of Rpop can be chosen by setting register Page 1, Register 20, Bits D1-D0).
Table 2-3. Rpop Values
Page 1, Register 20, Bits D1-D0) Rpop Value
00 2 kΩ
01 6 kΩ
10 25 kΩ
To minimize audible artifacts, two parameters can be adjusted to match application requirements. The
voltage Vload across Rload at the beginning of slow charging should not be more than a few mV. At that time
the voltage across Rload can be determined as:
(1)
For a typical Rload of 32Ω, Rpop of 6 kΩor 25 kΩwill deliver good results (see Table 2-3 for register
settings).
According to the conceptual circuit in Figure 2-3, the voltage on PAD will exponentially settle to the output
common-mode voltage based on the value of Rpop and Cc. Thus, the output drivers must be in slow power-
up mode for time T, such that at the end of the slow power-on period, the voltage on Vpad is very close to
the common-mode voltage. The TLV320DAC3203 allows the time T to be adjusted to allow for a wide
range of Rload and Ccby programming Page 1, Register 20, Bits D5-D2). For the time adjustments, the
value of Ccis assumed to be 47μF. N=5 is expected to yield good results.
Page 1, Register 20, Bits D5- Slow Charging Time=N*Time – Constants(for Rpop and 47μF)
D2)
0000 N=0
0001 N=0.5
0010 N=0.625
0011 N=0.75
0100 N=0.875
0101 N=1.0
0110 N=2.0
0111 N=3.0
1000 N=4.0
1001 N=5.0
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Page 1, Register 20, Bits D5- Slow Charging Time=N*Time – Constants(for Rpop and 47μF)
D2)
1010 N=6.0
1011 N=7.0
1100 N=8.0
1101 N=16 (Not valid for Rpop=25kΩ)
1110 N=24 (Not valid for Rpop=25kΩ)
1111 N=32 (Not valid for Rpop=25kΩ)
Again, for example, for Rload=32Ω, Cc=47μF and common mode of 0.9V, the number of time constants
required for pop-free operation is 5 or 6. A higher or lower Ccvalue will require higher or lower value for N.
During the slow-charging period, no signal is routed to the output driver. Therefore, choosing a larger than
necessary value of N results in a delay from power-up to signal at output. At the same time, choosing N to
be smaller than the optimal value results in poor pop performance at power-up.
The signals being routed to headphone drivers (e.g. DAC and IN) often have DC offsets due to less-than-
ideal processing. As a result, when these signals are routed to output drivers, the offset voltage causes a
pop. To improve the pop-performance in such situations, a feature is provided to soft-step the DC-offset.
At the beginning of the signal routing, a high-value attenuation can be applied which can be progressively
reduced in steps until the desired gain in the channel is reached. The time interval between each of these
gain changes can be controlled by programming Page 1, Register 20, Bits D7-D6). This gain soft-stepping
is applied only during the initial routing of the signal to the output driver and not during subsequent gain
changes.
Page 1, Register 20, Bits D7-D6 Soft-stepping Step Time During initial signal routing
00 0 ms (soft-stepping disabled)
01 50ms
10 100ms
11 200ms
It is recommended to use the following sequence for achieving optimal pop performance at power-up:
1. Choose the value of Rpop, N (time constants) and soft-stepping step time for slow power-up.
2. Choose the configuration for output drivers, including common modes and output stage power
connections
3. Select the signals to be routed to headphones.
4. Power-up the blocks driving signals into HPL and HPR, but keep it muted
5. Unmute HPL and HPR and set the desired gain setting.
6. Power-on the HPL and HPR drivers.
7. Unmute the block driving signals to HPL and HPR after the Driver PGA flags are set to indicate
completion of soft-stepping after power-up. These flags can be read from Page 1, Register 63, Bits D7-
D6).
It is important to configure the Headphone Output driver depop control registers before powering up the
headphone; these register contents should not be changed when the headphone drivers are powered up.
Before powering down the HPL and HPR drivers, it is recommended that user read back the flags in Page
1, Register 63. For example. before powering down the HPL driver, ensure that bit D(7) = 1 and bit D(3) =
1 if INL is routed to HPL and bit D(1) = 1 if the Left Mixer is routed to HPL. The output driver should be
powered down only after a steady-state power-up condition has been achieved. This steady state power-
up condition also must be satisfied for changing the HPL/R driver mute control in Page 1, Register 16 and
17, Bits D7), i.e. muting and unmuting should be done after the gain and volume controls associated with
routing to HPL/R finished soft-stepping.
In the differential configuration of HPL and HPR, when no coupling capacitor is used, the slow charging
method for pop-free performance need not be used. In the differential load configuration for HPL and
HPR, it is recommended to not use the output driver MUTE feature, because a pop may result.
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LEFT
DAC
HPL
HPR
LEFT_DACP
LEFT_DACM
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During the power-down state, the headphone outputs are weakly pulled to ground using an approximately
50kΩresistor to ground, to maintain the output voltage on HPL and HPR pins.
2.2.2.2 Mono Differential DAC to Mono Differential Headphone Output
Figure 2-4. Low Power Mono DAC to Differential Headphone
This configuration supports the routing of the two differential outputs of the mono, left channel DAC to the
headphone amplifiers in differential mode (Page 1 / Register 12, D3 =1 and Page 1 / Register 13, D4 =1).
2.2.2.2.1 Offset Correction Scheme for Differential DAC to Differential Headphone Output
The TLV320DAC3203 offers an offset correction scheme which is based on calibration during power up.
This scheme will minimize differences in DC voltage between the HPL and HPR outputs.
The offset calibration happens after the headphones are powered up in differential mode. All other
headphone configurations like signal routings, gain settings and mute removal needs to be configured
before the power up of headphones. Any change in these settings while the headphones are powered up
may result in additional differential offsets and are best avoided.
The offset calibration block has a few programmable parameters which the user needs to control. The
user can either choose to calibrate the offset at each power-up of headphones or do it only for first power
up of headphone after system power up and hardware reset.
Programming Page 1 / Register 125, D(1:0) as “01” would cause the offset to be calibrated for each power
up of headphone. This is particularly useful when some headphone configurations like gain or signal
routings change between power ups.
Programming Page 1 / Register 125, D(1:0) as “10” would cause the offset to be calibrated for only the
first power-up of the headphone amplifiers after hardware reset. The calibration data will be stored in
internal memory until the next hardware reset or until AVDD power is removed. Since offset calibration is
not done every time the headphone amplifiers power up the turn on time is reduced by approximately 3.6
ms for subsequent powerups.
Programming Page 1 / Reg 125, D (1:0) as “00” (default) will disable offset correction block.
While the offset is being calibrated no signal should be applied to the headphone amplifier, i.e. the DAC
should be kept muted and analog bypass routing should be kept at highest attenuation setting of 78dB.
The user can read Page 1 / Regiseter 2, D2 to poll if calibration is completed (D2=”1” -> calibration is
completed).
Please see Section 4.5 for an example setup script enabling offset correction.
2.2.2.3 Headphone Amplifier Class-D Mode
By default the headphone amplifiers in the TLV320DAC3203 work in Class-AB mode. By writing to Page
1, Register 3, Bits D7-D6) for the left headphone amplifier, and Page 1, Register 4, Bits D7-D6) with value
11, the headphone amplifiers enter a Class-D mode of operation.
In this mode a high frequency digital pulse-train representation of the DAC signal is fed to the load
connected to HPL and HPR outputs.
19
SLAU434–May 2012 TLV320DAC3203 Application
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L = 82 HmC = 47 F
Cm
C = 1 FmRload = 32 W
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Because the output signal is a pulse train switching between Power Supply and Ground, the efficiency of
the amplifier is greatly improved. In this mode however, for good noise performance, care should be taken
to keep the analog power supply clean.
For using the Class-D mode of operation, the following clock-divider condition should be met:
MDAC = I × 4, where I = 1, 2, ..., 32
When a direct digital pulse train is driven out as a signal, high frequencies as a function of pulse train
frequency are also present which lead to power waste. To increase the efficiency and reduce power
dissipation in the load due to these high frequencies, an LC filter should be used in series with the output
and the load. The cutoff frequency of the LC filter should be adjusted to allow audio signals below 20kHz
to pass through, but highly attenuate the high-frequency signal content.
Figure 2-5. Configuration for Using Headphone Amplifier in Class-D Mode
For using the headphones in the Class-D mode of operation, the headphones should first be powered up
in default Class-AB mode to charge the AC-coupling capacitor to the set common mode voltage. Once the
headphone amplifiers have been so powered up, the DAC should be routed to headphones and unmuted
before they can be switched to the Class-D mode. After Class D mode has been turned on, the linear,
Class AB mode amplifier must be turned off. For powering down the headphone amplifiers, the DAC
should first be muted.
See Section 4.3 for an example setup script enabling Class-D mode.
20 TLV320DAC3203 Application SLAU434–May 2012
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