Texas Instruments 990 User manual

TEXAS INSTRUMENTS
ImprovingMan'sEffectiveness Through Electronics
~--------"'
Model 990 Computer
ITV /EIA Interface Module
Depot Maintenance Manual
MANUAL NO. 945408-9701
ORIGINAL ISSUE 1 MARCH 1976
REVISED AND REISSUED 1 MAY 1977
INCLUDES
CHANGE 1 ..... 1 DECEMBER 1978
Digital Systems Division

© Texas Instruments Incorporated 1977, 1979
All· Rights Reserved, Printed in U.S.A.
The information and/or drawings set forth in this document and all rights in and to inventions disclosed
herein and patents which might be granted thereon disclosing or employing the materials, methods,
techniques or apparatus described herein, are the exclusive property of Texas Instruments Incorporated.
MANUAL REVISION HISTORY
Model 990 Computer TTY/EIA Interface Module Depot
Maintenance Manual (945408-9701)
Original Issue . . . . . . . . . . . . . . . . . . .1 March 1976
Revised . . . . . . . . . . . . . . . . . . . . . . .1 May 1977 (ECN 419692)
Change 1 .................... 1December1978 (ECN 419640)

PREFACE
This manual provides maintenance instructions for the Texas Instruments TTY/EIA Terminal
Interface Module. The manual also provides theory of operation for the module. The information
in this manual is divided into the following sections:
T
j_.
II.
General Description -This section briefly describes the module, including its operation
and characteristics.
Installation -This section provides instructions for unpacking, inspecting, and installing
the module into a Model 990 Computer mainframe or expansion chassis.
III. Operating Instructions -This section provides programming instructions for the module
and a description of how the software controls the operation of the module.
IV. Theory of Operation -This section contains a detailed block diagram description of the
TTY/EIA Terminal Interface Module, describes the module;s interfaces with the Model
990 Computer and a peripheral device, and provides a discussion of the module's
operation.
V. Maintenance -This section provides troubleshooting and fault isolation procedures for
the module.
Alphabetical Index -The alphabetical index provides an alphabetical listing of key
words and concepts within the manual and locates them for easy reference.
Additional information related to the TTY/EIA Terminal Interface Module may be found in the
following documents.
Title
990 Computer Family Systems Handbook
Model 990 Computer TMS 9990 Microprocessor
Assembly Language Programmer's Guide
Model 990 ComputerProgramming Card
Model 990 Computer 733 ASR/KSR Tenninal Installation
and Operation
Model 990/4 Computer System Hardware Reference
Manual
Model 990/10 Computer System Hardware Reference
Manual
Model 990 Computer Family Maintenance Drawings
Model 990 Computer Diagnostic Handbook
TI Part Number
945250-9701
943441-9701
943440-9701
945259-9701
945251-9701
945417-9701
945421-9701
and
945421-9702
945400-9701
Digital Systems Division

~ __ _,,;,____ ___ _
~ 945408-9701
Paragraph
1.1
1.2
1.2.l
1 '1 ')
.J..,(,,.""'6
1.2.3
1.2.4
1.2.5
1.3
1.4
1.5
2.2
2.3
2.4
3.1
3.2
3.2.l
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
4.1
4.2
4.2.l
4.2.2
4.2.3
4.2.4
4.2.S
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
TABLE OF CONTENTS
Title
SECTION I. GENERAL DESCRIPTION
General .....
Equipment Overview
Transmit Mode
Receive Mode . .
Interrupt Response
Character Format .
Diagnostic Mode . . .
Physical Characteristics .
Electrical Characteristics
Module Address . . .
SECTION II. INSTALLATION
General ...... .
Unpacking ............ .
Inspection and Perparation for Installation
Installation . . . . . . . . . . .
SECTION III. OPERATING INSTRUCTIONS
General ...
Programming
Interrupts
Timing Considerations
Output Operation
Input Operation . . .
Error Detection . . .
Sample Program Sequences
SECTION IV. THEORY OF OPERATION
General .....
Block Diagram Description
4-MHz Oscillator
Buad Rate Clock
Address Decoder
Transmit Shift Gating Logic
Transmit Go Flag
Transmit Shift Clock Generator
Transmit Bit Counter
Transmit Shift Register
Current Loop Interface
Diagnostic Loop Logic
EIA Line Drivers
Status and Interrupt Logic
Receive Shift Clock Generator
Receive Bit Counter
iii
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3
3
3
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6
6
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9
11
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1 A
1 ....
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Paragraph
4.2.15
4.2.16
4.2.17
4.2.18
4.2.19
4.2.20
4.2.21
4.2.22
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
5.1
5.2
5.3
5.4
5.4.l
TABLE OF CONTENTS (Continued)
Receive Go Flag . . . .
TTY/EIA Receive Switch
EIA Line Receivers
Receive Transition Detector
Receive Shift Register
Receive Buffer Register
Multiplexer . . . . .
Timing Error Flag . .
Detailed Interface Discussion
Title
Full Duplex TTY /EIA Module-to-Model 990 Computer Interface
Full Duplex TTY/EIA Module-to-Current Loop Device Interface
Full Duplex TTY/EIA Module-to-EIA Device Interface
Module Operation
Preparation to Transmit
Data Transmission
Interrupts
Data Reception
Testing . . . .
. General . . . . . . .
SECTION V. MAINTENANCE
Maintenance Philosophy
Special Test Equipment
Troubleshooting Procedures
Scoping Loops
LIST OF ILLUSTRATIONS
1-1 TTY/EIA Terminal Interface Module . . . . . . . . . .
1-2 Full Duplex TTY/EIA Interface Module Simplified Block Diagram
1-3 Asynchronous (START/STOP) Data Transmission Formats
2-1 Jumper Socket Locations . . . . . . . . . . . . . . . . . .
3-1 TTY/EIA Terminal Interface Module Addressable Input/Output Lines
3-2 Output Character Transfer
3-3 Input Character Transfer
34 Echo Character Sample Routine
3-5 Output Character String Sample Routine
4-1 TTY/EIA Terminal Interface Module Detailed Functional Block Diagram
4-2 Baud Rate Clock Logic Diagram
4-3 Transmit Shift Register Logic . . . . . . . .
4-4 Receive Go Latch Logic Diagram . . . . . .
4-5 Full Duplex TTY/EIA Module Interface Diagram
4-6 Full Duplex TTY/EIA Module Addressable Input Lines
4-7 Full Duplex TTY/EIA Module Addressable Output Lines
iv
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31
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2
4
8
9
13
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30
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Figure
5-1
5-2
5-3
5-4
5-5
5-6
c "'7
J-/
5-8
Table
1-1
2-1
3-1
3-2
3-3
4-1
4-2
4-3
5-1
5-2
LIST OF ILLUSTRATIONS (Continued)
Titie
Model 990/4 Computer Hot Mock-up System
Model 990/10 Computer Hot Mock-up System
Transmit Go Flag Timing . . .
Transmit Shift Clock Generation
Transmit Bit Counter Signals
Transmit Shift Register Signals
Receive Shift Clock Signals
Receive Bit Counter Signals .
LIST OF TABLES
Title
TTY /EIA Terminal Interface Module Electrical Characteristics
Jumper Schedule
TTY /EIA Terminal Interface Module Output Command Signals
TTY /EIA Terminal Interface Module Input Status Signals
Status Transitions Affecting New Status Flag
DATACLK Baud Rate Selection . . . . . . . .
Active Address Decoder Output for CRUBIT,12-15
Muitipiexer Output for CRUBIT,12-15
Troubleshooting Procedures
Baud Rate Clock Signals
v
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43
43
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44
5
7
10
10
11
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22
27
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41
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SECTION I
GENERAL DESCRIPTION
1.1 GENERAL
The Teletypewriter/Electronic Industries Association (TTY/EIA) Terminal Interface Module (fig-
ure 1-1) provides a communication path from Texas Instruments Series 990 Computers to
peripheral devices that operate from either a current loop interface or an interface that conforms
to EIA Standard RS-232C. The TTY/EIA module can be wired for transmit and receive rates
ranging from 75 to 9600 baud, and character code formats of 10 or 11 bits. Typical devices
which can interface with the computer through this module include Texas Instruments Model
733 ASR or 733/743 KSR Data Terminals, Texas Instruments Model 306 and 588 Line Printers,
and Bell 103 (A or F) or 202 (C or D) data sets, or their equivalents.
1.2 EQUIPMENT OVERVIEW
Figure 1-2 is a simplified diagram of the TTY/EIA module. The module consists of transmit
logic, receive logic, and diagnostic logic. The transmit and receive logic can be exercised
simultaneously to achieve full duplex operation. Module timing is accomplished by a 4-MHz
oscillator and a group of counters that provide a jumper-selected divide network necessary for
generating the desired transmit/receive frequency. Prior to data transmission by the computer,
Figure 1-1. TTY/EIA Terminal Interface Module
1
Digital Systems Division

CRUBIT15
CRUBIT14
CRUBIT13
CRUBIT12
IMODSELA-
CRUDATAOUT
STORECLOCK-
(A)133015
----
-
-
l
,,
l
~ ,
.'
' ~·
~CRUDATAIN
-
CPU DATA
CPU COMMAND
16 TO 1
--
ADDR DECODER ADDR DECODER
-
LINE
MULTIPLEXER
L.
jJ
CRU INT-
l
COMMAND AND
-
r=--
STATUS CONTROL
,,
,.
TRANSMIT
-
TRANSMIT
j~
·~
-
RECEIVE
SHIFT TIM ING AND
~
BUFFER
GATING
CONTROL
REµ I STER
.----
l
l
,,
BAUD RATE
RECEIVE
14--
GENERATOR
SHIFT
REGISTER
TRANSMIT
~
SHIFT
REGISTER
! OSCLK
!
L---
4 MHZ
RECEIVE
CRYSTAL
TIMING AND
i----
OSCILLATOR
DATACLK_
CONTROL
-
,.
_t~
t~
TTY LINE
EIA LINE
-
EIA COMPATIBLE TERMINAL
-
INTERFACE
INTERFACE
-
l
TTY COMPATIBLE TERMINAL
-
-
Figure 1-2. Full Duplex TIY /EIA Interface Module Simplified Block Diagram

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~ 945408-9701
the request to send and data terminal ready flags are set by the 1/0 service routine to establish
communications with an EIA data terminal. The Data Set Ready signal is then checked to ensure
the data terminal is ready for communications.
1.2.1 TRANSMIT MODE. In the transmit mode, the computer transfers serial data into the
transmit shift register with a STORECLK- signal. Address bits and a module enable signal allow
the shifting process to continue until an 8-bit character has been loaded into the shift register.
When a full character has been received from the computer, the transmit go flag is set. The
transmit go flag enables development of a transmit shift clock whose frequency is determined by
the oscillator/counter network. The transmit shift clock serially transfers the start bit, the 8-bit
character, and one or two stop bits to the attached data terminal. The write request flag is set to
indicate that the character has been output to the data terminal and the module is ready for
another transmission cycle.
1.2.2 RECEIVE MODE. In the receive mode, the data terminal holds either the TTY or EIA
input in a "mark" (logic I) condition until a "space" (logic 0) condition indicates that a new
character is about to be transmitted to the module. The "space" condition sets the receive go
flag, which enables the development of a receive shift clock whose frequency is determined by
the oscillator/counter network. The receive shift clock gates the serial input data into an 8-bit
shift register until a full character has been received. The shift register character is transferred in
parallel to a buffer register and applied to a multiplexer for reading by the computer. The read
request interrupt logic is set to indicate that the buffer register holds a character for the
computer. The computer then enters a service routine that supplies the necessary module enable
and address bits to fetch the character.
1.2.3 INTERRUPT RESPONSE. An interrupt line from the module informs the computer when
the write request flag or read request interrupt logic is set, or when a transition occurs in the
Data Set Ready or Data Carrier Detect signals from the data terminal. All four signals are applied
to the multiplexer and can be read by the computer to determine the source of the interrupt.
The computer instruction repertoire includes single (SBO, SBZ, and TB) and multiple (LOCR
and STCR) bit instructions that can be used to control operation of the module. The SBO and
SBZ instructions set and clear the addressed control flip-flop; the TB instruction tests the
addressed input status line. The LDCR instruction serially transfers an 8-bit character from
memory to the module transmit shift register, and the STCR instruction reads an 8-bit character
from the module receive buffer register into the computer memory, one bit at a time.
1.2.4 CHARACTER FORMAT. The module transmits and receives 10- or II-bit format code as
illustrated in figure I-3. Eight data bits are provided by either the computer or the attached
terminal. The terminal also supplies with its input data a start bit and either one or two stop
bits. The terminal requires these start and stop bits in data transmitted to it. The module
removes_ the start and stop bits from data before transmitting the data to the computer. The
start and stop bits synchronize the receiving circuitry with the remote transmitter for each
character transmitted. Thus, characters may be transmitted in blocks or in random bursts. The
I0- or I I-bit code formats are selected by jumper connections on the module.
3 Digital Systems Division

~----9-4-54_0_8_-9_7_0_1 ____________________________________________ ~-----
I
LOGIC 1 ----
0
START
BIT
10 BIT FORMAT
8 DATA BITS
STOP
START BIT OF NEXT
CHARACTER OR
MARK (OFF) FOR NOT DATA
LOGIC 1 ---- 11 BIT FORMAT BIT
/\ Wll/!Jllfl/J/IPl/11~ : \ WA
START \
0
BIT 8 DATA BITS
2 STOP BITS
(A) 130725
Figure 1-3. Asynchronous (START/STOP) Uata Transmission Formats
1.2.5 DIAGNOSTIC MODE. The diagnostic mode is enabled by setting Communications Register
Unit (CRU) output bit 15 to a one. In this mode the EIA outputs are gated back into the EIA in-
puts. Also, the following output signals are gated back to the following input signals:
Output Signal
DTR
RTS
XMDT
RTS negated
1.3 PHYSICAL CHARACTERISTICS
Input Signal
DSR
DCD
RCYD
RCR.
The TTY /EIA Terminal Interface Module is implemented on a half-size printed circuit board that
can be inserted into any CRU slot of any Model 990 Computer chassis or expansion chassis. The
circuit board is a double-sided board that is 177.8 millimetres (7.00 inches) wide and 274.3 milli-
metres (10.80 inches) high as oriented in figure 1-1. The board is made to be inserted into an 80-
contact, printed circuit board slot connector located in the backpanel of the chassis. There are
two connectors located ·:it the top of the board: a 10-pin flat cable connector (the smaller of the
two) and a connector that conforms to the industry standard for RS-232 EIA interface. There are
eight sets of pluggable jumper sockets on the module labeled El through E27. Jumper plugs are pro-
vided to be plugged into the desired sockets prior to installation of the module as described in
Section II.
1.4 ELECTRICAL CHARACTERISTICS
The interface logic levels and power requirements for the TTY/EIA Terminal Interface Module
are listed in table 1-1.
1.5 MODULE ADDRESS
The location of the module within the computer chassis (or expansion chassis) determines the
CRU base address that the module recognizes. Therefore, before selecting a chassis location,
determine the address that the software handling routine expects the module to recognize.
Change 1 4
Digital Systems Division

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Table 1-1. TTY/EIA Terminal Interface Module Electrical Characteristics
Specification
Peripheral Inputs
Module Outputs
Power (from computer or
expansion chassis)
Transmission Rates Available
Requirement
(EIA Data) -3V to -25V = Logic 1 (Marking)
3V to 25V = Logic 0 (Spacing)
(EIA Control) 3V to 25V = Logic 1 (on)
-3V to -25V = Logic 0 (off)
(TTY) Short Circuit = Logic 1
Open Circuit = Logic 0
(EIA Data) -SV to -11 V =Logic 1
SV to llV =Logic 0
(EIA Control) SV to 11 V = Logic 1
-SV to -11 V = Logic 0
(TTY) 20ma Current Loop = Logic 1
Open Circuit =Logic 0
+5Vdc at 0.38A
EIA I f I
±12Vdc at 20 mA
nter ace
20
mA
75, 110, 300, 1200, 2400, 4800 and 9600 baud
5 Digital
Systems Division

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SECTION II
INSTALLATION
2.1 GENERAL
This section provides instructions for unpacking, inspecting, and installing a TTY /EIA Terminal
Interface Module. Particular attention is given to the connection of the jumper plugs provided with
the circuit board.
2.2 UNPACKING
The module is packed in one box and wrapped in plastic bubble-pack wrapping. Visually inspect
the box for signs of damage. Open the box and remove the module from the bubble-pack
wrapping. Verify that at least eight jumper plugs have been received (they are shipped plugged into
the circuit board). Do not discard any packing material until all equipment is accounted for.
2.3 INSPECTION AND PREPARATION FOR INSTALLATION
Perform the following steps prior to installing the module into a chassis slot:
1. Visually inspect the circuit board for cracks, corrosion, loose components, and loose
connectors.
2. Remove all jumper plugs from their sockets.
3. According to the predetermined operating requirements for the module, insert the
jumper plugs into the sockets. Table 2-1 gives the connections for possible options;
figure 2-1 illustrates the locations of the jumper connections.
4. Install a center card guide (if one is not present) for the selected chassis slot.
2.4 INSTALLATION
After defining a location for the module and checking the jumper plug configuration, perform the
following steps to install the module in the desired location:
1. Ensure that chassis power is off.
2. Insert the circuit board, component side up, into the selected slot until the sides of the
board slide into the card guides on either side of the slot (one guide is in a center card
guide which must have been installed before card insertion).
3. Gently push the board straight in until the card edge connector engages the slotted
connector in the backpanel.
4. Insert the appropriate cable into the proper cable connector.
5, Dress the cable out of the chassis (toward the rear of the chassis),
6. Conn,ect the other end of the cable to the desired peripheral device in accordance with
the installation instructions for the device.
6
Digital Systems Division

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945408-9701
Table 2-1. Jumper Schedule
Option Jumper 733 733/743 306/588
From To
ASR
KSR
Line Printer
Baud Rate=
75
El A
E2
110
El A E2
300
El A
E3
x
1200
ElB
E4 x
2400
ElB
ES
4800
ElB
E6 x
9600 El A
E7
Logic Level = EIA
E8 E9
x x x
TTY E9
ElO
Code Format = 10-bit
El 1 E12 x x x
(receive) 11-bit E12 E13
Code Format = 10-bit E14
EIS
x x x
(transmit) 11-bit EIS E16
Enable receive during RTS E17 E18 x x x
Disable 110 baud E20
E21
x x x
Enable 110 baud
E21 E22
Enable 110 baud E23 E24
RTSE = RTSE E2S E26 x x
.
RTSE = DTRE E26 E27 x
7
Digital Systems Division

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E25 ,E2.6, E27
RTSE SIGNAL
SOURCE
EIA,EIB,E2,
E3,E4,ES,E6,
E7 BAUD RATE
SELECTION
E14,E15,E16
TRANSMIT
CODE FORMAT
(B)135215 (733-1275-9-1)
Figure 2-1. Jumper Socket Locations
8
E8,E9,E10
TTY/EIA LOGIC
LEVEL
E23 ,E24
ENABLE
110 BAUD
E17,El8 ,E19
ENABLE/DISABLE
RECEIVE WHEN
RTS ON
Etl,Et2,E13
RECEIVE CODE
FORMAT
Digital Systems Division

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SECTION III
OPERATING INSTRUCTIONS
· 3.1 GENERAL
Operation of the TTY/EIA Terminal Interface Module consists of the programming required to
perform the necessary interface functions with the attached data terminal. The service routines
implemented to handle this interface use the SBO, SBZ, TB, LDCR, and STCR instructions. These
instructions normally use an effective CRU address that addresses bit zero of the module under
consideration. Since the module can be inserted into any of the available CRU chassis locations
and the locations are wired for preestablished addresses, the base address depends upon that hard-
ware configuration.
The only consideration other than programming that affects the module's operation is the
selection of the proper jumper configuration to match the transfer rate and code format of the
attached data terminal. Refer to Section II of this manual for the details of the various jumper
configurations.
3.2 PROGRAMMING
The interface between the computer and the module consists of 16 addressable 1/0 bits. The
output bits can be divided into two groups of eight, as shown in figure 3-1. The first eight bits
OUTPUT
INPUT
[IJ
LSB
MSB
}
CHARACTER
TO BE
TRANSMITTED
[[]
LSB } RECEIVED
_CH~RACTER
MSB
8
9
A
B
c
D
E
F
NOT USED
DTR (DATA TERMINAL READY)
RTS (REQUEST TO SEND)
CLRWRQ (CLEAR WRITE REQUEST)
C~RRRQ (CLEAR READ REQUEST)
CLRNSF (CLEAR NEW STATUS FLAG)
ENABLE INTERRUPTS
DIAGNOSTIC MODE
I
ff WITH KITS 2265150-0001
000 2, RCR IS REPLACED BY
(A)12918S
RING 1-NDICATOR
8
XMTING (TRANSMIT IN PROGRESS)
9
TIM ERR (TIM ING ERROR)
A
RC,r:(REVERSE CHANNEL RECEIVE)
B
WRQ (WRITE REQUEST)
c
RRQ (READ REQUEST)
D
DCD (DATA CARRIER DETECT)
E
DSR (DATA SET READY)
F
INT (INTERRUPT)
Figure 3-1. TIY /EIA Terminal Interface Module Addressable Input/Output Lines
I
I
Change 1 9 Digital Systems Division

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~ 945408-9701
I
make up the character to be sent to the data terminal, and the last eight bits are used primarily
for control. The first eight bits of input make up the character being received from the data
terminal, and the last eight bits provide the computer with status data. Tables 3-1 and 3-2
describe the output command bits and input status bits, respectively.
Table 3-1. TIY/EIA Terminal Interface Module Output Command Signals
Signal
Data Terminal Ready
Request to Send
Clear Write Request
Clear Read Request
Clear New Status Flag
Enable Interrupts
Diagnostic Mode
Description
Enables data terminal operation (must be on before any communica-
tion using the TTY/EIA module).
Places data terminal in transmit mode (not used with teletypewriters).
Clears write request flag on module to prepare for another character
write (transmit).
Clears read request interrupt logic on module to prepare for another
character read (receive).
Clears new status flag on module to enable new interrupts.
Enables interrupt generating logic on module. (DTR must also be
on.)
Gates EIA outputs to EIA inputs.
Table 3-2. TIY /EIA Terminal Interface Module Input Status Signals
. Signal
Transmit In-Progress
Timing Error
Reverse Channel Receive*
Write Request
Read Request
Data Carrier Detect
Data Set Ready
Interrupt
Description
Module is currently transmitting to a data terminal.
Indicates data in receive buffer register may be in error because two
or more characters have been loaded in the buffer and no read opera-
tion has been performed by the computer.
Indicates reverse channel receive status of 202 type dataset (not used
by teletypewriter).
Write request flag set to indicate a character has been sent to the data
terminal.
Read request flag set to indicate a character has been received
from the data terminal and is ready to be read by the com-
puter.
Indicates carrier is detected at the data terminal (not used by
teletypewriter).
Indicates data terminal is ready to communicate (not used by
teletypewriter).
Module interrupt flag set when the write request flag or read request
flags are set or when a transition occurs in the Data Set Ready or Data
Carrier Detect signals. DTR must have been set.
I *With kits 2265150-0001/0002, this signal is Ring Indicator signifying a remote station is calling the host.
Change 1
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The I/O routines written to handle communications with the data terminals attached to the module
vary with each device type. This is due to the difference in the controls accepted and status re-
turned by the data terminals. Generally, the I/O routine must first establish communications with
the data terminal and then proceed to read/write data on a character-by-character basis. At the same
time, the routine must be prepared for irregular status indicators and be capable of handling
interrupts.
3.2.1 INTERRUPTS. An interrupt is a signal that informs the computer that the module requires
attention. The interrupt flag for the TTY/EIA Terminal Interface Module is input bit F16 . This bit
sets whenever one of three conditions occurs:
• Write Request (input bit B16 ) - When the module has completed transmission of a
character and requires a new character _from the computer, it sets input bit B and sets
the Interrupt Flag, input bit F, to a one. This flag is reset by a CPU output to bit B
(Clear Write Request).
• Read Request (input bit C
16
) - One-half bit time after the module receives an input
character and loads it into the receive buffer register, it sets input bit C and sets the
Interrupt Flag, input bit F, to a one. This flag is reset by a CPU output to bit C (Clear
Read Request).
• New Status Flag -Whenever a status transition occurs in either Data Carrier Detect
(input bit D) or Data Set Ready (input bit E), the module sets the interrupt flag, input
bit F, to a one. Table 3-3 lists the status changes that set the new status flag. This flag
is reset by a CPU output to bit D (Clear New Status Flag).
The interrupt signal to the computer is generated when the interrupt flag is set, ai1d interrupts are
enabled by setting the Enable Interrupt latch, CRU output bit E
16
, to a one. This interrupt signal
is connected to an interrupt level by jumper wiring on the computer backpanel. Refer to the Model
990/4 Computer System Hardware Reference Manual (Manual Number 945251-9701) or the Model
990/10 Computer System Hardware Reference Manual (Manual Number 945417-9701) for informa-
tion on this wiring.
Table 3-3. Status Transitions Affecting New Status Flag
CRU Output CRU Input Bits {EIA Status)
New Status Flag
Bit D E (DSR) D (DCD) .
0 0 to 1 0 1
0 1 1
to 0
0 x 0
to 1 1
0 1
to 0 x 1
pulse x x 0
X =either 1 or 0
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When the interrupt signal is recognized by the computer and the interrupt occurs at a level less than
or equal to the interrupt level in the computer status register, then the following actions occur:
I. The new workspace pointer and program-counter contents are fetched from memory
locations determined by the interrupt level.
2. The current workspace pointer, program-counter and status-register contents are stored in
workspace registers 13, 14 and 15 of the new workspace.
3. The new status register contents are set to inhibit interrupts of lower priority than the
level of the interrupt.
4. The interrupt processing routine is entered at the address specified by the new program
00~~~ •
The interrupt-processing routine determines which module generated the interrupt by interrogating
bit F16 of all modules corresponding to the interrupt level until it finds an active interrupt bit. The
program then examines input bits B (Write Request), C (Read Request), D (Data Carrier Detect),
and E (Data Set Ready) of that module to determine the condition that caused the interrupt, and
the routine must clear the interrupt condition by generating an output (either a I or a 0) to the ap-
plicable address bit.
3.2.2 TIMING CONSIDERATIONS. When data is being transferred to the CPU, a timing error
can occur if the program does not store a received character into memory before a new character
is received. When such an overrun occurs, CRU input bit 9 (TIMERR) from the module sets to
flag the condition. This bit clears automatically when the read request interrupt logic is reset.
---- -
Timing is not critical when data is being transferred from the CPU. However, efficient use of the
communication line requires that the next character to be transmitted be presented to the
interface within one bit time following the Writer Request interrupt. The time interval, in seconds,
between characters for a particular format and baud rate is given by the number of bits per charac-
ter (including start and stop bits) divided by the baud rate. The reciprocal of this character time is
the character rate. The interval between bits (bit time) is the reciprocal of the baud rate.
3.2.3 OUTPUT OPERATION. A character may be output from the computer to the module using
an 8-bit Load CR (LDCR) instruction. Any of the addressing modes of the 990 Computer may be
used. The direct-addressing mode is of the form:
LDCR @CHAR, 8
This instruction results in an 8-bit transfer from memory location CHAR to the current CRU
base address starting with bit 0 and incremented through bit 7. Figure 3-2 illustrates this
transfer. Initiating this sequence starts data transmission from the module when the entire 8-bit
character is present in the module. The data is sent serially on the communication line.
During the transfer operation, CRU bit 8 (Transmit in Progress) remains true; it resets when the
character has been completely transmitted and Write Request (bit B) has been set. A new
character output to the module must not be started until Transmit in Progress drops and Write
Request sets, Outputs to clear intem1pt bits reset independently of the output data lines.
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(DATA TRANSFER IS SERIAL)
0 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MEMORY
ADDRESS 0
CHAR
(A) 130727A
0 0
xx x xx x xx
X =NOT USED
Figure 3-2. Output Character Transfer
MODULE
OUTPUT BITS
0
2
3
4
5
6
7
•
-4-1-
•
•
3.2.4 INPUT OPERATION. A character is input to the computer from the module using·an 8-bit
Store CR (STCR) instruction. Any of the addressing modes of the 990 Computer may be used. The
direct addressing mode is of the form:
STCR @CHAR, 8
This instruction results in an 8-bit transfer from the current CRU base address (bits 0 through 7) to
memory location CHAR. Figure 3-3 illustrates this transfer. The Store CR operation usually occurs
after the module has notified .the program that data is ready for transfer by the Read Request
(bit C) and the Interrupt (bit F). The program must then transfer the data and reset the
interrupt before the next character arrives from the input device and is transferred into the
module buffer register. Failure to respond within this time constraint results in a data overrun
error, and sets the Timing Error input bit (bit 9).
3.2.5 ERROR DETECTION. All data error detection, except data overrun conditions, is the
responsibility of the data-handling program. If one of the eight bits from the module represents
a parity bit, the program must check the input data character parity. This is done by testing the
parity bit in the computer status register after the LDCR instruction. Similarly, if the device con-
nected to the module requires a parity bit, the program must generate that bit. Cyclical redundancy
check characters to maintain the integrity of a data stream, if used, must also be generated and
checked by the program. Module input bit 9 (Timing Error) indicates a data overrum condition.
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Digital Systems Division