Texas Instruments 990/10A User manual

MODEL 990/10A COMPUTER
GENERAL DESCRIPTION

MODEL 990/10A COMPUTER,
GENERAL DESCRIPTION
WARNING: This equipment generates, uses, and can radiate radio fre-
quency energy and if not installed and used in accordance with the in-
structions manual, may cause interference to radio communications. It
has been tested and found to comply with the limits for a Class A com-
puting device pursuant to Subpart J of Part 15 of FCC Rules, which are
designed to provide reasonable protection against such interference
when operated in a commercial environment. Operation of this equip-
ment in a residential area is likely to cause interference in which case the
user at his own expense will be required to take whatever measures may
be required to correct the interference.
WARNING: No user serviceable, installable, or replaceable parts are in-
side the Model 990A13 chassis. The card cage area of the Model 990A13
chassis contains hazardous live electrical components involving risk of
energy hazard-high current levels. Installation instructions provided in
this manual are to be used by trained personnel familiar with electrical
hazards and with a knowledge of basic hand tools and cabling tech-
niques. A detailed knowledge of computer hardware or software is not
required.

LIST OF EFFECTIVE PAGES
Insert latest changed pages and discard superseded pages.
Note: The changes in the text are indicated by a change number at the bot-
tom of the page and a vertical bar in the outer margin of the changed pages,
with the following exceptions:
m A change number at the bottom of the page but no change bar indicates
either a deletion or a page layout change.
m An entire section with no change bars but with change numbers at the
bottom of each page is an entirely new section.
Model 990/10A Computer, General Description (2302633-9701)
Original Issue ... 1... ce ee ee tt eee ee September 1982
Change 1... cece ee ee eee eet eee February 1984
Change 2 0... eee ee ee ee eee eee eet nes May 1985
© 1982, 1984, 1985, Texas Instruments Incorporated. All Rights Reserved.
No part of this publication may be reproduced, stored in a retrieval system,
or transmitted, in any form or by any means, electronic, mechanical, photo-
copying, recording, or otherwise, without the prior written permission of
Texas Instruments.
The manual consists of the most recent full revision (indicated as 0) and the following changed pages
since the last revision. The total pages and change numbers in this publication are as follows:
Page Change No. Page Change No. Page Change No.
Cover ...... cc eee eens 2 1-8 2... ee ee 1 3-14 . oe ee ee eee 2
Inside Cover............ 2 1-9 -— 1-23 ........ 0.0 0 3-15 - 3-18 ............ 0
Title Page .............. 2 1-24 - 1-25 ............ 1 Ce re 0
Effective Pages .......... 2 1-26 .... ee eee eee 0 Ame2 ce ee eee 1
WH/iV oo ee ce 0 07S 0 4-3 —- 4-14 ..... 0... 0
rr 2 1 re 1 0 ie 1
Vi — Vib ww ee 0 7 0 4-16. ee eens 2
Vili ee ee es 1 2-4 —- 2-6 ...cc eee 1 4-17/4-18 ..........00.. 1
5 2 3-1 — 3-4 Loe eee 0 A-1 - A-10 ............ 0
| 0 oe 1 Index-1 -— Index-4....... 0
1-2A/1-2B ............. 1 3-6 — 3-8 ww. ee ee eee 0 Customer Response ...... 2
1-3 - 1-4 ......... ee, 2 Ch 2 Business Reply .......... 2
1-5 fe ee ee ee ee 1 3-10 2. cee ee ee eee 1 Questionnaire ........... 2
| 0 2 B-11 ... eee eee ee ee 0 Business Reply .......... 2
1-6A/1-6B ............. 1 3-12 ee es 1 Inside Cover............ 2
| 0 Oe 0 Cover ..... cece eee eee 2

Preface
This manual provides information about the. Model 990/10A Computer and is directed to both the in-
Stallation personnel and the end-user.
Information in this manual is divided into the following sections:
Section
1 General — Contains physical and functional descriptions that acquaint the user with the
hardware components and capabilities of the Model 990/10A Computer.
2 Installation — Outlines procedures for unpacking the Model 990/10A Computer from its
shipping container and setting the option jumpers and switches.
3 Operation — Describes the indicators on the front panel and PWB and provides general
operating procedures.
4 Programming — Presents information for use by programmers on the function of the pro-
cessor and the asynchronous communication controller.
Appendix
A Using the Multiprocessing Interface — Contains information on system configuration
and programming the multiprocessing interface.
The following documents contain additional information related to the Model 990/10A Computer.
Title Part Number
Model 990/10A Computer Maintenance Manual — Field
Theory and Maintenance 2302634-9701
Model 990/10A Computer Maintenance Manual — Depot
Theory and Maintenance 2302635-9701
Model 990 Computer 990/10 and 990/12 Assembly
Language Reference Manual 2270509-9701
Model 990 Computer Diagnostics Handbook 945400-9701
Model 990A13 Chassis Maintenance Manual — General
Description 2308774-9701
ROM Loader User’s Guide 2270534-9701
2302633-9701 iii/iv

Contents
Paragraph
1.1
1.2
1.3
1.3.4
1.3.2
1.3.2.1
1.3.2.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.4
1.5
1.5.1
1.5.2
1.5.2.1
1.5.2.2
1.5.2.3
1.5.2.4
1.5.2.5
1.5.3
1.5.4
1.5.5
1.5.5.1
1.5.5.2
1.5.5.3
1.5.5.4
1.5.5.5
1.5.5.6
1.5.5.7
1.5.5.8
1.5.6
1.5.6.1
1.5.6.2
1.5.7
1.5.8
1.5.9
1.5.10
2302633-9701
1 — General Description
General... 0... ccc eee teens
Purpose of Equipment..................
Equipment Description
Microprocessor ...........000 cece eae
Memory... .....0. 00 cece ee eee eee
Asynchronous Communication Controller
Specifications .....................08.
Functional Description of Equipment
Microprocessor ...........2..0 02 eee
Memory Mapping..................5-
Map Operation.................05.
Map Initialization..................
TILINE Peripheral Control Space (TPCS) Mapping
Scratch Pad RAM..................
Loader/Self-Test ROM Mapping
Memory Correction and Control
Memory Allocation ..................
InterruptS .. 0... 0... ee ee ee
Level 0 Interrupt (Power Restored)
Level 1 Interrupt (Power Failure Imminent)
Level 2 Interrupt (Error Conditions)
Level 3 Host Processor Interrupt .
Level 5 or 15 Interrupt (Real-Time Clock)
Level 8 (EIA Port Interrupt)
External Interrupts
Nonmaskable Interrupt (NMI)
Communication Register Unit (CRU) Controller
Parallel CRU Operations
CRU Addressing...................
Backpanel Interface
Front Panel Interface
Asynchronous Communication Port
TILINE Interface.................040.
eo @ © © € @e © © © @ @ © © © e@ @ 8
Page

Contents
Paragraph
1.5.10.1
1.5.10.2
1.5.10.3
1.5.10.4
2.1
2.2
2.3
2.3.1
3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.3.4
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.2
3.4.3
3.4.4
3.4.5
3.5
3.5.1
3.5.2
3.5.3
vi
° Title Page
TILINE Master .....00.0 00.000. 0. cc cc cece cence eee eee 125
TILINE Slave................ Soe ee ec ct ee ee eee ee eee ee ee eee eee 1-25
TILINE Hold .. 0.0... 00.000. cee ce ce ee ec ce eee eee eee ee 126
TILINE Wait .. 0.0.00. 0.0. ce en cee eee e eee eee as 1-26
General... 0.0.0.0. 00. ccc cee eee eee cee eee eee eee eee eee 2-1
Unpacking/Packing 990/10A Board ...... 0... 0.0. eee eens 2-1
990/10A Installation Procedures... 1.0.0... eee ee eens 2-2
Setting Option Switches and Jumpers on the 990/10A Board .................. 2-2
3 — Operation
General... ec eee ee eee eee eee eee eee eee ee eee 3-1
Control/Display Module Controls and Indicators .......... 0.0.0.0... cece eee 3-2
Controls ... 0... eee ee eee eee eee eee ee eee eee 3-2
HALT Switch 0.00000 cece eee e eet e een 3-2
RUN Switch 2.0.2.0... 0 ce ee eee eee eee 3-2
LOAD Switch ... 0.0.0. 2. eee ee ene eee 3-2
ALT LOAD Switch 2.0.0.0 0. cc nets 3-3
Indicators .. 0. en eee nee eee eee ee ees 3-3
Hexadecimal Display ...... 0.0.00. ee eee eens 3-3
POWERLED...... 0... 0 cc eee eee nes 3-3
FAULTLED...... 0. nee ee eens 3-3
RUNLED... 0... cee bene ee eens 3-3
IDLE LED 2.0... nc ee eee eens 3-3
990/10A PWB Indicators ....... 00.0. 0. cc eee ee nee eee 3-5
Major Fault LED... . 0.0.0.0. ce ce eee eens 3-5
Fault LED «0... nee eee eee eee eens 3-5
Memory Error indicators ...... 0.0000. eee eee eens 3-5
Double-Bit Error... 0.0.0 ce eee eee ees 3-5
Single-Bit Error... 0. ee eee eee eee ees 3-5
nO) 5) a 3-6
BIT-IN-ERROR ......... ee ene eee ee ee eee ee ee eee eee eee nee 3-6
Q90/10A Self-Test ........ 0.0000... eee ee ee ee ee ee eee eens 3-6
Self-Test Description... 0... 0. ene ene eens 3-6
Major Fault Test.... 0.0.0... ccc cece teen e tent bebe e teen nes 3-6
General Fault Test... 0.0... 0. cc eee eee teen ne 3-13
Self-Test Execution Time ...................... eee ee eee eee eee 3-14
Self-Test Error Reporting ...... 0.0.0.0... eee ae 3-14
Bypassing a Self-Test Failure ....... 0... 00. eens 3-14
Other Information Available as a Result of a Self-Test Failure................ 3-16
Load Device Verification.......................0.. cee eee eee eee eee 3-17
Special Features of Load Device Verification.................0.0......0045. 3-17
Understanding Self-Test Error Codes ......... 0.0.00 0.00 cc cee eee 3-17
Understanding Loader Error CodeS .......... 0.0.0 0c eens 3-18
2302633-9701

Paragraph
4.1
4.2
4.2.1
4.2.2
4.3
4.4
4.5
4.5.1
45.2
4.5.3
4.5.4
4.6
4.6.1
4.6.2
4.6.3
Appendix
A
2302633-9701
Title
4 — Programming
Additional Instructions .......... 0... ccc cee eee eee
Mapping Instructions (LMF, LDS, LDD).....................
Status Register ...... Lee eee eee eee eee eect eee eeeee
Error Status Register... 1... 0... ccc ccc eee eet aee
TMS9902 Asynchronous Communication Controller
CRU Implementation External to the TMS 9902 ..............
Interrupt Output ...... 0.0.0. cc ce cee ee eens
Control and Data Output........... 0.0... cece eee
Status and Data lnput .......... 0.0... ce es
Memory Error log .......... ccc eee eee neta eae
Error Correction Test... 0... 0... ccc ee eee tenes
Output Bits... cee eee ene ene es
Input Bits ..... ae eee eee eee ee ee eee eee en ee eee eee nes
Appendix
Title
Using the Multiprocess Interface................. 00.0000 0 00
eeeeeee @ co ee © 8
Contents
Page
vii

Contents
lilustrations
Figure Title Page
1-1 Model 990/10A Processor Board ...... 0.0... cc ec eee e eens 1-2
1-1A Model 990/10A Surface Mount 1-Megabyte Processor Board .................. 1-2A
1-2 TILINE Peripheral Control Space Implementation.............0............0000. 1-8
1-3 Flowchart of Nonmaskable Interrupt and Front Panel Code ................... 1-14
1-4 Single-Bit CRU Address Development .............. 0.00. c ccc ee ee eee 1-18
2-1 Switch and Jumper LocationS ..... 0.0... 0. eee eee eee eens 2-3
2-2 Switch and Jumper Locations on 1-Megabyte Processor Board ................. 2-4
3-1 Control/Display Module... 0.0... nee nee eee 3-1
3-2 Universal Loader Search Algorithm ........0.0 00. . eee 3-4
3-3 990/10A Board Failure Indicators ..... 0.0.00. een 3-5
3-4 Flowchart of 990/10A Self-test Code .... 0... een 3-7
3-5 Programmer Panel andCDM ........ 0.0.00. eee eens 3-15
4-4 990/10A Status Register .... 0.0... . eee ee 4-2
4-2 Asynchronous Communication Port Interface ......... 0.000.002 eee 4.3
4-3 Diagnostic Control Output Bit Assignment — Word0...............-. 0.0206. 4-14
4-4 Error Log Input Bit Assignment — Word0.... 0.6... ee 4-15
4-5 Error Log Input Bit Assignment — Word1........... 2.00.0 4-16
Tables
Table Title Page
1-1 Physical, Electrical, and Environmental Specifications.................0........ 1-6
1-2 990/10A Typical Memory Allocation .... 0.0.00... . cc eee 1-10
1-3 Error Status Register CRU Bit Definitions............0 0.0.0.0... 0 ee 1-12
1-4 CRU Address Map ..... 0... 0... eee ete eee 1-19
1-5 Backpanel Connector P1 ... 0... eens 1-20
1-6 Backpanel Connector P2 ....... 0... eee nee teens 1-22
1-7 Front Panel Connector P4 2.0... nent eens 1-24
1-8 Asynchronous Communication Port Connector P3......... 20.0... 0. cee ee 1-25
2-1 Memory Control TPCS Addresses... 0... 0... ccc ne eee eens 2-2
2-2 990/10A Controller Starting Address Switch Settings....................0.0... 2-5
2-3 Option JUMPErS 20 ee eee ene e net eee teen 2-5
3-1 Self-Test Error Reporting Bit Assignment ......... 0.0.0... eee 3-18
4-1 CRU Output Bits totheACC ... 0... ee 4-5
4-2 CRU Input Bits fromthe ACC .. 0... ee 4-11
4-3 Memory Control TPCS Addresses ........ 0.00.00. ee 4-14
viii Change 1 2302633-9701

General Description
1.1 GENERAL
This manual provides unpacking, installation, testing, and operating information for the Texas
Instruments Model 990/10A Processor (Figure 1-1 or Figure 1-1A). This section contains functional
and physical descriptions to acquaint the user with the hardware components and capabilities of
the Model 990/10A Processor, hereafter referred to as the 990/10A.
1.2 PURPOSE OF EQUIPMENT
The 990/10A is a single board replacement for the 990/10 processor. The 990/10A combines a
990/10-compatible processor with a maximum of 1.5 megabytes of error correcting memory, an
asynchronous communications port, TILINE™ interface, communications register unit (CRU)
interface, and control logic for operation in a multiprocessor system. When combined in.a chassis
with appropriate peripherals for input, output, and mass storage, the 990/10A forms part of a stand-
alone minicomputer system.
1.3 EQUIPMENT DESCRIPTION
The 990/10A is a full-function processor on a single printed wiring board (PWB). Much of the discrete
circuitry of the 990/10 is incorporated into custom large scale integration (LSI) devices in the
990/10A, resulting in lower cost and power consumption with increased reliability. The speed in-
creases resulting from the single-board design of the 990/10A give an average 1.5 times increase in
throughput over the 990/10, for most applications. The following paragraphs describe the major
components of the 990/10A.
TILINE is a trademark of Texas Instruments Incorporated.
2302633-9701 Change 2 1-1

General Description
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1-2 2302633-9701

General Description
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Change 1
2302633-9701

General Description
1.3.1. Microprocessor
The TMS 99000 microprocessor used on the 990/10A is an upwardly compatible, high performance
member of the TMS 9900 family. This microprocessor implements the 990/10 instruction set and an
additional five instructions, providing the capability of a full minicomputer on a single chip.
The following characteristics are offered by the microprocessor.
e Sixteen-bit instruction word
e Memory-to-memory architecture
e 77 instructions including signed multiply and divide
€ Multiple register files resident in memory
e 16 prioritized hardware interrupts
e 16 software interrupts
e Programmed input/output (I/O) and direct memory accessing (DMA) capability
e I/O operation addressable in bit, byte, or word increments via the CRU
e Multiprocessor system interlock signal
e Privileged instructions
e User and supervisor modes
1.3.2 Memory
Four pencil switches select the lower bound of on-board memory in 128-kilobyte increments. This
memory can be accessed by the microprocessor or by any device on the TILINE bus.
The 990/10A is provided with on-board memory in a variety of configurations:
e Two rows of 64 kilobit dynamic random-access memory (DRAM) integrated circuits (ICs)
totalling 256 kilobytes
e Four rows of 64K DRAM ICs totalling 512 kilobytes
e Eight rows of 64K DRAM surface-mount ICs totalling 1024 kilobytes
e One row of 256K DRAM ICs totalling 512 kilobytes
e Two rows of 256K DRAM ICs totalling 1024 kilobytes
e Three rows of 256K DRAM ICs totalling 1536 kilobytes
2302633-9701 Change 2 1-3

General Description
1.3.2.1. Memory Correction and Control. The correction and control chip provides error detec-
tion and correction capability for the on-board memory. This chip generates a six-bit checkword
with each memory write. On subsequent memory reads, the checkword is used to correct single
bit errors and to flag double bit errors.
1.3.2.2 Memory Mapping. The memory mapping chip performs a mapping algorithm to convert
16-bit byte level addresses (logical addresses) into 20-bit word addresses (physical addresses) for
the internal memory bus. In addition to generating the physical addresses, the memory mapping
chip detects an attempt to access memory addresses larger than the value stored in the highest
limit register. Logic external to the memory mapping chip generates an error interrupt, preventing
out-of-range addressing. This external logic also detects accesses to peripheral controllers and
maps these accesses to the TILINE peripheral control space (TPCS).
1.3.3 Input/Output (I/O)
The following paragraphs describe the interface controllers on the 990/10A that provide input/output
capability. These controllers are also used for many of the on-board data and control word transfer
operations of the processor. Both TILINE and CRU controllers are provided, as well as one on-board
asynchronous communication port.
1.3.3.1 TILINE Control. The TILINE is a high-speed, asynchronous interface bus that provides
transfer rates approaching the rates of DMA interface controllers, but does not require the complex
controllers for each device. The 990/10A supports all existing TILINE memory and peripheral
devices. TILINE devices can access memory contained on the 990/10A board as well as off-board
TILINE memory. The TILINE controller consists of a master controller and a slave controller along
with synchronization and interface circuits common to both.
1.3.3.2 CRU Interface. The 990/10A provides the CRU interface that is standard on 990 family pro-
cessors, in a custom integrated circuit. This versatile, command-driven interface can effectively
handle a wide range of control and data transfer operations with its extremely flexible format. The
CRU can set, reset, or test a field of one to sixteen bits in the CRU array. The CRU operates ata 2.5
megahertz data rate with devices in the main chassis, and at a 1.67 megahertz rate on CRU reads
from devices in an expansion chassis. CRU writes to expansion chassis devices occur at 2.5
megahertz. The use of an expansion chassis in the system does not reduce the rate for main
chassis communication. In addition to the CRU control function, the CRU controller performs the
following functions:
e Bus status decode
e Single instruction execution control
e Run mode logic
e System error latch
e Front panel test logic
e Real-time clock state controller
e Ready generation to the microprocessor
1-4 Change 2 2302633-9701

General Description
1.3.3.3 Asynchronous Communication Controller. . The asynchronous communication controller
provides an interface port for one video terminal, printer, or any other EIA compatible device. The
asynchronous communication controller uses the TMS 9902 chip to provide the following:
Interrupt control
Timing control between the microprocessor and an I/O device
Asynchronous operation
Character length of five to eight bits
Fully programmable data rate
Interval timer
Even, odd, or no parity
1, 1.5, or 2 stop bits
2302633-9701 Change 1 1-5

General Description
1.4 SPECIFICATIONS
Table 1-1 lists the physical, electrical, and environmental specifications for the 990/10A board.
Table 1-1. Electrical, Environmental, and Physical Specifications
Characteristic
Specification
Electrical
Total power required
Voltage
+5 V main
+ 5 V main (1 megabyte)
+5 V memory
with 512K bytes
with 1 megabyte
with 1.5 megabytes
+ 12 V memory
+12V main
—- 12V main
— 12 V memory
—-5V memory
Environmental
Ambient temperature (operating)
Ambient temperature (storage)
Ambient humidity (operating)
Ambient humidity (storage)
Shock
Vibration
Physical
Length x Width
Not more than 30 watts
Current Power Requirements
4.8A 24.0W
4.6A 23.0 W
1.10 A (operating) 5.5 W
0.17 A (standby) 0.9W
1.20 A (operating) 6.0 W
0.33 A (standby) 1.7W
1.30 A (operating) 6.5W
0.50 A (standby) 2.5W
0.00A 0.0W
26 mA (EIA drivers) 0.3 W
— 26 mA (EIA drivers) 0.3 W
0.00A 0.0W
0.00A 0.0W
0 to 65 °C (32 to 149 °F) (Derate2 °C
(3.6 ° F) for every 761 m (approximately
2500 ft) of elevation)
— 40 to 70 °C(- 40 to 158 ° F)
5 to 95% (noncondensing)
5 to 95% (noncondensing)
2-inch vertical drop (installed in chassis)
1 G (5 to 80 Hz) (installed in chassis)
0.3 G (80 to 500 Hz) (installed in chassis)
362 mm x 274 mm (14.25 in. x 10.80 in.)
1-6
Change 2
2302633-9701