Texas instruments Tms320c645x User manual

TMS320C645x DSPEthernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

User's Guide

Literature Number: SPRU975B

August 2006

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Contents

Preface .............................................................................................................................. 101 Introduction .............................................................................................................. 111.1 Purpose of the Peripheral ..................................................................................... 111.2 Features ......................................................................................................... 111.3 Functional Block Diagram ..................................................................................... 121.4 Industry Standard(s) Compliance Statement ............................................................... 132 EMAC Functional Architecture .................................................................................... 142.1 Clock Control .................................................................................................... 142.2 Memory Map .................................................................................................... 152.3 System Level Connections .................................................................................... 162.4 Ethernet Protocol Overview ................................................................................... 242.5 Programming Interface ......................................................................................... 262.6 EMAC Control Module ......................................................................................... 372.7 Management Data Input/Output (MDIO) Module ........................................................... 382.8 EMAC Module ................................................................................................... 432.9 Media Independent Interfaces ................................................................................ 462.10 Packet Receive Operation ..................................................................................... 502.11 Packet Transmit Operation .................................................................................... 552.12 Receive and Transmit Latency ............................................................................... 552.13 Transfer Node Priority .......................................................................................... 562.14 Reset Considerations .......................................................................................... 562.15 Initialization ...................................................................................................... 572.16 Interrupt Support ................................................................................................ 602.17 Power Management ............................................................................................ 632.18 Emulation Considerations ..................................................................................... 633 EMAC Control Module Registers ................................................................................. 643.1 Introduction ...................................................................................................... 643.2 EMAC Control Module Interrupt Control Register (EWCTL) .............................................. 643.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) ................................. 654 MDIO Registers ......................................................................................................... 664.1 Introduction ...................................................................................................... 664.2 MDIO Version Register (VERSION) ......................................................................... 674.3 MDIO Control Register (CONTROL) ......................................................................... 684.4 PHY Acknowledge Status Register (ALIVE) ................................................................ 694.5 PHY Link Status Register (LINK) ............................................................................. 704.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 714.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .......................... 724.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ................... 734.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................. 744.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ................ 754.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .......... 764.12 MDIO User Access Register 0 (USERACCESS0) ......................................................... 774.13 MDIO User PHY Select Register 0 (USERPHYSEL0) .................................................... 784.14 MDIO User Access Register 1 (USERACCESS1) ......................................................... 79

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4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 805 EMAC Port Registers ................................................................................................. 815.1 Introduction ...................................................................................................... 815.2 Transmit Identification and Version Register (TXIDVER) ................................................. 855.3 Transmit Control Register (TXCONTROL) .................................................................. 865.4 Transmit Teardown Register (TXTEARDOWN) ............................................................ 875.5 Receive Identification and Version Register (RXIDVER) .................................................. 885.6 Receive Control Register (RXCONTROL) .................................................................. 895.7 Receive Teardown Register (RXTEARDOWN) ............................................................. 905.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .................................... 915.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................... 925.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) ................................................ 935.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .......................................... 945.12 MAC Input Vector Register (MACINVECTOR) ............................................................. 955.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ..................................... 965.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................... 975.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ................................................. 985.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ........................................... 995.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ..................................... 1005.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ................................... 1015.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ................................................. 1025.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ........................................... 1035.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .......... 1045.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................... 1065.23 Receive Unicast Clear Register (RXUNICASTCLEAR) .................................................. 1075.24 Receive Maximum Length Register (RXMAXLEN) ....................................................... 1085.25 Receive Buffer Offset Register (RXBUFFEROFFSET) .................................................. 1095.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .................. 1105.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) ....................... 1115.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) .............................. 1125.29 MAC Control Register (MACCONTROL) .................................................................. 1135.30 MAC Status Register (MACSTATUS) ...................................................................... 1155.31 Emulation Control Register (EMCONTROL) .............................................................. 1175.32 FIFO Control Register (FIFOCONTROL) .................................................................. 1185.33 MAC Configuration Register (MACCONFIG) .............................................................. 1195.34 Soft Reset Register (SOFTRESET) ........................................................................ 1205.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ....................................... 1215.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 1225.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 1235.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 1245.39 Back Off Test Register (BOFFTEST) ....................................................................... 1255.40 Transmit Pacing Algorithm Test Register (TPACETEST) ............................................... 1265.41 Receive Pause Timer Register (RXPAUSE) .............................................................. 1275.42 Transmit Pause Timer Register (TXPAUSE) .............................................................. 1285.43 MAC Address Low Bytes Register (MACADDRLO) ...................................................... 1295.44 MAC Address High Bytes Register (MACADDRHI) ...................................................... 1305.45 MAC Index Register (MACINDEX) ......................................................................... 1315.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) ............................ 1325.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) ............................ 133

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5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) ........................................... 1345.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) ........................................... 1355.50 Network Statistics Registers ................................................................................. 136Appendix A Glossary ...................................................................................................... 145Appendix B Revision History ............................................................................................ 147

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List of Figures

1 EMAC and MDIO Block Diagram ........................................................................................ 122 Ethernet Configuration with MII Interface ............................................................................... 163 Ethernet Configuration with RMII Interface ............................................................................. 184 Ethernet Configuration with GMII Interface ............................................................................. 205 Ethernet Configuration with RGMII Interface ........................................................................... 226 Ethernet Frame ............................................................................................................. 247 Basic Descriptor Format ................................................................................................... 268 Typical Descriptor Linked List ............................................................................................ 279 Transmit Descriptor Format ............................................................................................... 3010 Receive Descriptor Format ................................................................................................ 3311 EMAC Control Module Block Diagram .................................................................................. 3712 MDIO Module Block Diagram ............................................................................................. 3913 EMAC Module Block Diagram ............................................................................................ 4314 EMAC Control Module Interrupt Control Register (EWCTL) .......................................................... 6415 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) ............................................. 6516 MDIO Version Register (VERSION) ..................................................................................... 6717 MDIO Control Register (CONTROL) ..................................................................................... 6818 PHY Acknowledge Status Register (ALIVE) ............................................................................ 6919 PHY Link Status Register (LINK) ......................................................................................... 7020 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ........................................ 7121 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ...................................... 7222 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ............................... 7323 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ............................. 7424 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ........................... 7525 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ..................... 7626 MDIO User Access Register 0 (USERACCESS0) ..................................................................... 7727 MDIO User PHY Select Register 0 (USERPHYSEL0) ................................................................ 7828 MDIO User Access Register 1 (USERACCESS1) ..................................................................... 7929 MDIO User PHY Select Register 1 (USERPHYSEL1) ................................................................ 8030 Transmit Identification and Version Register (TXIDVER) ............................................................. 8531 Transmit Control Register (TXCONTROL) .............................................................................. 8632 Transmit Teardown Register (TXTEARDOWN) ........................................................................ 8733 Receive Identification and Version Register (RXIDVER) ............................................................. 8834 Receive Control Register (RXCONTROL) .............................................................................. 8935 Receive Teardown Register (RXTEARDOWN) ........................................................................ 9036 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ................................................ 9137 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .............................................. 9238 Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................................ 9339 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ...................................................... 9440 MAC Input Vector Register (MACINVECTOR) ......................................................................... 9541 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 9642 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................... 9743 Receive Interrupt Mask Set Register (RXINTMASKSET) ............................................................. 9844 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ...................................................... 9945 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................ 10046 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ............................................... 10147 MAC Interrupt Mask Set Register (MACINTMASKSET) ............................................................. 10248 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ...................................................... 10349 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ...................... 10450 Receive Unicast Enable Set Register (RXUNICASTSET) .......................................................... 10651 Receive Unicast Clear Register (RXUNICASTCLEAR) ............................................................. 10752 Receive Maximum Length Register (RXMAXLEN) ................................................................... 108

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53 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 10954 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 11055 Receive Channel nFlow Control Threshold Register (RX nFLOWTHRESH) ..................................... 11156 Receive Channel nFree Buffer Count Register (RX nFREEBUFFER) ............................................ 11257 MAC Control Register (MACCONTROL) .............................................................................. 11358 MAC Status Register (MACSTATUS) .................................................................................. 11559 Emulation Control Register (EMCONTROL) .......................................................................... 11760 FIFO Control Register (FIFOCONTROL) .............................................................................. 11861 MAC Configuration Register (MACCONFIG) ......................................................................... 11962 Soft Reset Register (SOFTRESET) .................................................................................... 12063 MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 12164 MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 12265 MAC Hash Address Register 1 (MACHASH1) ........................................................................ 12366 MAC Hash Address Register 2 (MACHASH2) ........................................................................ 12467 Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 12568 Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 12669 Receive Pause Timer Register (RXPAUSE) .......................................................................... 12770 Transmit Pause Timer Register (TXPAUSE) .......................................................................... 12871 MAC Address Low Bytes Register (MACADDRLO) .................................................................. 12972 MAC Address High Bytes Register (MACADDRHI) .................................................................. 13073 MAC Index Register (MACINDEX) ..................................................................................... 13174 Transmit Channel nDMA Head Descriptor Pointer Register (TX nHDP) .......................................... 13275 Receive Channel nDMA Head Descriptor Pointer Register (RX nHDP) .......................................... 13376 Transmit Channel nCompletion Pointer Register (TX nCP) ......................................................... 13477 Receive Channel nCompletion Pointer Register (RX nCP) ......................................................... 13578 Statistics Register ......................................................................................................... 136

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List of Tables

1 Interface Selection Pins ................................................................................................... 162 EMAC and MDIO Signals for MII Interface ............................................................................. 173 EMAC and MDIO Signals for RMII Interface ........................................................................... 194 EMAC and MDIO Signals for GMII Interface ........................................................................... 215 EMAC and MDIO Signals for RGMII Interface ......................................................................... 236 Ethernet Frame Description ............................................................................................... 247 Basic Descriptors ........................................................................................................... 268 Receive Frame Treatment Summary .................................................................................... 539 Middle of Frame Overrun Treatment .................................................................................... 5410 Emulation Control .......................................................................................................... 6311 EMAC Control Module Registers ......................................................................................... 6412 EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions ................................... 6413 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions ....................... 6514 Management Data Input/Output (MDIO) Registers .................................................................... 6615 MDIO Version Register (VERSION) Field Descriptions ............................................................... 6716 MDIO Control Register (CONTROL) Field Descriptions .............................................................. 6817 PHY Acknowledge Status Register (ALIVE) Field Descriptions ..................................................... 6918 PHY Link Status Register (LINK) Field Descriptions .................................................................. 7019 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................. 7120 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ................ 7221 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ........ 7322 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions ....... 7423 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ..... 7524 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) FieldDescriptions ................................................................................................................. 7625 MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................... 7726 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions .......................................... 7827 MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................... 7928 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions .......................................... 8029 Ethernet Media Access Controller (EMAC) Registers ................................................................. 8130 Transmit Identification and Version Register (TXIDVER) Field Descriptions ....................................... 8531 Transmit Control Register (TXCONTROL) Field Descriptions ....................................................... 8632 Transmit Teardown Register (TXTEARDOWN) Field Descriptions.................................................. 8733 Receive Identification and Version Register (RXIDVER) Field Descriptions ....................................... 8834 Receive Control Register (RXCONTROL) Field Descriptions ........................................................ 8935 Receive Teardown Register (RXTEARDOWN) Field Descriptions .................................................. 9036 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions .......................... 9137 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ........................ 9238 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ...................................... 9339 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ................................ 9440 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................... 9541 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions .......................... 9642 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions......................... 9743 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ...................................... 9844 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ................................ 9945 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions .......................... 10046 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions......................... 10147 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ...................................... 10248 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................ 10349 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 104

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50 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 10651 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 10752 Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................ 10853 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ........................................ 10954 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ....... 11055 Receive Channel nFlow Control Threshold Register (RX nFLOWTHRESH) Field Descriptions ............... 11156 Receive Channel nFree Buffer Count Register (RX nFREEBUFFER) Field Descriptions ...................... 11257 MAC Control Register (MACCONTROL) Field Descriptions ........................................................ 11358 MAC Status Register (MACSTATUS) Field Descriptions ........................................................... 11559 Emulation Control Register (EMCONTROL) Field Descriptions .................................................... 11760 FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................ 11861 MAC Configuration Register (MACCONFIG) Field Descriptions ................................................... 11962 Soft Reset Register (SOFTRESET) Field Descriptions .............................................................. 12063 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................ 12164 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................. 12265 MAC Hash Address Register 1 (MACHASH1) Field Descriptions ................................................. 12366 MAC Hash Address Register 2 (MACHASH2) Field Descriptions ................................................. 12467 Back Off Test Register (BOFFTEST) Field Descriptions ............................................................ 12568 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ..................................... 12669 Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................... 12770 Transmit Pause Timer Register (TXPAUSE) Field Descriptions ................................................... 12871 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ........................................... 12972 MAC Address High Bytes Register (MACADDRHI) Field Descriptions ............................................ 13073 MAC Index Register (MACINDEX) Field Descriptions ............................................................... 13174 Transmit Channel nDMA Head Descriptor Pointer Register (TX nHDP) Field Descriptions .................... 13275 Receive Channel nDMA Head Descriptor Pointer Register (RX nHDP) Field Descriptions .................... 13376 Transmit Channel nCompletion Pointer Register (TX nCP) Field Descriptions .................................. 13477 Receive Channel nCompletion Pointer Register (RX nCP) Field Descriptions ................................... 13578 Statistics Register Field Descriptions .................................................................................. 136A-1 Physical Layer Definitions ............................................................................................... 146B-1 Document Revision History .............................................................................................. 147

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PrefaceSPRU975B – August 2006

Read This First

About This Manual

This document provides a functional description of the Ethernet Media Access Controller (EMAC) andPhysical layer (PHY) device Management Data Input/Output (MDIO) module integrated withTMS320C645x devices.

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the C6000™ devices and related support tools. Copies of thesedocuments are available on the Internet at www.ti.com. Tip: Enter the literature number in the search boxprovided at www.ti.com .

TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU732B ) describes theCPU architecture, pipeline, instruction set, and interrupts of the C64x and C64x+ DSPs.

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TMS320C6000 Programmer's Guide (literature number SPRU198 ) describes ways to optimize C andassembly code for the TMS320C6000™ DSPs and includes application program examples.

TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301 ) introduces the CodeComposer Studio™ integrated development environment and software tools.

Code Composer Studio Application Programming Interface Reference Guide (literature numberSPRU321 ) describes the Code Composer Studio™ application programming interface (API), which allowsyou to program custom plug-ins for Code Composer.

TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 ) describes theTMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal directmemory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,bandwidth management, and the memory and cache.

TMS320C645x DSP Peripherals Overview Reference Guide (literature number SPRUE52 ) provides abrief description of the peripherals available on the TMS320C645x digital signal processors (DSPs).