Texas Instruments ADS62P EVM Series User manual

ADS62PXXEVM
User's Guide
Literature Number: SLAU237AMay 2008 – Revised April 2009

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Contents
1 Overview ............................................................................................................................. 61.1 ADS62PXX EVM Quick-Start Procedure .............................................................................. 62 Circuit Description ............................................................................................................... 82.1 Schematic Diagram ....................................................................................................... 82.2 ADC Circuit Function ..................................................................................................... 83 TI ADC SPI Control Interface ................................................................................................ 173.1 Installing the ADC SPI Control Software ............................................................................. 173.2 Setting Up the EVM for ADC SPI Control ............................................................................ 183.3 Using the TI ADC SPI Interface Software ............................................................................ 194 Connecting to FPGA Platforms ............................................................................................ 214.1 TSW1200 Capture Board ............................................................................................... 214.2 TSW1100 ................................................................................................................. 245 ADC Evaluation .................................................................................................................. 255.1 Hardware Selection ..................................................................................................... 255.2 Coherent Input Frequency Selection .................................................................................. 266 Physical Description ........................................................................................................... 276.1 PCB Layout ............................................................................................................... 276.2 Bill of Materials ........................................................................................................... 316.3 EVM Schematics ........................................................................................................ 33
Important Notices ............................................................................................................... 39
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List of Figures
1 ADS62PXX Jumpers ........................................................................................................ 82 ADS62PXX Surface Jumpers .............................................................................................. 93 ADS62PXXEVM Power Distribution ..................................................................................... 104 CDCE72010 EEPROM Configuration Block Diagram ................................................................. 165 Found New Hardware ..................................................................................................... 176 Window Logo Testing ...................................................................................................... 187 Hardware Device Manager ................................................................................................ 188 SPI Interface Screen ....................................................................................................... 199 TSW1200 GUI Introduction ............................................................................................... 2110 Quick-Setup Test Result .................................................................................................. 2211 ADC Performance With Clock Through Onboard VCXO, CDCE72010 and Crystal Filter ....................... 2312 ADC Performance With Clock Through Onboard VCXO, CDCE72010 Configured for Differential LVPECLOutput ........................................................................................................................ 2413 Top Silkscreen .............................................................................................................. 2714 Component Side ............................................................................................................ 2815 Power Plane 1 .............................................................................................................. 2816 Layer 2 ....................................................................................................................... 2917 Layer 3 ....................................................................................................................... 2918 Bottom Side ................................................................................................................. 3019 EVM Schematic, Sheet 1 .................................................................................................. 3320 EVM Schematic, Sheet 2 .................................................................................................. 3421 EVM Schematic, Sheet 3 .................................................................................................. 3522 EVM Schematic, Sheet 4 .................................................................................................. 3623 EVM Schematic, Sheet 5 .................................................................................................. 3724 Breakout Board Schematic, Sheet 6 ..................................................................................... 38
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List of Tables
1 Jumper List ................................................................................................................... 72 EVM Power Supply Jumper Description ................................................................................ 113 EVM Power Supply Options .............................................................................................. 114 Analog Input Jumper description ......................................................................................... 125 EVM Analog Input Options ................................................................................................ 136 Clock Input Jumper Description .......................................................................................... 147 EVM Clock Input Options ................................................................................................. 158 ADS62PXX Frequently Used Registers ................................................................................. 209 Bill of Materials ............................................................................................................. 31
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1 Overview
1.1 ADS62PXX EVM Quick-Start Procedure
User's GuideSLAU237A – May 2008 – Revised April 2009
ADS62PXXEVM
This user’s guide gives a general overview of the evaluation module (EVM) and provides a generaldescription of the features and functions to be considered while using this module. This manual isapplicable to the ADS62P42/43/44/45/48/49, ADS62P22/23/24/25/28/29 and ADS62C15/17 analog todigital converters (ADC), which will be collectively referred to as ADS62PXX. This document should beused in combination with respective ADC data sheet. The ADS62PXX EVM provides a platform forevaluating the analog-to-digital converter (ADC) under various signal, clock, reference and power supplyconditions.
The ADS62PXXEVM provides numerous options for providing clock, input frequency and power to theADC under evaluation. The quick start procedure describes how to quickly get initial results using thedefault configuration of the EVM as it was shipped. The EVM can be put back to default configuration bysetting all jumpers to the default positions as described in Table 1 . The default configuration of the EVM isfor the Input Frequency (IF) and the clock input, each to be a single ended input that istransformer-coupled to the ADC. The default configuration for the power supply is to provide a single 5Vsupply to the red banana jack J10, PWR IN. The default configuration for the EVM is to control the modesof operation by jumper settings for parallel input control pins rather than serial SPI control of the registerspace. The other modes of operation of the EVM are described in the latter sections of this document. Ifusers modify the default jumper settings, this procedure does not apply.
A quick-setup procedure for the default configuration of the ADS62PXX follows:
1. Verify all the jumper settings against the schematic jumper list in Table 1 .2. Connect the 5V supply between J10 (PWR IN) and J12(GND). If you are using the TSW1200 forcapture, it also can be used to source 5V for the EVM. To use the 5V output power of the TSW1200,configure JP8 to short 1-2, J22 to short 1-2, and jumper over 5V from the banana jacks on theTSW1200 to J10 on the ADC EVM. Do not connect a voltage source greater than 5.5V.3. Switch on power supplies.4. Using a function generator with 50 Ωoutput impedance, generate a 0V offset, 1.5V
PP
sine-wave clockinto J19. The frequency of the clock must be within the specification for the device speed grade.5. Use a frequency generator with a 50 Ωoutput impedance, generate a 0V offset, –1 dBFS-amplitudesine-wave signal into J6 (Channel A) or J3 (Channel B).This provides a transformer-coupled differentialinput signal to the ADC.6. Connect the TSW1200 or suitable logic analyzer to J8 to capture the resulting digital data. If aTSW1200 is being used to capture data, follow the additional alphabetically labeled steps. For moredetails, see Connecting to FPGA Platforms , located in this document.a. After installing the TSW1200 software and connecting the TSW1200 to the USB port, open theTSW1200 software.b. Depending on the ADC under evaluation, select from the TI ADC Selection pull-down menu.c. Change the ADC Sample rate and ADC Input frequency to match those of the signal generator.d. After selecting a Single Tone FFT test, press the Capture Data button.
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Table 1. Jumper List
Jumper Function Default Jumper Setting
Interface Circuit Operational Amplifier THS4509 (Bypassed)
SJP1 AMP_OUT+ 1-2SJP2 AMP_OUT- 1-2JP3 THS4509_PD 2-3SJP5 AMPIN- 1-2SJP3 AMPIN+ No Shunt
ADC Circuit
JP11 Parallel 1-2JP9 SDATA 1-2JP10 SEN 1-2MODE (Internal or External reference and GainJP12 1-2selection)JP8 SCLK 1-2JP5 CTRL3 1-2JP6 CTRL2 1-2JP7 CTRL1 1-2JP13 No ShuntDFS (Data Format and LVDS/CMOS outputJP14 3-4interface)JP22 SDOUT/SPI-MISO Selection No Shunt
Clock Interface Circuit
J18 VCXO EN No ShuntSJP4 CLOCKIN 1-2SJP7 CLOCKIN, Y0, Y1P SELECT 1-2SJP6 YIN SELECT 1-2SJP8 PLL LOCK 1-2J15 RST (CDC Reset) No ShuntJ14 CDC_PWRDWN 1-2JP20 AUX SEL 1-2JP21 MODE_SEL 1-2
Power Supply
JP15 ADC VA 1-2JP18 ADC VD 1-2JP16 TPS79501 INPUT SELECT 1-2JP19 5V_AUX 1-2JP17 TPS5420 INPUT SELECT No Shunt
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2 Circuit Description
2.1 Schematic Diagram
2.2 ADC Circuit Function
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The schematic diagram for the this EVM is attached at the end of this document. See the schematic orrelevant section of this user's guide before changing any jumpers.
Selection of various modes of operation of the ADS62PXX EVM is most often controlled by jumpers on theEVM, either by placing shunts on 0.025-inch square jumper posts or by installation of surface mount 0 Ωresistors. In general, the use of 0 Ωresistors as jumpers are used in the clock or signal path where signalintegrity is critical, and jumper posts are used for static or low-speed control paths. Figure 1 shows therelative location of the jumpers, connectors, and switches used on the ADS62PXX EVM. Figure 2 showsthe relative locations of most of the resistors and surface-mount 0 Ωjumper locations used on the EVM. Inthe description of the circuit options in the following sections, each operational mode is accompanied by atable entry that details the jumper or resistor changes that enable that option. Figure 1 and Figure 2 canassist the user to quickly identify where these jumpers are located on the EVM.
Figure 1. ADS62PXX Jumpers
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2.2.1 ADC Operational Mode
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Figure 2. ADS62PXX Surface Jumpers
By default, the ADC is configured to operate in parallel-mode operation, since jumper (JP11) asserts a3.3V state to the ADC reset pin. Consequently, the SW1 reset pushbutton must be pressed only when thedevice is configured in serial operation mode. Since the ADC is in parallel operation mode, voltages areused to set the ADC configuration modes. Users can use the information printed on the EVM silkscreen toset the operation modes.
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2.2.2 EVM Power Connections
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Figure 3. ADS62PXXEVM Power Distribution
Power is supplied to the EVM through banana jacks. From this input power, several different ways ofdelivering power to the ADC and other EVM functions are available. Figure 3 shows a simplifiedrepresentation of the power options available for the ADS62PXXEVM. The default option is to provide 5Vto the red banana jack J10, and from there, the EVM generates 3.3V for the analog supply to the ADCand the necessary digital supply voltage for the populated ADC. The EVM also generates the propervoltages for optional features of the EVM such as the Clock Generation circuitry, the USB circuitry, andthe CMOS output buffer.
Some ADC devices that may be evaluated on the ADS62PXXEVM platform do not take 1.8V for the digitalsupply, but rather require 3.3V for the digital supply. For this reason, an adjustable voltage regulator waschosen for the digital supply; the output may be changed to 3.3V by changing the value of a resistor, R269and capacitor C148. The resistor and capacitor need not to be changed in the field unless the ADC isbeing changed, because the EVM ships with the correct digital supply voltage for the ADC that is installed.For reference, ADS62P42/43/44/45,ADS62P22/23/24/25 and ADS62C15 use 3.3V as digital supply for theADC whereas ADS62P48/49,ADS62P28/29 and ADS62C17 use 1.8V as digital supply for the ADC.
Power for the optional THS4509 operational amplifier is supplied by banana jacks J11 and J13. If theamplifier is being evaluated in AC coupled configuration, 5V is supplied to J11, and J13 is connected toground. In DC-coupled configuration, 4V is supplied to J11 and –1V is supplied to J13. Otherwise, theseinputs may be left unconnected.
Although various power options are available on this EVM, care must be taken while applying power onJ10 as different options have different voltage ranges specified. Table 2 displays the general jumpersetting information; Table 3 displays the various power option settings. Prior to making any jumpersettings, see the schematics located at the end of this document.
CAUTION
Voltage limits: Exceeding the maximum input voltages can damage EVMcomponents. Undervoltage can cause improper operation of some or all of theEVM components.
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2.2.2.1 Power Supply Option 1
2.2.2.2 Power Supply Option 2
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Table 2. EVM Power Supply Jumper Description
EVM Banana Jack Description Jumper
Setting 6V to 36V power supplyJ10 Input
default-apply just 5V1-2 →Connects 5.3V to input of TPS79501JP16 TPS79501 INPUT SELECT
2-3 →TPS79501 Input connected to J102-3 →TPS79501 output as 5V_AUX railsJP19 5V_AUX
1-2 →5V_AUX rail connected to J10JP17 TPS5420 INPUT SELECT Shunt →J10 connected to TPS5420D
Table 3. EVM Power Supply Options
EVM
Evaluation Goal Jumper Changes Required Voltage on J10 CommentsOption
JP16 →1-2Evaluate ADC performance using
JP19 →2-3 Maximuma cascaded switching power1 JP17 →1-2 6V - 36V performance andsupply (TPS5420D) and LDO
JP15 →1-2 efficiencysolution (TPS79501DCQ)
JP18 →1-2JP16 →1-2JP19 →1-2Evaluate ADC performance using Maximum2 JP17 →No Shunt 5.1V - 5.5Va LDO based solution PerformanceJP15 →1-2JP18 →1-2JP16 →No Shunt; JP19 →NoShuntEvaluate ADC performance using Isolated power supplyJP17 →No Shuntan isolated ADC AVDD and Do not apply power for current3 JP15 →Connect 3.3V to pin 2 ofDVDD for current consumption on J10 consumptionjumpermeasurements measurementsJP18 →Connect 1.8V to pin 2 ofjumper
Option 1 supplies the power to the ADC using cascaded topology of the TPS5420D switching powerregulator and the TPS79501DCQ Low Drop-Out regulator. The TPS5420 is a step-down converter whichworks with the input voltage in the range 6V to 36V. The switching supply increases efficiency for higherinput voltages but does create noise on the voltage supplies. To reduce the noise, an ultra-low-noise,high-PSSR LDO TPS79501DCQ is used to clean the power supply. The TPS5420D is designed for 5.3Voutput, which acts as a supply for the TPS79501. The TPS79501 is designed to output 5V, which is theAVDD for the ADC. This voltage rail is input to the LDO TPS79633, which outputs 3.3V, used for DVDDfor the ADC. A separate TPS79633 is designed to output 3.3V for the CDCE72010 supply rail. Thissolution adds two features to the EVM: one is to increase the range of the power supply on jumper J10from 6V to 36V, allowing the user to choose any power supply source in the specified range withoutcausing significant power dissipation. The other feature is that the output-voltage rail has a much lowerripple, allowing better performance of the part even when the power source is fluctuating.
Option 2 supplies power to the ADC using the LDOs TPS79633DCQ and TPS79601DCQ. The LDOs takea maximum input of 5.5V. When using this option, take care powering up the EVM, because highervoltage or reverse polarity can damage it. This is the default power-supply configuration for theADS62PXXEVM.
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2.2.2.3 Power Supply Option 3
2.2.3 ADC Analog Inputs
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Option 3 is used to evaluate ADC performance using an isolated AVDD and DVDD power supply forcurrent-consumption measurements. This option must be used with caution, because reversing the powersupply or connecting to the wrong connector can damage the EVM. One common use of this option is tomeasure the separate current consumption of the relative supplies under particular operating conditions.For this option, the shunts on jumpers JP18 and JP15 are removed and the input power is supplied to thecenter post of the jumper. For convenience, a ground post is provided next to the center post for headerconnections that contain power and ground on 0.1" centers.
The EVM can be configured to use either a transformer-coupled input or a TH4509 amplifier input, bothfrom a single-ended source. The SMA connector J6 (for Channel A) and J3 (for Channel B) provide thesingle-ended analog input to the transformer-coupled input circuit to the ADC. The SMA connector J7 andJ9 are not installed by default, but can be used to bring a differential input clock to thetransformer-coupled input or to bring a single ended input to the THS4509 input circuit. To use thetransformer for one of these options, the EVM must be configured for one of the options listed in Table 5 .See the schematic located at the end of this document prior to making any jumper changes.
Table 4. Analog Input Jumper description
EVM Banana Jack Description Jumper Setting
J6 Analog Input single-endedJ3 Analog Input single-endedAnalog input, can be used with J6 forJ7 Not populateddifferential inputAnalog input, can be used with J3 forJ9 Not populateddifferential input
2-3 →AMPOUT+ is selected as source of input to ADCSJP1 AMPOUT+, +ve terminal of T4 1-2 →Use analog input from J3 as signal source to ADC(use with appropriate SJP5 setting)2-3 →AMPOUT- is selected as source of input to ADCCSJP2 AMPOUT-, -ve terminal of T4 1-2 →Use analog input from J9 as signal source to AD(use with appropriate SJP3 setting1-2 →J3 supplies the analog signal to ADCSJP5 INPUT -ve select
2-3 →-ve input to amplifier1-2 →J9 supplies the analog signal to ADCSJP3 INPUT +ve select
2-3 →+ve input to amplifier DEFAULT is no shunt1-2 →Pulls up the pin (Normal operation or amplifier is ON)SP3 Power down for amplifier THS4509
2-3 →Grounds the pin (Low-power mode or amplifier is off)
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2.2.3.1 Analog Input Option 1
2.2.3.2 Analog Input Option 2
2.2.4 ADC Clock Input
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Table 5. EVM Analog Input Options
EVM Jumper Changes Voltage on J11Evaluation Goal Analog signal to ADC CommentsOption Required and J13
SJP1 →1-2Evaluate ADC SJP2 →1-2
From J6 (Channel A) or1 performance using direct SJP3 →No shunt Do not connect DefaultJ3 (Channel B)input to ADC SJP5 →1-2JP3 →2-3SJP1 →2-3SJP2 →2-3SJP3 →2-3Evaluate ADC Signal from J3 and J9 Used if inputSJP5 →2-3 J11 →5V2 performance using input is amplified by signal requiresJP3 →1-2 J13 →GNDthrough THS4509 THS4509 amplificationInstall J9Remove R63Install R62
Option 1 supplies the transformer-coupled input from J6 or J3 to the ADC. This configuration is the defaulton the EVM. The test result using this option is shown in Figure 10 . A double-transformer input circuit isused to provide better differential to single-ended conversion than a single transformer can provide. Thetransformers used are both of a 1:1 turns ratio, so termination of the 50 Ωinput signal path after thetransformers can be two 25 Ωresistors terminated to the Common Mode Voltage (VCM) provided by theADC.
Following the transformer coupling, surface mount pads are provided for several input circuits. By default,the input circuit is configured as shown in the ADS62PXX data sheet under the recommended input circuitfor high-bandwidth (>100 MHz IF) inputs. However, the recommended low-bandwidth input circuit for theADS62PXX can be implemented on the surface mount pads provided.
Option 2 allows the use of an amplifier to provide input to the ADC. TI has a range of widebandoperational amplifiers such as THS4508/09/11/13/20. On this EVM, THS4509 is used as an example toamplify the input from J3 or J9. The THS4509 is powered up by applying 5 V to J11 and GND to J13 (forAC coupled configuration). A differential power supply (4V applied to J11 and -1V applied to J13) may alsobe used to power up the amplifier if common-mode biasing is an issue for DC-coupled applications. Seethe THS4509 data sheet (SLOS547 ). The output of the THS4509 is filtered through a band-pass filterbefore ADC input. The band-pass filter can be designed depending on the end application. By default, theband-pass filter components are not populated because the filter design depends on the end application.The TI schematic provides an example of a filter that is designed for the frequency band of 10 MHz to 58MHz. When using the suggested filter, be sure to consider the proper value for R5, R6, R11 and R12resistors, because the ADC may impose limits on how large these resistors may be while the amplifiermay impose limits on how low an impedance it can drive. A key point when designing a filter is to design itfor proper load termination. Care must be taken when supplying the input to the board; the sourceimpedance must be 50 Ω. Results can vary due to mismatching of the various source and terminationimpedances.
The clock can be supplied to the ADC in one of several ways. The default clocking option is to supply asingle ended clock directly to the SMA connecter J19 directly, and this clock is converted to differentialand AC coupled to the ADC by transformer coupling. The clock input must be from a clean, low-jittersource and is commonly filtered by a narrow bandpass filter. The clock amplitude is commonly set toabout 1.5V peak to peak, and the amplitude offset is not an issue due to the AC coupling of the clockinput. The clock source is commonly synchronized with the input frequency signal generator to keep theclock and IF coherent for meaningful FFT analysis.
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Alternatively, the clock may be supplied by an onboard VCXO and CDCE72010 clock buffer. TheCDCE72010 Clock Buffer has been factory programmed to output a clock to the ADC that is 1/4 the rateof the on-board VCXO. While using this clock option, a separate 20MHz reference clock must be suppliedto the CDCE72010 by way of the Clock Input SMA connector J19 (Surface jumper SJP4 should beshorted to position 2-3 for this case). From the CDCE7201 two clocking options to the ADC are possible.A differential LVPECL clock output may be connected to the ADC clock input or a single-ended CMOSclock from the CDCE72010 may be routed to the ADC transformer-coupled clock input through anon-board crystal filter. For better performance, selecting the CMOS clock through a crystal output isrecommended. Prior to making any jumper settings, see the schematic located at the end of thisdocument. Table 6 displays the various clock option settings. The VCXO and crystal filter do not comepopulated on the EVM by default, although the CDCE72010 Clock buffer is installed.
Table 6. Clock Input Jumper Description
EVM Banana Jack Description Jumper Setting
1-2 →VCXO enabledJ18 ENABLE VCXO TCO-2111
2-3 →VCXO disabled Default is no shuntJ19 Clock Input
1-2 →CDCE72010 is power downJ14 CDCE72010 power down
Open →CDCE72010 is on1-2 →ResetJ15 CDCE72010 Reset
Open →Normal operation (Default)1-2 →J19 supplies clock directly to ADCSJP4 Clock In or CDC reference Jumper
2-3 →Reference clock for CDCE720101-2 →Connects J19 to ADC3-4 →Connects Yo output of CDCE72010Clock input +ve terminal of T6 for ADCSJP7 (This path has crystal filter) to ADCclock
5-6 →Connects Y1P(Differential LVPECL clock output of CDCE72010)1-2 →Connects to ground (default)Clock input +ve terminal of T4 for ADC 2-3 →Connects to Y1NSJP6
clock (Differential clock output of CDCE72010) only to be used withY1P1-2 →High (Default), see data sheet of CDCE72010 (SCAS858 )JP21 Mode select pin for CDCE72010
2-3 →Ground1-2 →Connects to D3 diodeSJP8 PLLLOCK LED
2-3 →Ground through 10nF capacitor1-2 →High, see data sheet of CDCE72010JP20 AUX_SEL pin for CDCE72010
2-3 →Ground (Default)
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2.2.4.1 Clock Option 1
2.2.4.2 Clock Option 2
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Table 7. EVM Clock Input Options
Jumper Changes Frequency Input CDC ConfigurationEVM Option Evaluation Goal CommentsRequired on J19 Description
J18 →2-3SJP4 →1-2Evaluate ADC
SJP7 →1-2 ADC’s Sampling1 performance using a NA DefaultSJP6 →1-2 Frequencysinusoid clock
J14 →1-2J15 →No shuntJ18 →1-2Evaluate ADC
SJP4 →2-3performance using a
SJP7 →3-4 20M for VCXO at Divide VCXO frequency Maximum2 crystal filtered LVCMOS
SJP6 →1-2 983.04 MHz by 4, output on Y0 performanceclock derived from
J14 →No ShuntCDCE72010
J15 →No ShuntJ18 →1-2Evaluate ADC SJP4 →2-3 Divide VCXO frequency
Notperformance using a SJP7 →5-6 20M for VCXO at by 4, differential3 recommended fordifferential LVCEPL SJP6 →2-3 983.04 MHz LVPECL Clock output
most applicationsclock J14 →No Shunt on Y1P and Y1NJ15 →No Shunt
The Clock Option 1 provides a clock to ADC directly from an external source. For the direct supply of theclock to the ADC, a single-ended square or sinusoidal clock input must be applied to J19. The clockfrequency must be within the maximum frequency specified for the ADC. The clock input is converted to adifferential signal by a Mini-Circuits™ ADT4-1WT, which has an impedance ratio of 4, implying thatvoltage applied on J19 is stepped up by a factor of 2. ADC performance in this case depends on the clocksource quality. This option is also the default configuration on the EVM, when it is shipped from thefactory. The test result using this option is shown in Figure 10 .
Option 2 uses the onboard VCXO and CDCE72010 to provide a clock to the ADC. The CDCE72010 isused in SPI mode which uses the internal EEPROM to configure the CDCE72010. The EEPROM isprogrammed in the factory for a divide-by-4 configuration. The EEPROM configuration is shown inFigure 4 . The clock at J19 is the reference clock for CDCE72010. The VCXO frequency can be calculatedas Fvcxo = Fout x 4 (Fout is the frequency output U0 and U1). The reference clock for CDCE72010 iscalculated from Ref Clock = (Fvcxo x 125)/(48 x 128). This is the clock-to-M divider. When VCXO offrequency 983.04 MHz is used, the calculation results in a reference clock of 20 MHz; the clock output onY0 pin of CDCE72010 is 245.76 MHz. This clock is filtered using the crystal filter with center frequency of245.76 MHz. By default, the VCXO and the crystal filter are not populated on the EVM, so that the usercan populate the components depending on the end application and sampling rate. This configuration isrecommended for applications requiring an onboard clock generation scheme. The test result using thisoption is shown in Figure 11 .
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2.2.4.3 Clock Option 3
2.2.5 ADC Digital Outputs
2.2.6 LEDs on the EVM
Circuit Description www.ti.com
Figure 4. CDCE72010 EEPROM Configuration Block Diagram
Option 3 is used for a differential LVPECL clock. This configuration eliminates the need for a crystal filter.It uses the same EEPROM configuration as Option 2, but in this case, the ADC clock pins are connectedto Y1N and Y1P. The jumper setting uses the clock output Y1P and Y1N from CDCE72010, to clock ADC.This configuration is not recommended for SNR critical applications. Notice that the clock frequency doesnot change. The frequency remains the same as in Clock Option 2. The test result using this option isshown in Figure 12 .
The LVDS digital outputs can be accessed through the J8 output connector. A parallel 100- Ωterminationresistor must be placed at the receiver to properly terminate each LVDS data pair. These resistors arerequired if the user wants to analyze the signals on an oscilloscope or a logic analyzer. The ADCperformance also can be quickly evaluated using the TSW1200 boards as explained in the next section.The TSW1200 will automatically terminate the LVDS outputs once the TSW1200 is connected to J8.
The ADS62PXX and most other ADCs that may be evaluated on this EVM also have an option to outputthe digitized parallel data in the form of single-ended CMOS. If single-ended CMOS is desired, headerpost connectors J1 and J2 are provided for the CMOS output. In order to use the header J1, a CMOSbuffer U12 must be installed in place of a bank of 0-ohm resistors that by default steer the outputs to theLVDS connector J8. And in order to use the header J2, a CMOS buffer U13 must be installed in place of abank of 0-ohm resistors that by default steer the outputs to the LVDS connector J8.
There are four LEDs on the EVM. LED D4 is named as ADC VD; this LED illuminates when the 3.3Vdigital supply is available to the ADC by setting jumper JP18 to position 1-2. Similarly, LED D5 (ADC VA)illuminates when the 3.3V analog supply is available to the ADC by setting jumper JP15 to position 1-2.LED D6 is 3.3V AUX, which illuminates when the 33V auxiliary supply is available from TPS79633. LEDD3 is the PLL LOCK LED. This LED illuminates when the CDC72010 PLL is locked.
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3 TI ADC SPI Control Interface
3.1 Installing the ADC SPI Control Software
www.ti.com TI ADC SPI Control Interface
This section describes the software features of the EVM kit. The TI ADC SPI control software provides fullcontrol of the SPI interface, allowing users to write to any of the ADC registers found in the data sheet.For most ADS62PXX performance evaluations, users do not need to use the TI SPI control software.Users only need to use the ADC SPI control software when the desired feature is inaccessible through theADC parallel interface mode.
The ADC SPI control software can be installed on a personal computer by running the setup.exe filelocated on the CD. This file installs the graphical user interface (GUI) along with the USB drivers neededto communicate to the USB port that resides on the EVM. When prompted, users should allow theWindows
®
operating system to search for device drivers by checking "Yes, this time only", as seen inFigure 5 . It will find the TI ADC SPI interface drivers automatically. After the software is installed, insert theUSB cable to the EVM to finish the installation . The "Found New Hardware" wizard will start, and youmust acknowledge that the TI ADC SPI Interface has not passed the Windows
®
Logo testing as shown inFigure 6 . After completion, the TI ADC SPI Interface should show up in the Hardware Device Manager.Figure 7 shows the SPI interface in the Hardware Manager which indicates that it is ready for use.
Note: Before plugging in the USB cable for the first time, install the TI ADC SPI software. Thesoftware installs the drivers necessary for USB communication.
Figure 5. Found New Hardware
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3.2 Setting Up the EVM for ADC SPI Control
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Figure 6. Window Logo Testing
Figure 7. Hardware Device Manager
Users who wish to use the ADC SPI interface must supply 5 VDC to P5, which provides power to the USBcircuit. By default, the EVM comes with the ADC configured in parallel mode. In order to use the SPIinterface to control the ADC modes of operation, users must move several jumpers.•Move jumper JP11 to short positions 2–3, which places the ADC into serial operation mode.•Move jumper JP8 to short positions 2–3, which allows the USB circuit to control SCLK.•Move jumper JP9 to short positions 2–3, which allows the USB circuit to control SDATA.•Move jumper JP10 to short positions 2–3, which allows the USB circuit to control SEN.
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3.3 Using the TI ADC SPI Interface Software
www.ti.com TI ADC SPI Control Interface
Once the software is installed and the USB cable is connected, three primary modes of operating thesoftware are available: SPI Register Writes, SPI Register Write Using a Script File, and ADS62PXXFrequently Used Registers.
Note: Before beginning an ADC evaluation, users are required to reset the ADC. This can easily bedone by pressing the ADS62PXX Reset button found on the ADS62PXX tab. For mostADS62PXX evaluations that make use of the SPI interface, users should also assert theOverride Bit also found on the ADS62PXX tab. This will force the ADC to be configured bythe SPI interface only and it will ignore any board-level settings that may have been set.Please consult the datasheet for a full list of available functions in SPI interface mode.
Figure 8. SPI Interface Screen
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3.3.1 SPI Register Writes
3.3.2 SPI Register Write Using a Script File
3.3.2.1 ADS62PXX Frequently Used Registers
TI ADC SPI Control Interface www.ti.com
The most basic mode of operation allows full control of writing to individual register addresses. From thetabs at the top of the interface screen (Figure 8 ), select the ADS62PXX ADC. Next, type the AddressBytes(s) in hexadecimal (hex) and Data Byte(s) in hex, which can be found in the device data sheet.When you are ready to send this command to the ADC, either press "Enter" on your keyboard or press theSend Data button. The graph indicator is updated with the patterns sent to the ADC. The default inputs toboth the Address Byte(s) and Data Byte(s) fields are hex inputs as designated by the small xin thecontrol. Users can change the default input style by clicking on the "x" to binary, decimal, octal, or hex.Multiple register writes can be written simply by changing the contents of the Address Byte(s) and DataByte(s) field and pressing "Enter" or Send Data again. The ADC SPI History window will keep track of theregister writes performed in a session.
After the ADC is configured to the desired usage, users can save time in future ADC configurations bysaving a script file. By pressing the Save Script button, it dumps ADC SPI History window contents into atext file. Alternatively, users can edit the script file in a text editor. An example script file is located in the\\Install Directory\Script Files\ADS62PXX_LVDS_oBinary.txt which configures the ADC for use with theTSW1200. When ready to write the contents of the script file to the ADC, users can press the Load Scriptbutton and they will be prompted for the file location of their script file. The commands are sent to the ADCwhen the user acknowledges the selection of the file, however the graph indicator does not show multiplewrites. The ADC SPI History will update to show the register writes executed in the script file.
For ease of use, several buttons have been added that allow one-click register writes of commonly usedfeatures found in Table 8 . These are found in the ADS62PXX tab (note that there is one tab forADS62PX5/X4/X3/X2,one tab for ADS62Px9/X8 and one tab for ADS62C15/17, because thesecommands are specific to the ADS62PXX ADC only. The software writes to the ADC both the contents ofthe associated address and data when the button is clicked. When the ADS62PXX Reset button ispressed, it issues a software reset to the ADC, and it resets the button values to match the contents insideof the ADC. The graph indicator plots the SPI commands written to the ADC when a button has beenpressed.
Table 8. ADS62PXX Frequently Used Registers
Default Value Alternate Value
ADS62PXX ResetOver-ride bit: Off Over-ride bit: On2s Complement Straight BinaryCMOS DDR LVDSPowerdown: OFF Multiple Powerdown OptionsNo Course Gain 3.5-dB Course GainINT Reference EXT ReferenceBit-Wise (LVDS Only) Byte-WiseTest Mode: None Multiple OptionsFine Gain Multiple Options
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