Texas Instruments MSP430FR57 Series User manual

MSP430FR57xx Family
User's Guide
Literature Number: SLAU272C
May 2011–Revised November 2013

Contents
Preface ...................................................................................................................................... 24
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) ...................... 26
1.1 System Control Module (SYS) Introduction ............................................................................ 27
1.2 System Reset and Initialization .......................................................................................... 27
1.2.1 Device Initial Conditions After System Reset ................................................................. 29
1.3 Interrupts .................................................................................................................... 29
1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 30
1.3.2 SNMI Timing ...................................................................................................... 30
1.3.3 Maskable Interrupts .............................................................................................. 30
1.3.4 Interrupt Processing .............................................................................................. 31
1.3.5 Interrupt Nesting .................................................................................................. 32
1.3.6 Interrupt Vectors .................................................................................................. 32
1.3.7 SYS Interrupt Vector Generators ............................................................................... 33
1.4 Operating Modes .......................................................................................................... 35
1.4.1 Low-Power Modes and Clock Requests ...................................................................... 37
1.4.2 Entering and Exiting Low-Power Modes LPM0 Through LPM4 ............................................ 38
1.4.3 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 38
1.5 Principles for Low-Power Applications .................................................................................. 39
1.6 Connection of Unused Pins .............................................................................................. 40
1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 40
1.8 Configuring JTAG Pins ................................................................................................... 40
1.9 Vacant Memory Space .................................................................................................... 41
1.10 Boot Code .................................................................................................................. 41
1.11 Bootstrap Loader (BSL) .................................................................................................. 41
1.12 JTAG Mailbox (JMB) System ............................................................................................ 41
1.12.1 JMB Configuration ............................................................................................... 42
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox ................................................................ 42
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox ...................................................................... 42
1.12.4 JMB NMI Usage ................................................................................................. 42
1.13 JTAG and SBW Lock Mechanism Using the Electronic Fuse ....................................................... 42
1.13.1 JTAG and SBW Lock Without Password ..................................................................... 43
1.13.2 JTAG and SBW Lock With Password ........................................................................ 43
1.14 Device Descriptor Table .................................................................................................. 43
1.14.1 Identifying Device Type ......................................................................................... 44
1.14.2 TLV Descriptors ................................................................................................. 45
1.14.3 Calibration Values ............................................................................................... 46
1.15 SFR Registers ............................................................................................................. 49
1.15.1 SFRIE1 Register ................................................................................................. 50
1.15.2 SFRIFG1 Register ............................................................................................... 51
1.15.3 SFRRPCR Register ............................................................................................. 53
1.16 SYS Registers ............................................................................................................. 54
1.16.1 SYSCTL Register ................................................................................................ 55
1.16.2 SYSJMBC Register ............................................................................................. 56
1.16.3 SYSJMBI0 Register ............................................................................................. 57
1.16.4 SYSJMBI1 Register ............................................................................................. 57
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1.16.5 SYSJMBO0 Register ............................................................................................ 58
1.16.6 SYSJMBO1 Register ............................................................................................ 58
1.16.7 SYSUNIV Register .............................................................................................. 59
1.16.8 SYSSNIV Register .............................................................................................. 59
1.16.9 SYSRSTIV Register ............................................................................................. 60
2 Power Management Module and Supply Voltage Supervisor ................................................... 61
2.1 Power Management Module (PMM) Introduction ..................................................................... 62
2.2 PMM Operation ............................................................................................................ 63
2.2.1 VCORE and the Regulator ......................................................................................... 63
2.2.2 Supply Voltage Supervisor ...................................................................................... 63
2.2.3 Supply Voltage Supervisor - Power-Up ........................................................................ 64
2.2.4 LPM3.5, LPM4.5 .................................................................................................. 64
2.2.5 Brownout Reset (BOR) .......................................................................................... 64
2.2.6 RST/NMI ........................................................................................................... 64
2.2.7 PMM Interrupts ................................................................................................... 65
2.2.8 Port I/O Control ................................................................................................... 65
2.3 PMM Registers ............................................................................................................ 66
2.3.1 PMMCTL0 Register .............................................................................................. 67
2.3.2 PMMIFG Register ................................................................................................ 68
2.3.3 PM5CTL0 Register ............................................................................................... 69
3 Clock System (CS) ............................................................................................................. 70
3.1 Clock System Introduction ................................................................................................ 71
3.2 Clock System Operation .................................................................................................. 73
3.2.1 CS Module Features for Low-Power Applications ........................................................... 73
3.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................. 73
3.2.3 XT1 Oscillator ..................................................................................................... 73
3.2.4 XT2 Oscillator ..................................................................................................... 74
3.2.5 Digitally Controlled Oscillator (DCO) ........................................................................... 74
3.2.6 Operation From Low-Power Modes, Requested by Peripheral Modules ................................. 75
3.2.7 CS Module Fail-Safe Operation ................................................................................ 76
3.2.8 Synchronization of Clock Signals ............................................................................... 78
3.3 Module Oscillator (MODOSC) ........................................................................................... 78
3.3.1 MODOSC Operation ............................................................................................. 78
3.4 CS Registers ............................................................................................................... 79
3.4.1 CSCTL0 Register ................................................................................................. 80
3.4.2 CSCTL1 Register ................................................................................................. 81
3.4.3 CSCTL2 Register ................................................................................................. 82
3.4.4 CSCTL3 Register ................................................................................................. 83
3.4.5 CSCTL4 Register ................................................................................................. 84
3.4.6 CSCTL5 Register ................................................................................................. 85
3.4.7 CSCTL6 Register ................................................................................................. 86
4 CPUX ............................................................................................................................... 87
4.1 MSP430X CPU (CPUX) Introduction ................................................................................... 88
4.2 Interrupts .................................................................................................................... 90
4.3 CPU Registers ............................................................................................................. 91
4.3.1 Program Counter (PC) ........................................................................................... 91
4.3.2 Stack Pointer (SP) ................................................................................................ 91
4.3.3 Status Register (SR) ............................................................................................. 93
4.3.4 Constant Generator Registers (CG1 and CG2) .............................................................. 94
4.3.5 General-Purpose Registers (R4 to R15) ...................................................................... 95
4.4 Addressing Modes ......................................................................................................... 97
4.4.1 Register Mode .................................................................................................... 98
4.4.2 Indexed Mode ..................................................................................................... 99
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4.4.3 Symbolic Mode .................................................................................................. 103
4.4.4 Absolute Mode .................................................................................................. 108
4.4.5 Indirect Register Mode ......................................................................................... 110
4.4.6 Indirect Autoincrement Mode .................................................................................. 111
4.4.7 Immediate Mode ................................................................................................ 112
4.5 MSP430 and MSP430X Instructions .................................................................................. 114
4.5.1 MSP430 Instructions ............................................................................................ 114
4.5.2 MSP430X Extended Instructions .............................................................................. 119
4.6 Instruction Set Description .............................................................................................. 130
4.6.1 Extended Instruction Binary Descriptions .................................................................... 131
4.6.2 MSP430 Instructions ............................................................................................ 133
4.6.3 Extended Instructions .......................................................................................... 185
4.6.4 Address Instructions ............................................................................................ 228
5 FRAM Controller (FRCTL) ................................................................................................. 243
5.1 FRAM Introduction ....................................................................................................... 244
5.2 FRAM Organization ...................................................................................................... 244
5.3 FRCTL Module Operation .............................................................................................. 244
5.4 Programming FRAM Memory Devices ................................................................................ 245
5.4.1 Programming FRAM Memory by JTAG or Spy-Bi-Wire .................................................... 245
5.4.2 Programming FRAM Memory by Bootstrap Loader (BSL) ................................................ 245
5.4.3 Programming FRAM Memory by Custom Solution ......................................................... 245
5.5 Wait State Control ....................................................................................................... 245
5.5.1 Manual Wait State Control ..................................................................................... 245
5.5.2 Automatic Wait State Control .................................................................................. 246
5.5.3 Wait State and Cache Hit ...................................................................................... 246
5.5.4 Safe Access ..................................................................................................... 246
5.6 FRAM ECC ............................................................................................................... 246
5.7 FRCTL Registers ......................................................................................................... 247
5.7.1 FRCTL0 Register ............................................................................................... 248
5.7.2 GCCTL0 Register ............................................................................................... 249
5.7.3 GCCTL1 Register ............................................................................................... 250
6 Memory Protection Unit (MPU) .......................................................................................... 251
6.1 Memory Protection Unit (MPU) Introduction .......................................................................... 252
6.2 MPU Segments ........................................................................................................... 253
6.2.1 Main Memory Segments ....................................................................................... 253
6.2.2 Segment Border Setting ........................................................................................ 253
6.2.3 Information Memory ............................................................................................ 255
6.3 MPU Access Management Settings ................................................................................... 255
6.4 MPU Violations ........................................................................................................... 256
6.4.1 Interrupt Table and Reset Vector ............................................................................. 256
6.4.2 Violation Handling ............................................................................................... 256
6.5 MPU Registers ........................................................................................................... 257
6.5.1 MPUCTL0 Register ............................................................................................. 258
6.5.2 MPUCTL1 Register ............................................................................................. 259
6.5.3 MPUSEG Register .............................................................................................. 260
6.5.4 MPUSAM Register .............................................................................................. 261
6.5.5 MPUIV Register ................................................................................................. 263
7 DMA Controller ................................................................................................................ 264
7.1 Direct Memory Access (DMA) Introduction ........................................................................... 265
7.2 DMA Operation ........................................................................................................... 267
7.2.1 DMA Addressing Modes ....................................................................................... 267
7.2.2 DMA Transfer Modes ........................................................................................... 268
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7.2.3 Initiating DMA Transfers ....................................................................................... 274
7.2.4 Halting Executing Instructions for DMA Transfers .......................................................... 275
7.2.5 Stopping DMA Transfers ....................................................................................... 275
7.2.6 DMA Channel Priorities ........................................................................................ 275
7.2.7 DMA Transfer Cycle Time ..................................................................................... 276
7.2.8 Using DMA With System Interrupts ........................................................................... 276
7.2.9 DMA Controller Interrupts ...................................................................................... 276
7.2.10 Using the eUSCI_B I2C Module With the DMA Controller ................................................ 277
7.2.11 Using ADC10 With the DMA Controller ..................................................................... 278
7.3 DMA Registers ........................................................................................................... 279
7.3.1 DMACTL0 Register ............................................................................................. 281
7.3.2 DMACTL1 Register ............................................................................................. 282
7.3.3 DMACTL2 Register ............................................................................................. 283
7.3.4 DMACTL3 Register ............................................................................................. 284
7.3.5 DMACTL4 Register ............................................................................................. 285
7.3.6 DMAxCTL Register ............................................................................................. 286
7.3.7 DMAxSA Register ............................................................................................... 288
7.3.8 DMAxDA Register ............................................................................................... 289
7.3.9 DMAxSZ Register ............................................................................................... 290
7.3.10 DMAIV Register ................................................................................................ 291
8 Digital I/O ........................................................................................................................ 292
8.1 Digital I/O Introduction ................................................................................................... 293
8.2 Digital I/O Operation ..................................................................................................... 294
8.2.1 Input Registers (PxIN) .......................................................................................... 294
8.2.2 Output Registers (PxOUT) ..................................................................................... 294
8.2.3 Direction Registers (PxDIR) ................................................................................... 294
8.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 294
8.2.5 Function Select Registers (PxSEL0, PxSEL1) .............................................................. 295
8.2.6 Port Interrupts ................................................................................................... 295
8.3 I/O Configuration ......................................................................................................... 297
8.3.1 Configuration After Reset ...................................................................................... 297
8.3.2 Configuration of Unused Port Pins ........................................................................... 297
8.3.3 Configuration for LPMx.5 Low-Power Modes ............................................................... 298
8.4 Digital I/O Registers ..................................................................................................... 300
8.4.1 P1IV Register .................................................................................................... 313
8.4.2 P2IV Register .................................................................................................... 313
8.4.3 P3IV Register .................................................................................................... 314
8.4.4 P4IV Register .................................................................................................... 314
8.4.5 PxIN Register .................................................................................................... 315
8.4.6 PxOUT Register ................................................................................................. 315
8.4.7 PxDIR Register .................................................................................................. 315
8.4.8 PxREN Register ................................................................................................. 316
8.4.9 PxSEL0 Register ................................................................................................ 316
8.4.10 PxSEL1 Register ............................................................................................... 316
8.4.11 PxSELC Register .............................................................................................. 317
8.4.12 PxIES Register ................................................................................................. 317
8.4.13 PxIE Register ................................................................................................... 317
8.4.14 PxIFG Register ................................................................................................. 318
9 CRC Module .................................................................................................................... 319
9.1 Cyclic Redundancy Check (CRC) Module Introduction ............................................................. 320
9.2 CRC Standard and Bit Order ........................................................................................... 320
9.3 CRC Checksum Generation ............................................................................................ 321
9.3.1 CRC Implementation ........................................................................................... 321
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9.3.2 Assembler Examples ........................................................................................... 322
9.4 CRC Registers ........................................................................................................... 324
9.4.1 CRCDI Register ................................................................................................. 325
9.4.2 CRCDIRB Register ............................................................................................. 325
9.4.3 CRCINIRES Register ........................................................................................... 326
9.4.4 CRCRESR Register ............................................................................................ 326
10 Watchdog Timer (WDT_A) ................................................................................................. 327
10.1 WDT_A Introduction ..................................................................................................... 328
10.2 WDT_A Operation ....................................................................................................... 330
10.2.1 Watchdog Timer Counter (WDTCNT) ....................................................................... 330
10.2.2 Watchdog Mode ................................................................................................ 330
10.2.3 Interval Timer Mode ........................................................................................... 330
10.2.4 Watchdog Timer Interrupts ................................................................................... 330
10.2.5 Fail-Safe Features ............................................................................................. 331
10.2.6 Operation in Low-Power Modes ............................................................................. 331
10.3 WDT_A Registers ........................................................................................................ 332
10.3.1 WDTCTL Register ............................................................................................. 333
11 Timer_A .......................................................................................................................... 334
11.1 Timer_A Introduction .................................................................................................... 335
11.2 Timer_A Operation ....................................................................................................... 337
11.2.1 16-Bit Timer Counter .......................................................................................... 337
11.2.2 Starting the Timer .............................................................................................. 337
11.2.3 Timer Mode Control ........................................................................................... 338
11.2.4 Capture/Compare Blocks ..................................................................................... 341
11.2.5 Output Unit ...................................................................................................... 343
11.2.6 Timer_A Interrupts ............................................................................................. 347
11.3 Timer_A Registers ....................................................................................................... 349
11.3.1 TAxCTL Register ............................................................................................... 350
11.3.2 TAxR Register .................................................................................................. 351
11.3.3 TAxCCTLn Register ........................................................................................... 352
11.3.4 TAxCCRn Register ............................................................................................ 354
11.3.5 TAxIV Register ................................................................................................. 354
11.3.6 TAxEX0 Register ............................................................................................... 355
12 Timer_B .......................................................................................................................... 356
12.1 Timer_B Introduction .................................................................................................... 357
12.1.1 Similarities and Differences From Timer_A ................................................................ 357
12.2 Timer_B Operation ....................................................................................................... 359
12.2.1 16-Bit Timer Counter .......................................................................................... 359
12.2.2 Starting the Timer .............................................................................................. 359
12.2.3 Timer Mode Control ........................................................................................... 360
12.2.4 Capture/Compare Blocks ..................................................................................... 363
12.2.5 Output Unit ...................................................................................................... 366
12.2.6 Timer_B Interrupts ............................................................................................. 370
12.3 Timer_B Registers ....................................................................................................... 372
12.3.1 TBxCTL Register ............................................................................................... 373
12.3.2 TBxR Register .................................................................................................. 375
12.3.3 TBxCCTLn Register ........................................................................................... 376
12.3.4 TBxCCRn Register ............................................................................................ 378
12.3.5 TBxIV Register ................................................................................................. 379
12.3.6 TBxEX0 Register ............................................................................................... 380
13 Real-Time Clock B (RTC_B) ............................................................................................... 381
13.1 Real-Time Clock RTC_B Introduction ................................................................................. 382
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13.2 RTC_B Operation ........................................................................................................ 384
13.2.1 Real-Time Clock and Prescale Dividers .................................................................... 384
13.2.2 Real-Time Clock Alarm Function ............................................................................ 384
13.2.3 Reading or Writing Real-Time Clock Registers ............................................................ 385
13.2.4 Real-Time Clock Interrupts ................................................................................... 385
13.2.5 Real-Time Clock Calibration .................................................................................. 387
13.2.6 Real-Time Clock Operation in LPMx.5 Low-Power Mode ................................................ 388
13.3 RTC_B Registers ........................................................................................................ 389
13.3.1 RTCCTL0 Register ............................................................................................ 391
13.3.2 RTCCTL1 Register ............................................................................................ 392
13.3.3 RTCCTL2 Register ............................................................................................ 393
13.3.4 RTCCTL3 Register ............................................................................................ 393
13.3.5 RTCSEC Register – Hexadecimal Format ................................................................. 394
13.3.6 RTCSEC Register – BCD Format ........................................................................... 394
13.3.7 RTCMIN Register – Hexadecimal Format .................................................................. 395
13.3.8 RTCMIN Register – BCD Format ............................................................................ 395
13.3.9 RTCHOUR Register – Hexadecimal Format ............................................................... 396
13.3.10 RTCHOUR Register – BCD Format ....................................................................... 396
13.3.11 RTCDOW Register ........................................................................................... 397
13.3.12 RTCDAY Register – Hexadecimal Format ................................................................ 397
13.3.13 RTCDAY Register – BCD Format .......................................................................... 397
13.3.14 RTCMON Register – Hexadecimal Format ............................................................... 398
13.3.15 RTCMON Register – BCD Format ......................................................................... 398
13.3.16 RTCYEAR Register – Hexadecimal Format .............................................................. 399
13.3.17 RTCYEAR Register – BCD Format ........................................................................ 399
13.3.18 RTCAMIN Register – Hexadecimal Format ............................................................... 400
13.3.19 RTCAMIN Register – BCD Format ......................................................................... 400
13.3.20 RTCAHOUR Register – Hexadecimal Format ............................................................ 401
13.3.21 RTCAHOUR Register – BCD Format ...................................................................... 401
13.3.22 RTCADOW Register ......................................................................................... 402
13.3.23 RTCADAY Register – Hexadecimal Format .............................................................. 403
13.3.24 RTCADAY Register – BCD Format ........................................................................ 403
13.3.25 RTCPS0CTL Register ....................................................................................... 404
13.3.26 RTCPS1CTL Register ....................................................................................... 405
13.3.27 RTCPS0 Register ............................................................................................ 406
13.3.28 RTCPS1 Register ............................................................................................ 406
13.3.29 RTCIV Register ............................................................................................... 407
13.3.30 BIN2BCD Register ........................................................................................... 408
13.3.31 BCD2BIN Register ........................................................................................... 408
14 32-Bit Hardware Multiplier (MPY32) .................................................................................... 409
14.1 32-Bit Hardware Multiplier (MPY32) Introduction .................................................................... 410
14.2 MPY32 Operation ........................................................................................................ 412
14.2.1 Operand Registers ............................................................................................. 413
14.2.2 Result Registers ................................................................................................ 414
14.2.3 Software Examples ............................................................................................ 415
14.2.4 Fractional Numbers ............................................................................................ 416
14.2.5 Putting It All Together ......................................................................................... 419
14.2.6 Indirect Addressing of Result Registers ..................................................................... 422
14.2.7 Using Interrupts ................................................................................................ 422
14.2.8 Using DMA ...................................................................................................... 423
14.3 MPY32 Registers ........................................................................................................ 424
14.3.1 MPY32CTL0 Register ......................................................................................... 426
15 REF Module .................................................................................................................... 427
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15.1 REF Introduction ......................................................................................................... 428
15.2 Principle of Operation ................................................................................................... 429
15.2.1 Low-Power Operation ......................................................................................... 429
15.2.2 REFCTL ......................................................................................................... 429
15.2.3 Reference System Requests ................................................................................. 429
15.3 REF Registers ............................................................................................................ 431
15.3.1 REFCTL0 Register ............................................................................................. 432
16 ADC10_B Module ............................................................................................................. 433
16.1 ADC10_B Introduction ................................................................................................... 434
16.2 ADC10_B Operation ..................................................................................................... 436
16.2.1 10-Bit ADC Core ............................................................................................... 436
16.2.2 ADC10_B Inputs and Multiplexer ............................................................................ 436
16.2.3 Voltage Reference Generator ................................................................................ 437
16.2.4 Auto Power Down .............................................................................................. 437
16.2.5 Sample and Conversion Timing .............................................................................. 437
16.2.6 Conversion Result ............................................................................................. 439
16.2.7 ADC10_B Conversion Modes ................................................................................ 439
16.2.8 Window Comparator ........................................................................................... 444
16.2.9 Using the Integrated Temperature Sensor ................................................................. 445
16.2.10 ADC10_B Grounding and Noise Considerations ......................................................... 446
16.2.11 ADC10_B Interrupts .......................................................................................... 447
16.3 ADC10_B Registers ..................................................................................................... 449
16.3.1 ADC10CTL0 Register ......................................................................................... 450
16.3.2 ADC10CTL1 Register ......................................................................................... 452
16.3.3 ADC10CTL2 Register ......................................................................................... 454
16.3.4 ADC10MEM0 Register ........................................................................................ 455
16.3.5 ADC10MEM0 Register, 2s-Complement Format .......................................................... 455
16.3.6 ADC10MCTL0 Register ....................................................................................... 456
16.3.7 ADC10HI Register ............................................................................................. 457
16.3.8 ADC10HI Register, 2s-Complement Format ............................................................... 457
16.3.9 ADC10LO Register ............................................................................................ 458
16.3.10 ADC10LO Register, 2s-Complement Format ............................................................. 458
16.3.11 ADC10IE Register ............................................................................................ 459
16.3.12 ADC10IFG Register .......................................................................................... 460
16.3.13 ADC10IV Register ............................................................................................ 461
17 Comparator_D ................................................................................................................. 462
17.1 Comparator_D Introduction ............................................................................................. 463
17.2 Comparator_D Operation ............................................................................................... 464
17.2.1 Comparator ..................................................................................................... 464
17.2.2 Analog Input Switches ......................................................................................... 464
17.2.3 Port Logic ....................................................................................................... 464
17.2.4 Input Short Switch ............................................................................................. 464
17.2.5 Output Filter .................................................................................................... 465
17.2.6 Reference Voltage Generator ................................................................................ 466
17.2.7 Comparator_D, Port Disable Register CDPD .............................................................. 467
17.2.8 Comparator_D Interrupts ..................................................................................... 467
17.2.9 Comparator_D Used to Measure Resistive Elements .................................................... 467
17.3 Comparator_D Registers ................................................................................................ 469
17.3.1 CDCTL0 Register .............................................................................................. 470
17.3.2 CDCTL1 Register .............................................................................................. 471
17.3.3 CDCTL2 Register .............................................................................................. 472
17.3.4 CDCTL3 Register .............................................................................................. 473
17.3.5 CDINT Register ................................................................................................ 474
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17.3.6 CDIV Register .................................................................................................. 475
18 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode ........................... 476
18.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview .................................. 477
18.2 eUSCI_A Introduction – UART Mode ................................................................................. 477
18.3 eUSCI_A Operation – UART Mode .................................................................................... 479
18.3.1 eUSCI_A Initialization and Reset ............................................................................ 479
18.3.2 Character Format .............................................................................................. 479
18.3.3 Asynchronous Communication Format ..................................................................... 479
18.3.4 Automatic Baud-Rate Detection ............................................................................. 482
18.3.5 IrDA Encoding and Decoding ................................................................................ 483
18.3.6 Automatic Error Detection .................................................................................... 484
18.3.7 eUSCI_A Receive Enable .................................................................................... 485
18.3.8 eUSCI_A Transmit Enable .................................................................................... 485
18.3.9 UART Baud-Rate Generation ................................................................................ 486
18.3.10 Setting a Baud Rate .......................................................................................... 488
18.3.11 Transmit Bit Timing - Error calculation .................................................................... 489
18.3.12 Receive Bit Timing – Error Calculation .................................................................... 489
18.3.13 Typical Baud Rates and Errors ............................................................................. 490
18.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes ................................. 492
18.3.15 eUSCI_A Interrupts .......................................................................................... 492
18.4 eUSCI_A UART Registers .............................................................................................. 494
18.4.1 UCAxCTLW0 Register ........................................................................................ 495
18.4.2 UCAxCTLW1 Register ........................................................................................ 496
18.4.3 UCAxBRW Register ........................................................................................... 497
18.4.4 UCAxMCTLW Register ........................................................................................ 497
18.4.5 UCAxSTATW Register ........................................................................................ 498
18.4.6 UCAxRXBUF Register ........................................................................................ 499
18.4.7 UCAxTXBUF Register ......................................................................................... 499
18.4.8 UCAxABCTL Register ......................................................................................... 500
18.4.9 UCAxIRCTL Register .......................................................................................... 501
18.4.10 UCAxIE Register ............................................................................................. 502
18.4.11 UCAxIFG Register ........................................................................................... 503
18.4.12 UCAxIV Register ............................................................................................. 504
19 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode .............................. 505
19.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ....................... 506
19.2 eUSCI Introduction – SPI Mode ........................................................................................ 506
19.3 eUSCI Operation – SPI Mode .......................................................................................... 508
19.3.1 eUSCI Initialization and Reset ............................................................................... 508
19.3.2 Character Format .............................................................................................. 509
19.3.3 Master Mode .................................................................................................... 509
19.3.4 Slave Mode ..................................................................................................... 510
19.3.5 SPI Enable ...................................................................................................... 511
19.3.6 Serial Clock Control ........................................................................................... 511
19.3.7 Using the SPI Mode With Low-Power Modes .............................................................. 512
19.3.8 SPI Interrupts ................................................................................................... 512
19.4 eUSCI_A SPI Registers ................................................................................................. 514
19.4.1 UCAxCTLW0 Register ........................................................................................ 515
19.4.2 UCAxBRW Register ........................................................................................... 517
19.4.3 UCAxSTATW Register ........................................................................................ 518
19.4.4 UCAxRXBUF Register ........................................................................................ 519
19.4.5 UCAxTXBUF Register ......................................................................................... 520
19.4.6 UCAxIE Register ............................................................................................... 521
19.4.7 UCAxIFG Register ............................................................................................. 522
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19.4.8 UCAxIV Register ............................................................................................... 523
19.5 eUSCI_B SPI Registers ................................................................................................. 524
19.5.1 UCBxCTLW0 Register ........................................................................................ 525
19.5.2 UCBxBRW Register ........................................................................................... 527
19.5.3 UCBxSTATW Register ........................................................................................ 527
19.5.4 UCBxRXBUF Register ........................................................................................ 528
19.5.5 UCBxTXBUF Register ......................................................................................... 528
19.5.6 UCBxIE Register ............................................................................................... 529
19.5.7 UCBxIFG Register ............................................................................................. 529
19.5.8 UCBxIV Register ............................................................................................... 530
20 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode ............................... 531
20.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview .................................. 532
20.2 eUSCI_B Introduction – I2C Mode ..................................................................................... 532
20.3 eUSCI_B Operation – I2C Mode ....................................................................................... 533
20.3.1 eUSCI_B Initialization and Reset ............................................................................ 534
20.3.2 I2C Serial Data .................................................................................................. 534
20.3.3 I2C Addressing Modes ......................................................................................... 535
20.3.4 I2C Quick Setup ................................................................................................ 536
20.3.5 I2C Module Operating Modes ................................................................................. 537
20.3.6 Glitch Filtering .................................................................................................. 547
20.3.7 I2C Clock Generation and Synchronization ................................................................. 547
20.3.8 Byte Counter .................................................................................................... 548
20.3.9 Multiple Slave Addresses ..................................................................................... 549
20.3.10 Using the eUSCI_B Module in I2C Mode With Low-Power Modes ..................................... 549
20.3.11 eUSCI_B Interrupts in I2C Mode ............................................................................ 550
20.4 eUSCI_B I2C Registers ................................................................................................. 553
20.4.1 UCBxCTLW0 Register ........................................................................................ 554
20.4.2 UCBxCTLW1 Register ........................................................................................ 556
20.4.3 UCBxBRW Register ........................................................................................... 558
20.4.4 UCBxSTATW ................................................................................................... 558
20.4.5 UCBxTBCNT Register ........................................................................................ 559
20.4.6 UCBxRXBUF Register ........................................................................................ 560
20.4.7 UCBxTXBUF ................................................................................................... 560
20.4.8 UCBxI2COA0 Register ........................................................................................ 561
20.4.9 UCBxI2COA1 Register ........................................................................................ 562
20.4.10 UCBxI2COA2 Register ...................................................................................... 562
20.4.11 UCBxI2COA3 Register ...................................................................................... 563
20.4.12 UCBxADDRX Register ....................................................................................... 563
20.4.13 UCBxADDMASK Register ................................................................................... 564
20.4.14 UCBxI2CSA Register ........................................................................................ 564
20.4.15 UCBxIE Register ............................................................................................. 565
20.4.16 UCBxIFG Register ........................................................................................... 567
20.4.17 UCBxIV Register ............................................................................................. 569
21 Embedded Emulation Module (EEM) .................................................................................. 570
21.1 Embedded Emulation Module (EEM) Introduction ................................................................... 571
21.2 EEM Building Blocks .................................................................................................... 573
21.2.1 Triggers ......................................................................................................... 573
21.2.2 Trigger Sequencer ............................................................................................. 573
21.2.3 State Storage (Internal Trace Buffer) ........................................................................ 573
21.2.4 Cycle Counter .................................................................................................. 573
21.2.5 Clock Control ................................................................................................... 574
21.3 EEM Configurations ..................................................................................................... 574
Revision History ....................................................................................................................... 575
10 Contents SLAU272C–May 2011–Revised November 2013
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List of Figures
1-1. BOR, POR, and PUC Reset Circuit..................................................................................... 28
1-2. Interrupt Priority............................................................................................................ 29
1-3. Interrupt Processing....................................................................................................... 31
1-4. Return From Interrupt..................................................................................................... 32
1-5. Operation Modes .......................................................................................................... 36
1-6. Devices Descriptor Table................................................................................................. 44
1-7. SFRIE1 Register........................................................................................................... 50
1-8. SFRIFG1 Register......................................................................................................... 51
1-9. SFRRPCR Register....................................................................................................... 53
1-10. SYSCTL Register.......................................................................................................... 55
1-11. SYSJMBC Register ....................................................................................................... 56
1-12. SYSJMBI0 Register....................................................................................................... 57
1-13. SYSJMBI1 Register....................................................................................................... 57
1-14. SYSJMBO0 Register...................................................................................................... 58
1-15. SYSJMBO1 Register...................................................................................................... 58
1-16. SYSUNIV Register ........................................................................................................ 59
1-17. SYSSNIV Register ........................................................................................................ 59
1-18. SYSRSTIV Register....................................................................................................... 60
2-1. PMM Block Diagram ...................................................................................................... 62
2-2. High-Side and Low-Side Voltage Failure and Resulting PMM Actions............................................. 63
2-3. PMM Action at Device Power-Up ....................................................................................... 64
2-4. PMMCTL0 Register ....................................................................................................... 67
2-5. PMMIFG Register ......................................................................................................... 68
2-6. PM5CTL0 Register........................................................................................................ 69
3-1. Clock System Block Diagram............................................................................................ 72
3-2. Module Request Clock System.......................................................................................... 75
3-3. Oscillator Fault Logic...................................................................................................... 77
3-4. Switch MCLK from DCOCLK to XT1CLK .............................................................................. 78
3-5. CSCTL0 Register.......................................................................................................... 80
3-6. CSCTL1 Register.......................................................................................................... 81
3-7. CSCTL2 Register.......................................................................................................... 82
3-8. CSCTL3 Register.......................................................................................................... 83
3-9. CSCTL4 Register.......................................................................................................... 84
3-10. CSCTL5 Register.......................................................................................................... 85
3-11. CSCTL6 Register.......................................................................................................... 86
4-1. MSP430X CPU Block Diagram.......................................................................................... 89
4-2. PC Storage on the Stack for Interrupts................................................................................. 90
4-3. Program Counter .......................................................................................................... 91
4-4. PC Storage on the Stack for CALLA.................................................................................... 91
4-5. Stack Pointer............................................................................................................... 92
4-6. Stack Usage................................................................................................................ 92
4-7. PUSHX.A Format on the Stack.......................................................................................... 92
4-8. PUSH SP, POP SP Sequence .......................................................................................... 92
4-9. SR Bits...................................................................................................................... 93
4-10. Register-Byte and Byte-Register Operation ........................................................................... 95
4-11. Register-Word Operation................................................................................................. 95
4-12. Word-Register Operation................................................................................................. 96
11
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4-13. Register – Address-Word Operation.................................................................................... 96
4-14. Address-Word – Register Operation.................................................................................... 97
4-15. Indexed Mode in Lower 64 KB........................................................................................... 99
4-16. Indexed Mode in Upper Memory....................................................................................... 100
4-17. Overflow and Underflow for Indexed Mode........................................................................... 101
4-18. Example for Indexed Mode............................................................................................. 102
4-19. Symbolic Mode Running in Lower 64 KB............................................................................. 104
4-20. Symbolic Mode Running in Upper Memory .......................................................................... 105
4-21. Overflow and Underflow for Symbolic Mode ......................................................................... 106
4-22. MSP430 Double-Operand Instruction Format........................................................................ 114
4-23. MSP430 Single-Operand Instructions................................................................................. 115
4-24. Format of Conditional Jump Instructions.............................................................................. 116
4-25. Extension Word for Register Modes................................................................................... 119
4-26. Extension Word for Non-Register Modes............................................................................. 119
4-27. Example for Extended Register or Register Instruction............................................................. 120
4-28. Example for Extended Immediate or Indexed Instruction........................................................... 121
4-29. Extended Format I Instruction Formats ............................................................................... 122
4-30. 20-Bit Addresses in Memory ........................................................................................... 122
4-31. Extended Format II Instruction Format................................................................................ 123
4-32. PUSHM and POPM Instruction Format............................................................................... 124
4-33. RRCM, RRAM, RRUM, and RLAM Instruction Format ............................................................. 124
4-34. BRA Instruction Format ................................................................................................. 124
4-35. CALLA Instruction Format .............................................................................................. 124
4-36. Decrement Overlap...................................................................................................... 150
4-37. Stack After a RET Instruction .......................................................................................... 169
4-38. Destination Operand—Arithmetic Shift Left .......................................................................... 171
4-39. Destination Operand—Carry Left Shift................................................................................ 172
4-40. Rotate Right Arithmetically RRA.B and RRA.W ..................................................................... 173
4-41. Rotate Right Through Carry RRC.B and RRC.W.................................................................... 174
4-42. Swap Bytes in Memory.................................................................................................. 181
4-43. Swap Bytes in a Register ............................................................................................... 181
4-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A ................................................................ 208
4-45. Destination Operand-Arithmetic Shift Left ............................................................................ 209
4-46. Destination Operand-Carry Left Shift.................................................................................. 210
4-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A ............................................................... 211
4-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode......................................................... 213
4-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode................................................... 213
4-50. Rotate Right Through Carry RRCM[.W] and RRCM.A.............................................................. 215
4-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode ....................................................... 217
4-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode ................................................. 217
4-53. Rotate Right Unsigned RRUM[.W] and RRUM.A.................................................................... 218
4-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode ............................................................. 219
4-55. Swap Bytes SWPBX.A Register Mode................................................................................ 223
4-56. Swap Bytes SWPBX.A In Memory .................................................................................... 223
4-57. Swap Bytes SWPBX[.W] Register Mode ............................................................................. 224
4-58. Swap Bytes SWPBX[.W] In Memory .................................................................................. 224
4-59. Sign Extend SXTX.A .................................................................................................... 225
4-60. Sign Extend SXTX[.W] .................................................................................................. 225
5-1. FRAM Controller Block Diagram....................................................................................... 244
12 List of Figures SLAU272C–May 2011–Revised November 2013
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5-2. FRCTL0 Register ........................................................................................................ 248
5-3. GCCTL0 Register........................................................................................................ 249
5-4. GCCTL1 Register........................................................................................................ 250
6-1. Memory Protection Unit Overview ..................................................................................... 252
6-2. Segmentation of Main Memory......................................................................................... 253
6-3. MPUCTL0 Register...................................................................................................... 258
6-4. MPUCTL1 Register...................................................................................................... 259
6-5. MPUSEG Register....................................................................................................... 260
6-6. MPUSAM Register....................................................................................................... 261
6-7. MPUIV Register.......................................................................................................... 263
7-1. DMA Controller Block Diagram......................................................................................... 266
7-2. DMA Addressing Modes ................................................................................................ 267
7-3. DMA Single Transfer State Diagram .................................................................................. 269
7-4. DMA Block Transfer State Diagram................................................................................... 271
7-5. DMA Burst-Block Transfer State Diagram............................................................................ 273
7-6. DMACTL0 Register...................................................................................................... 281
7-7. DMACTL1 Register...................................................................................................... 282
7-8. DMACTL2 Register...................................................................................................... 283
7-9. DMACTL3 Register...................................................................................................... 284
7-10. DMACTL4 Register...................................................................................................... 285
7-11. DMAxCTL Register ...................................................................................................... 286
7-12. DMAxSA Register........................................................................................................ 288
7-13. DMAxDA Register........................................................................................................ 289
7-14. DMAxSZ Register........................................................................................................ 290
7-15. DMAIV Register.......................................................................................................... 291
8-1. P1IV Register............................................................................................................. 313
8-2. P2IV Register............................................................................................................. 313
8-3. P3IV Register............................................................................................................. 314
8-4. P4IV Register............................................................................................................. 314
8-5. PxIN Register............................................................................................................. 315
8-6. PxOUT Register.......................................................................................................... 315
8-7. PxDIR Register........................................................................................................... 315
8-8. PxREN Register.......................................................................................................... 316
8-9. PxSEL0 Register......................................................................................................... 316
8-10. PxSEL1 Register......................................................................................................... 316
8-11. PxSELC Register ........................................................................................................ 317
8-12. PxIES Register ........................................................................................................... 317
8-13. PxIE Register............................................................................................................. 317
8-14. PxIFG Register........................................................................................................... 318
9-1. LFSR Implementation of CRC-CCITT Standard, Bit 0 is the MSB of the Result................................ 320
9-2. Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers.................................. 322
9-3. CRCDI Register.......................................................................................................... 325
9-4. CRCDIRB Register ...................................................................................................... 325
9-5. CRCINIRES Register.................................................................................................... 326
9-6. CRCRESR Register ..................................................................................................... 326
10-1. Watchdog Timer Block Diagram ....................................................................................... 329
10-2. WDTCTL Register ....................................................................................................... 333
11-1. Timer_A Block Diagram................................................................................................. 336
11-2. Up Mode .................................................................................................................. 338
13
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11-3. Up Mode Flag Setting ................................................................................................... 338
11-4. Continuous Mode ........................................................................................................ 339
11-5. Continuous Mode Flag Setting......................................................................................... 339
11-6. Continuous Mode Time Intervals ...................................................................................... 339
11-7. Up/Down Mode........................................................................................................... 340
11-8. Up/Down Mode Flag Setting............................................................................................ 340
11-9. Output Unit in Up/Down Mode ......................................................................................... 341
11-10. Capture Signal (SCS = 1)............................................................................................... 342
11-11. Capture Cycle ............................................................................................................ 342
11-12. Output Example – Timer in Up Mode ................................................................................. 344
11-13. Output Example – Timer in Continuous Mode ....................................................................... 345
11-14. Output Example – Timer in Up/Down Mode.......................................................................... 346
11-15. Capture/Compare Interrupt Flag ....................................................................................... 347
11-16. TAxCTL Register......................................................................................................... 350
11-17. TAxR Register............................................................................................................ 351
11-18. TAxCCTLn Register ..................................................................................................... 352
11-19. TAxCCRn Register ...................................................................................................... 354
11-20. TAxIV Register ........................................................................................................... 354
11-21. TAxEX0 Register......................................................................................................... 355
12-1. Timer_B Block Diagram................................................................................................. 358
12-2. Up Mode .................................................................................................................. 360
12-3. Up Mode Flag Setting ................................................................................................... 360
12-4. Continuous Mode ........................................................................................................ 361
12-5. Continuous Mode Flag Setting......................................................................................... 361
12-6. Continuous Mode Time Intervals ...................................................................................... 361
12-7. Up/Down Mode........................................................................................................... 362
12-8. Up/Down Mode Flag Setting............................................................................................ 362
12-9. Output Unit in Up/Down Mode ......................................................................................... 363
12-10. Capture Signal (SCS = 1)............................................................................................... 364
12-11. Capture Cycle ............................................................................................................ 364
12-12. Output Example – Timer in Up Mode ................................................................................. 367
12-13. Output Example – Timer in Continuous Mode ....................................................................... 368
12-14. Output Example – Timer in Up/Down Mode.......................................................................... 369
12-15. Capture/Compare TBxCCR0 Interrupt Flag .......................................................................... 370
12-16. TBxCTL Register......................................................................................................... 373
12-17. TBxR Register............................................................................................................ 375
12-18. TBxCCTLn Register ..................................................................................................... 376
12-19. TBxCCRn Register ...................................................................................................... 378
12-20. TBxIV Register ........................................................................................................... 379
12-21. TBxEX0 Register......................................................................................................... 380
13-1. RTC_B Block Diagram .................................................................................................. 383
13-2. RTCCTL0 Register ...................................................................................................... 391
13-3. RTCCTL1 Register ...................................................................................................... 392
13-4. RTCCTL2 Register ...................................................................................................... 393
13-5. RTCCTL3 Register ...................................................................................................... 393
13-6. RTCSEC Register........................................................................................................ 394
13-7. RTCSEC Register........................................................................................................ 394
13-8. RTCMIN Register ........................................................................................................ 395
13-9. RTCMIN Register ........................................................................................................ 395
14 List of Figures SLAU272C–May 2011–Revised November 2013
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13-10. RTCHOUR Register ..................................................................................................... 396
13-11. RTCHOUR Register ..................................................................................................... 396
13-12. RTCDOW Register ...................................................................................................... 397
13-13. RTCDAY Register........................................................................................................ 397
13-14. RTCDAY Register........................................................................................................ 397
13-15. RTCMON Register....................................................................................................... 398
13-16. RTCMON Register....................................................................................................... 398
13-17. RTCYEAR Register...................................................................................................... 399
13-18. RTCYEAR Register...................................................................................................... 399
13-19. RTCAMIN Register ...................................................................................................... 400
13-20. RTCAMIN Register ...................................................................................................... 400
13-21. RTCAHOUR Register ................................................................................................... 401
13-22. RTCAHOUR Register ................................................................................................... 401
13-23. RTCADOW Register..................................................................................................... 402
13-24. RTCADAY Register...................................................................................................... 403
13-25. RTCADAY Register...................................................................................................... 403
13-26. RTCPS0CTL Register................................................................................................... 404
13-27. RTCPS1CTL Register................................................................................................... 405
13-28. RTCPS0 Register........................................................................................................ 406
13-29. RTCPS1 Register........................................................................................................ 406
13-30. RTCIV Register........................................................................................................... 407
13-31. BIN2BCD Register....................................................................................................... 408
13-32. BCD2BIN Register....................................................................................................... 408
14-1. MPY32 Block Diagram .................................................................................................. 411
14-2. Q15 Format Representation............................................................................................ 416
14-3. Q14 Format Representation............................................................................................ 416
14-4. Saturation Flow Chart ................................................................................................... 418
14-5. Multiplication Flow Chart................................................................................................ 420
14-6. MPY32CTL0 Register ................................................................................................... 426
15-1. REF Block Diagram...................................................................................................... 428
15-2. REFCTL0 Register....................................................................................................... 432
16-1. ADC10_B Block Diagram............................................................................................... 435
16-2. Analog Multiplexer ....................................................................................................... 436
16-3. Extended Sample Mode................................................................................................. 438
16-4. Pulse Sample Mode ..................................................................................................... 438
16-5. Analog Input Equivalent Circuit ........................................................................................ 439
16-6. Single-Channel Single-Conversion Mode............................................................................. 440
16-7. Sequence-of-Channels Mode .......................................................................................... 441
16-8. Repeat-Single-Channel Mode.......................................................................................... 442
16-9. Repeat-Sequence-of-Channels Mode................................................................................. 443
16-10. Typical Temperature Sensor Transfer Function ..................................................................... 445
16-11. ADC10_B Grounding and Noise Considerations .................................................................... 446
16-12. ADC10CTL0 Register ................................................................................................... 450
16-13. ADC10CTL1 Register ................................................................................................... 452
16-14. ADC10CTL2 Register ................................................................................................... 454
16-15. ADC10MEM0 Register .................................................................................................. 455
16-16. ADC10MEM0 Register .................................................................................................. 455
16-17. ADC10MCTL0 Register................................................................................................. 456
16-18. ADC10HI Register ....................................................................................................... 457
15
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16-19. ADC10HI Register ....................................................................................................... 457
16-20. ADC10LO Register ...................................................................................................... 458
16-21. ADC10LO Register ...................................................................................................... 458
16-22. ADC10IE Register ....................................................................................................... 459
16-23. ADC10IFG Register ..................................................................................................... 460
16-24. ADC10IV Register ....................................................................................................... 461
17-1. Comparator_D Block Diagram ......................................................................................... 463
17-2. Comparator_D Sample-And-Hold...................................................................................... 465
17-3. RC-Filter Response at the Output of the Comparator............................................................... 466
17-4. Reference Generator Block Diagram.................................................................................. 466
17-5. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer ...................................... 467
17-6. Temperature Measurement System................................................................................... 467
17-7. Timing for Temperature Measurement Systems..................................................................... 468
17-8. CDCTL0 Register ........................................................................................................ 470
17-9. CDCTL1 Register ........................................................................................................ 471
17-10. CDCTL2 Register ........................................................................................................ 472
17-11. CDCTL3 Register ........................................................................................................ 473
17-12. CDINT Register .......................................................................................................... 474
17-13. CDIV Register ............................................................................................................ 475
18-1. eUSCI_Ax Block Diagram – UART Mode (UCSYNC = 0).......................................................... 478
18-2. Character Format ........................................................................................................ 479
18-3. Idle-Line Format.......................................................................................................... 480
18-4. Address-Bit Multiprocessor Format.................................................................................... 481
18-5. Auto Baud-Rate Detection – Break/Synch Sequence............................................................... 482
18-6. Auto Baud-Rate Detection – Synch Field............................................................................. 482
18-7. UART vs IrDA Data Format............................................................................................. 483
18-8. Glitch Suppression, eUSCI_A Receive Not Started................................................................. 485
18-9. Glitch Suppression, eUSCI_A Activated.............................................................................. 485
18-10. BITCLK Baud-Rate Timing With UCOS16 = 0....................................................................... 486
18-11. Receive Error............................................................................................................. 490
18-12. UCAxCTLW0 Register .................................................................................................. 495
18-13. UCAxCTLW1 Register .................................................................................................. 496
18-14. UCAxBRW Register ..................................................................................................... 497
18-15. UCAxMCTLW Register.................................................................................................. 497
18-16. UCAxSTATW Register .................................................................................................. 498
18-17. UCAxRXBUF Register .................................................................................................. 499
18-18. UCAxTXBUF Register................................................................................................... 499
18-19. UCAxABCTL Register................................................................................................... 500
18-20. UCAxIRCTL Register.................................................................................................... 501
18-21. UCAxIE Register......................................................................................................... 502
18-22. UCAxIFG Register....................................................................................................... 503
18-23. UCAxIV Register......................................................................................................... 504
19-1. eUSCI Block Diagram – SPI Mode .................................................................................... 507
19-2. eUSCI Master and External Slave (UCSTEM = 0) .................................................................. 509
19-3. eUSCI Slave and External Master..................................................................................... 510
19-4. eUSCI SPI Timing With UCMSB = 1.................................................................................. 512
19-5. UCAxCTLW0 Register .................................................................................................. 515
19-6. UCAxBRW Register ..................................................................................................... 517
19-7. UCAxSTATW Register .................................................................................................. 518
16 List of Figures SLAU272C–May 2011–Revised November 2013
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19-8. UCAxRXBUF Register .................................................................................................. 519
19-9. UCAxTXBUF Register................................................................................................... 520
19-10. UCAxIE Register......................................................................................................... 521
19-11. UCAxIFG Register....................................................................................................... 522
19-12. UCAxIV Register......................................................................................................... 523
19-13. UCBxCTLW0 Register .................................................................................................. 525
19-14. UCBxBRW Register ..................................................................................................... 527
19-15. UCBxSTATW Register .................................................................................................. 527
19-16. UCBxRXBUF Register .................................................................................................. 528
19-17. UCBxTXBUF Register................................................................................................... 528
19-18. UCBxIE Register......................................................................................................... 529
19-19. UCBxIFG Register....................................................................................................... 529
19-20. UCBxIV Register......................................................................................................... 530
20-1. eUSCI_B Block Diagram – I2C Mode.................................................................................. 533
20-2. I2C Bus Connection Diagram........................................................................................... 534
20-3. I2C Module Data Transfer............................................................................................... 535
20-4. Bit Transfer on I2C Bus.................................................................................................. 535
20-5. I2C Module 7-Bit Addressing Format .................................................................................. 535
20-6. I2C Module 10-Bit Addressing Format................................................................................. 536
20-7. I2C Module Addressing Format With Repeated START Condition................................................ 536
20-8. I2C Time-Line Legend ................................................................................................... 538
20-9. I2C Slave Transmitter Mode ............................................................................................ 539
20-10. I2C Slave Receiver Mode ............................................................................................... 540
20-11. I2C Slave 10-Bit Addressing Mode..................................................................................... 541
20-12. I2C Master Transmitter Mode........................................................................................... 543
20-13. I2C Master Receiver Mode.............................................................................................. 545
20-14. I2C Master 10-Bit Addressing Mode ................................................................................... 546
20-15. Arbitration Procedure Between Two Master Transmitters.......................................................... 546
20-16. Synchronization of Two I2C Clock Generators During Arbitration ................................................. 547
20-17. UCBxCTLW0 Register .................................................................................................. 554
20-18. UCBxCTLW1 Register .................................................................................................. 556
20-19. UCBxBRW Register ..................................................................................................... 558
20-20. UCBxSTATW Register .................................................................................................. 558
20-21. UCBxTBCNT Register................................................................................................... 559
20-22. UCBxRXBUF Register .................................................................................................. 560
20-23. UCBxTXBUF Register................................................................................................... 560
20-24. UCBxI2COA0 Register.................................................................................................. 561
20-25. UCBxI2COA1 Register.................................................................................................. 562
20-26. UCBxI2COA2 Register.................................................................................................. 562
20-27. UCBxI2COA3 Register.................................................................................................. 563
20-28. UCBxADDRX Register .................................................................................................. 563
20-29. UCBxADDMASK Register .............................................................................................. 564
20-30. UCBxI2CSA Register.................................................................................................... 564
20-31. UCBxIE Register......................................................................................................... 565
20-32. UCBxIFG Register....................................................................................................... 567
20-33. UCBxIV Register......................................................................................................... 569
21-1. Large Implementation of EEM.......................................................................................... 572
17
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List of Tables
1-1. Interrupt Sources, Flags, and Vectors.................................................................................. 32
1-2. Operation Modes .......................................................................................................... 37
1-3. Requested vs Actual LPM................................................................................................ 37
1-4. Connection of Unused Pins .............................................................................................. 40
1-5. Tag Values ................................................................................................................. 45
1-6. REF Calibration Tags..................................................................................................... 46
1-7. ADC Calibration Tags..................................................................................................... 47
1-8. BSL Configuration Tags .................................................................................................. 48
1-9. BSL_COM_IF Values ..................................................................................................... 48
1-10. BSL_CIF_CONFIG Values............................................................................................... 49
1-11. SFR Registers ............................................................................................................. 49
1-12. SFRIE1 Register Description ............................................................................................ 50
1-13. SFRIFG1 Register Description .......................................................................................... 51
1-14. SFRRPCR Register Description......................................................................................... 53
1-15. SYS Registers ............................................................................................................. 54
1-16. SYSCTL Register Description ........................................................................................... 55
1-17. SYSJMBC Register Description......................................................................................... 56
1-18. SYSJMBI0 Register Description......................................................................................... 57
1-19. SYSJMBI1 Register Description......................................................................................... 57
1-20. SYSJMBO0 Register Description ....................................................................................... 58
1-21. SYSJMBO1 Register Description ....................................................................................... 58
1-22. SYSUNIV Register Description.......................................................................................... 59
1-23. SYSSNIV Register Description .......................................................................................... 59
1-24. SYSRSTIV Register Description ........................................................................................ 60
2-1. PMM Registers ............................................................................................................ 66
2-2. PMMCTL0 Register Description......................................................................................... 67
2-3. PMMIFG Register Description........................................................................................... 68
2-4. PM5CTL0 Register Description.......................................................................................... 69
3-1. System Clocks vs Power Modes and Clock Requests ............................................................... 76
3-2. CS Registers............................................................................................................... 79
3-3. CSCTL0 Register Description ........................................................................................... 80
3-4. CSCTL1 Register Description ........................................................................................... 81
3-5. CSCTL2 Register Description ........................................................................................... 82
3-6. CSCTL3 Register Description ........................................................................................... 83
3-7. CSCTL4 Register Description ........................................................................................... 84
3-8. CSCTL5 Register Description ........................................................................................... 85
3-9. CSCTL6 Register Description ........................................................................................... 86
4-1. SR Bit Description......................................................................................................... 93
4-2. Values of Constant Generators CG1, CG2 ............................................................................ 94
4-3. Source and Destination Addressing .................................................................................... 97
4-4. MSP430 Double-Operand Instructions................................................................................ 115
4-5. MSP430 Single-Operand Instructions................................................................................. 115
4-6. Conditional Jump Instructions.......................................................................................... 116
4-7. Emulated Instructions ................................................................................................... 116
4-8. Interrupt, Return, and Reset Cycles and Length..................................................................... 117
4-9. MSP430 Format II Instruction Cycles and Length................................................................... 117
4-10. MSP430 Format I Instructions Cycles and Length .................................................................. 118
18 List of Tables SLAU272C–May 2011–Revised November 2013
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4-11. Description of the Extension Word Bits for Register Mode......................................................... 119
4-12. Description of Extension Word Bits for Non-Register Modes ...................................................... 120
4-13. Extended Double-Operand Instructions............................................................................... 121
4-14. Extended Single-Operand Instructions................................................................................ 123
4-15. Extended Emulated Instructions ....................................................................................... 125
4-16. Address Instructions, Operate on 20-Bit Register Data............................................................. 126
4-17. MSP430X Format II Instruction Cycles and Length ................................................................. 127
4-18. MSP430X Format I Instruction Cycles and Length.................................................................. 128
4-19. Address Instruction Cycles and Length............................................................................... 129
4-20. Instruction Map of MSP430X........................................................................................... 130
5-1. Manual Wait State Settings............................................................................................. 246
5-2. FRCTL Registers......................................................................................................... 247
5-3. FRCTL0 Register Description .......................................................................................... 248
5-4. GCCTL0 Register Description.......................................................................................... 249
5-5. GCCTL1 Register Description.......................................................................................... 250
6-1. Page Addresses for 16KB, 8KB, and 4KB Main Memory .......................................................... 254
6-2. Segment Access Rights................................................................................................. 255
6-3. MPU Registers ........................................................................................................... 257
6-4. MPUCTL0 Register Description........................................................................................ 258
6-5. MPUCTL1 Register Description........................................................................................ 259
6-6. MPUSEG Register Description......................................................................................... 260
6-7. MPUSAM Register Description ........................................................................................ 261
6-8. MPUIV Register Description............................................................................................ 263
7-1. DMA Transfer Modes.................................................................................................... 268
7-2. DMA Trigger Operation ................................................................................................. 275
7-3. Maximum Single-Transfer DMA Cycle Time ......................................................................... 276
7-4. DMA Registers ........................................................................................................... 279
7-5. DMACTL0 Register Description........................................................................................ 281
7-6. DMACTL1 Register Description........................................................................................ 282
7-7. DMACTL2 Register Description........................................................................................ 283
7-8. DMACTL3 Register Description........................................................................................ 284
7-9. DMACTL4 Register Description........................................................................................ 285
7-10. DMAxCTL Register Description........................................................................................ 286
7-11. DMAxSA Register Description ......................................................................................... 288
7-12. DMAxDA Register Description ......................................................................................... 289
7-13. DMAxSZ Register Description.......................................................................................... 290
7-14. DMAIV Register Description............................................................................................ 291
8-1. I/O Configuration......................................................................................................... 294
8-2. I/O Function Selection................................................................................................... 295
8-3. Digital I/O Registers ..................................................................................................... 300
8-4. P1IV Register Description .............................................................................................. 313
8-5. P2IV Register Description .............................................................................................. 313
8-6. P3IV Register Description .............................................................................................. 314
8-7. P4IV Register Description .............................................................................................. 314
8-8. PxIN Register Description .............................................................................................. 315
8-9. PxOUT Register Description ........................................................................................... 315
8-10. P1DIR Register Description ............................................................................................ 315
8-11. PxREN Register Description ........................................................................................... 316
8-12. PxSEL0 Register Description........................................................................................... 316
19
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8-13. PxSEL1 Register Description........................................................................................... 316
8-14. PxSELC Register Description .......................................................................................... 317
8-15. PxIES Register Description............................................................................................. 317
8-16. PxIE Register Description............................................................................................... 317
8-17. PxIFG Register Description............................................................................................. 318
9-1. CRC Registers ........................................................................................................... 324
9-2. CRCDI Register Description............................................................................................ 325
9-3. CRCDIRB Register Description........................................................................................ 325
9-4. CRCINIRES Register Description ..................................................................................... 326
9-5. CRCRESR Register Description....................................................................................... 326
10-1. WDT_A Registers........................................................................................................ 332
10-2. WDTCTL Register Description......................................................................................... 333
11-1. Timer Modes.............................................................................................................. 338
11-2. Output Modes ............................................................................................................ 343
11-3. Timer_A Registers....................................................................................................... 349
11-4. TAxCTL Register Description .......................................................................................... 350
11-5. TAxR Register Description.............................................................................................. 351
11-6. TAxCCTLn Register Description....................................................................................... 352
11-7. TAxCCRn Register Description ........................................................................................ 354
11-8. TAxIV Register Description............................................................................................. 354
11-9. TAxEX0 Register Description .......................................................................................... 355
12-1. Timer Modes.............................................................................................................. 360
12-2. TBxCLn Load Events.................................................................................................... 365
12-3. Compare Latch Operating Modes ..................................................................................... 366
12-4. Output Modes ............................................................................................................ 366
12-5. Timer_B Registers....................................................................................................... 372
12-6. TBxCTL Register Description .......................................................................................... 373
12-7. TBxR Register Description.............................................................................................. 375
12-8. TBxCCTLn Register Description....................................................................................... 376
12-9. TBxCCRn Register Description ........................................................................................ 378
12-10. TBxIV Register Description............................................................................................. 379
12-11. TBxEX0 Register Description .......................................................................................... 380
13-1. RTC_B Registers ........................................................................................................ 389
13-2. RTCCTL0 Register Description ........................................................................................ 391
13-3. RTCCTL1 Register Description ........................................................................................ 392
13-4. RTCCTL2 Register Description ........................................................................................ 393
13-5. RTCCTL3 Register Description ........................................................................................ 393
13-6. RTCSEC Register Description ......................................................................................... 394
13-7. RTCSEC Register Description ......................................................................................... 394
13-8. RTCMIN Register Description.......................................................................................... 395
13-9. RTCMIN Register Description.......................................................................................... 395
13-10. RTCHOUR Register Description....................................................................................... 396
13-11. RTCHOUR Register Description....................................................................................... 396
13-12. RTCDOW Register Description ........................................................................................ 397
13-13. RTCDAY Register Description ......................................................................................... 397
13-14. RTCDAY Register Description ......................................................................................... 397
13-15. RTCMON Register Description ........................................................................................ 398
13-16. RTCMON Register Description ........................................................................................ 398
13-17. RTCYEAR Register Description ....................................................................................... 399
20 List of Tables SLAU272C–May 2011–Revised November 2013
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