Texas Instruments ADS7881EVM User manual

User’s Guide
ADS7881EVM, ADS7891EVM Evaluation Module
Lijoy Philipose Data Acquisition Products
ABSTRACT
This user's guide describes the characteristics, operation, and use of the ADS78x1 (ADS7881 and ADS7891)
12-bit and 14-bit, parallel, analog-to-digital converter (ADC) evaluation module (EVM). Throughout this
document, the terms evaluation board, evaluation module, and EVM are synonymous with the ADS78x1EVM.
A complete circuit description, schematic diagram, layout, and bill of materials (BOM) are included in this
document.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Features............................................................................................................................................................................. 2
1.2 Analog Interface................................................................................................................................................................. 2
1.3 Digital Interface.................................................................................................................................................................. 4
1.4 Power Supplies.................................................................................................................................................................. 6
2 Using the EVM.........................................................................................................................................................................7
3 ADS78x1EVM Bill of Materials...............................................................................................................................................8
4 ADS78x1EVM Layout............................................................................................................................................................10
5 ADS78x1EVM Schematics................................................................................................................................................... 14
6 Revision History................................................................................................................................................................... 17
List of Figures
Figure 1-1. ADS7881 Input Buffer Circuit.................................................................................................................................... 3
Figure 2-1. Decoding Control Signals Using the Address Bus.................................................................................................... 7
Figure 4-1. Top Layer – Layer 1.................................................................................................................................................10
Figure 4-2. Ground Plane – Layer 2...........................................................................................................................................11
Figure 4-3. Power Plane – Layer 3............................................................................................................................................ 12
Figure 4-4. Bottom Layer – Layer 4........................................................................................................................................... 13
Figure 5-1. Schematic Page 1: Digital Buffer.............................................................................................................................14
Figure 5-2. Schematic Page 2: ADS7881, ADS7891................................................................................................................ 15
Figure 5-3. Schematic Page 3: Digital Communication............................................................................................................. 16
List of Tables
Table 1-1. Related Documentation from Texas Instruments........................................................................................................ 2
Table 1-2. Analog Input Connector.............................................................................................................................................. 2
Table 1-3. Solder Short Jumper Setting.......................................................................................................................................4
Table 1-4. Pin Out for Parallel Control Connector P2.................................................................................................................. 4
Table 1-5. Jumper Settings.......................................................................................................................................................... 5
Table 1-6. Data Bus Connector P3.............................................................................................................................................. 5
Table 1-7. Pin Out for Converter Control Connector J3............................................................................................................... 6
Table 1-8. Power-Supply Test Points........................................................................................................................................... 6
Table 1-9. Power Connector, J1, Pin Out.....................................................................................................................................6
Table 3-1. Bill of Materials............................................................................................................................................................8
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
The ADS78x1EVM showcases the 12-bit, 4-MSPS (ADS7881) and 14-bit, 3-MSPS (ADS7891) ADCs. The
ADS7881 and ADS7891 devices include a capacitor-based successive-approximation register (SAR) ADC with
inherent sample and hold. These devices offer either a 12-bit or 14-bit parallel interface. Both devices offer byte
mode operation that enables easy interface with 8-bit processors. They also have a pseudo-differential input
stage and a 2.5-V internal reference.
This evaluation module serves as a reference design and a low-cost method to test these converters in the end
application. The following sections describe the pin outs of the various analog, power, and digital connectors and
power requirements.
Table 1-1 lists documents related to the ADS78x1EVM.
Table 1-1. Related Documentation from Texas Instruments
Data Sheets Literature Number
ADS7881 SLAS400
ADS7891 SLAS410
ADS8411 SLAS369
THS4031 SLOS224
OPA132 SBOS054
REF1004-2.5 SBVS032
SN74AHC138 SCLS258
SN74AHC245 SCLS230
SN74AHC1G04 SCLS318
1.1 Features
The ADS78x1EVM includes the following features:
• Full-featured evaluation board for the high-speed, SAR-type ADS7881(12-bit, 4-MSPS) or ADS7891(14-bit,
3-MSPS) single-channel, parallel interface ADCs
• Onboard signal conditioning
• Onboard reference
• Input and output digital buffers
• Onboard decoding for stacking multiple EVMs
1.2 Analog Interface
The ADS7881 and ADS7891 ADCs have both a positive and negative analog input pin. The negative input pin,
which has a range of –200 mV up to 200 mV is shorted on the board. A signal for the positive input pin can be
applied at connector P1, pin 2 (as shown in Table 1-2) or at the center pin of the SMA connector J2.
Table 1-2. Analog Input Connector
Connector.Pin#(1) Signal Description
P1.2 +IN Noninverting input channel
P1.4 Reserved —
P1.6 Reserved —
P1.8 Reserved —
P1.10 Reserved —
P1.12 Reserved —
P1.14 Reserved —
P1.16 Reserved —
P1.18 Reserved —
P1.20 REF+ External reference input
(1) All odd-numbered pins of P1 are tied to AGND.
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1.2.1 Signal Conditioning
The factory recommends the analog input to any SAR-type converter be buffered and low-pass filtered. The
input buffer on the ADS78x1EVM uses the THS4031 (as shown in Figure 1-1) configured as an inverting
gain of one. However, the amplifier is not stable at a gain of one, and is thus configured for inverting gain of
one. The THS4031 was selected for its low noise, high slew rate, and fast settling time. The low-pass filter
resistor and capacitor values were selected such that the ADS78x1EVM meets the 1-MHz AC performance
specifications listed in the data sheet. The series resistor works in conjunction with the capacitor to filter the input
signal, but also isolates the amplifier from the capacitive load. The capacitor to ground at the input of the ADC
works in conjunction with the series resistor to filter the input signal, and functions as a charge reservoir. This
external filter capacitor works with the amplifier to charge the internal sampling capacitor during sampling mode.
Resistors R1 and R12 were selected to reduce offset.
The EVM has a provision to offset the input voltage by adjusting R25, a 10-kΩ potentiometer.
130 pF
C0G
+2.5 V
THS4031
1000 pF
C0G
(+)IN
(−)IN
C35
C16
R13
U2
C33
R25
C7
C31
C37
C15
R10
R6
R1
R12
604 W
−VCC
0.1 mF
1 mF
604 W
21 W
21 W
12 W
1 mF
0.1 mF
+VCC
1 mF
VIN
10 kW
Figure 1-1. ADS7881 Input Buffer Circuit
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1.2.2 Reference
The ADS78x1EVM provides an onboard 2.5-V reference circuit. The EVM also supplies a reference voltage via
connecter P1 pin 20. This reference voltage can be filtered through amplifier U1. The converter itself has on-chip
reference buffer, and therefore does not need to be buffered externally. The reference buffer circuit on the EVM
is used to generate the offset voltage for the input amplifier, U2.
The EVM allows selection from three reference sources. Set SJP1, SJP2, and SJP4 to select either an onboard
reference voltage (REF1004-2.5), ADC internal reference, or a user-supplied reference voltage via P1 pin 20.
Table 1-3 lists jumper settings and Section 5 provides full schematics.
Table 1-3. Solder Short Jumper Setting
Reference
Designator Description Pads
1–2 2–3
SJP1 Apply onboard reference directly to SJP2 pin 3 Installed(1) —
Apply buffered reference voltage to SJP2 pin 3 — Installed
SJP2 Apply internal reference to REFIN pin Installed(1) —
Apply external reference to REFIN pin — Installed
SJP4 Apply onboard reference to U1, reference buffer Installed —
Apply user-supplied reference to U1, reference buffer — Installed
SJP5 Apply DC offset to input signal Installed(1) —
SJP6 Short to pin 4 of amplifier U1 to ground Installed —
Short to pin 4 of amplifier U1 to –VCC — Installed(1)
SJP7 Short to pin 4 of amplifier U2 to ground Installed —
Short to pin 4 of amplifier U2 to –VCC — Installed(1)
(1) Factory-set condition.
1.3 Digital Interface
The ADS78x1EVM is designed for easy interfacing to multiple platforms. Samtec part numbers SSW-110-22-F-
D-VS-K, TSM-110-01-T-DV-P, SSW-116-22-S-D-VS, and TSM-116-01-T-D-V-P provide a convenient dual row
header and socket combination at P1, P2, P3, and J3. Consult Samtec at www.samtec.com or 1-800-SAMTEC-9
for a variety of mating connector options.
Connectors P1, P2, and P3 allows the user to plug the EVM into the 5-6k interface card to interface directly with
the TMS320C5000 and TMS320C6000 series of DSP. Table 1-4 lists the connector pin out.
Table 1-4. Pin Out for Parallel Control Connector P2
Connector.Pin(1) Signal Description
P2.1 DC_CS Daughter card board select pin
P2.3 — —
P2.5 — —
P2.7 A0 Address line from processor
P2.9 A1 Address line from processor
P2.11 A2 Address line from processor
P2.13 — —
P2.15 — —
P2.17 — —
P2.19 BUSY Busy signal from converter. W4 must be shorted.
(1) All even-numbered pins of P2 are tied to DGND.
Read (RD), conversion start (CONVST) and reset (RESET) signals to the converter can be assigned to two
different addresses in memory via jumper settings. The jumper settings allow up to two ADS78x1EVMs to be
stacked into processor memory. See Table 1-5 for jumper settings. The evaluation module does not allow the
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chip-select (CS) line of the converter to be assigned to different memory locations. Instead, ground or wire the
CS line to an appropriate signal of the user processor.
Table 1-5. Jumper Settings
Reference
Designator Description Pins
1–2 2–3
W1 Short U8 pin 14 to power-down or reset signal Installed(1) —
Short U8 pin 13 to power-down or reset signal — Installed
W2 Short U8 pin 12 to CONVST signal Installed(1) —
Short U8 pin 11 to CONVST signal — Installed
W3 Short U8 pin 10 to RD signal Installed(1) —
Short U8 pin 8 to RD signal — Installed
W4 Short inverted BUSY to INTC Installed(1) —
Short BUSY to INTC — Installed
W5 Short +5VD to +BVDD Installed(1) —
Short +3.3VD to +BVDD — Installed
(1) Factory-set condition.
The data bus is available at connector P3. Table 1-6 lists the pin out information. This EVM supports two devices
but the connector signals names are based on the ADS7981, which is the higher-resolution device. Depending
on which device is being evaluated, care must be taken when connecting the EVM to a host processor.
Table 1-6. Data Bus Connector P3
Connector.Pin(1) Signal Name Description
ADS7881 ADS7891
P3.1 B_DB0 Not connected Buffered data bit 0 (LSB)
P3.3 B_DB1 Not connected Buffered data bit 1
P3.5 B_DB2 Buffered data bit 0 (LSB) Buffered data bit 2
P3.7 B_DB3 Buffered data Bit 1 Buffered data bit 3
P3.9 B_DB4 Buffered data bit 2 Buffered data bit 4
P3.11 B_DB5 Buffered data bit 3 Buffered data bit 5
P3.13 B_DB6 Buffered data bit 4 Buffered data bit 6
P3.15 B_DB7 Buffered data bit 5 Buffered data bit 7
P3.17 B_DB8 Buffered data bit 6 Buffered data bit 8
P3.19 B_DB9 Buffered data bit 7 Buffered data bit 9
P3.21 B_DB10 Buffered data bit 8 Buffered data bit 10
P3.23 B_DB11 Buffered data bit 9 Buffered data bit 11
P3.25 B_DB12 Buffered data bit 10 Buffered data bit 12
P3.27 B_DB13 Buffered data bit 11 (MSB) Buffered data bit 13 (MSB)
P3.29 Not connected Not connected Not connected
P3.31 Not connected Not connected Not connected
(1) All even-numbered pins of P3 are tied to DGND.
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As described in Table 1-7, this evaluation module provides direct access all the analog-to-digital converter
control signals via connector J3.
Table 1-7. Pin Out for Converter Control Connector J3
Connector.Pin(1) Signal Description
J3.1 CS Chip-select pin. Active low.
J3.3 RD Read pin. Active low.
J3.5 CONVST Convert start pin. Active low.
J3.7 BYTE BYTE mode pin. Used for 8-bit buses.
J3.9 PWD/RST Active low input, acts as device power down or device reset signal.
J3.11 A_PDWN Nap mode enable, active low.
J3.13 BUSY Converter status output. High when a conversion is in progress.
(1) All even-numbered pins of J3 are tied to DGND.
1.4 Power Supplies
The EVM accepts four power supplies.
• A dual ±Vs DC supply for the dual-supply op amps. A ±12-V DC supply is recommended.
• A single +5.0-V DC supply for the analog section of the board (ADC + reference).
• A single +5.0-V or +3.3-V DC supply for the digital section of the board (ADC + address decoder + buffers).
There are two ways to provide these voltages.
1. Wire in voltages, as listed in Table 1-8, at test points on the EVM.
Table 1-8. Power-Supply Test Points
Test Point Signal Description
TP11 +BVDD Apply a +3.3-V DC or +5.0-V DC voltage. See the respective ADC data sheet for the full range.
TP10 +AVCC Apply a +5.0-V DC voltage.
TP12 +VA Apply a +12.0-V DC voltage. Positive supply for the amplifier.
TP14 –VA Apply a –12.0-V DC voltage. Negative supply for the amplifier.
1. Use the power connector J1 and derive the voltages elsewhere. Table 1-9 lists the pin out connections for
J1. Set jumper W5 to short between pins 1-2 or pins 2-3 to short +3.3VD or +5VD, respectively, to be the
buffer digital supply (+BVDD).
Table 1-9. Power Connector, J1, Pin Out
Signal Power Connector - J1 Signal
+VA (+12VA) 1 2 –VA (–12VA)
+AVCC (+5VA) 3 4 N/C
N/C 5 6 AGND
N/C 7 8 N/C
+3.3VD 9 10 +5VD
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2 Using the EVM
The ADS78x1EVM serves as a reference design, prototype board, and test platform for the software engineer to
develop code.
As a reference design, the ADS78x1EVM contains the essential circuitry to showcase the ADC. This essential
circuitry includes the input amplifier, reference circuit, and buffers. The EVM analog input circuit is optimized for
a 1-MHz sine wave, therefore users may need to adjust the resistor and capacitor values of the ADC input RC
circuit. In AC-type applications where signal distortion is a concern, use polypropylene capacitors in the signal
path. In applications where the input is multiplexed, either adjust or remove the ADC input resistor and capacitor,
as needed.
As a prototype board, the buffer circuit consists of a footprint in a standard 8-pin SOIC and resistor pads
for inverting and noninverting configurations. The ADS78x1EVM can be used to evaluate both dual- and single-
supply amplifiers. The EVM comes installed with a dual-supply amplifier that allows the user to take advantage
of the full input voltage range of the converter. For applications that require signal supply operation and smaller
input voltage ranges, the THS4031 can be replaced with a single-supply amplifier, such as the OPA300. Short
pad jumper SJP7 between pads 1 and 2, because SJP7 shorts the minus supply pin of the amplifier to ground.
The positive supply voltage can be applied via test point TP12 or connector J1 pin 1.
As a software test platform, connectors P1, P2, and P3 plug into the parallel interface connectors of the 5-6K
interface card. The 5-6K interface card sits on the C5000 and C6000 digital signal processor starter kit (DSK).
The ADS78x1EVM is then mapped into the processor memory space. This card also provides an area for signal
conditioning. This area can be used to install application circuits for digitization by the ADS7881 or ADS7891
ADC. See the 5–6K Interface Board user's guide for more information.
For the software engineer, the ADS78x1EVM provides a simple platform for interfacing to the converter. The
EVM provides standard 0.1" headers and sockets to wire into prototype boards. The user must only provide
three address lines (A2, A1, and A0) and one address valid line (DC_CS) to connector P2, as shown in Figure
2-1. To choose which address combinations generate RD, CONVST, and RESET set jumpers as shown in Table
1-5. Recall that the chip select (CS) signal is not memory mapped or tied to P2, and therefore must be controlled
via a general-purpose pin or shorted to ground at the J3 pin 1. If address decoding is not required, the EVM
provides direct access to converter data bus via P3 and control via J3.
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
1
1
W1
W2
W3
RD
CONVST
RESET
SN74AHC138
A
B
C
G
A0
A1
A2
DC_CS
Figure 2-1. Decoding Control Signals Using the Address Bus
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3 ADS78x1EVM Bill of Materials
Table 3-1 contains a complete bill of materials (BOM) for the ADS78x1EVM. The schematic diagrams are also provided for reference in Section 5.
Table 3-1. Bill of Materials
Item No. Qty. Value Reference
Designators Footprint Manufacturer Manufacturer's Part Number Description
1 2 21 R1 R12 805 Panasonic-ECG or Alternate ERJ-6ENF21R RES, 21.0 Ω, 1/10W, 1% 0805 SMD
2 3 NI R2 R5 R11 805 Not installed Not installed
3 1 NI R3 603 Not installed Not installed 1/10W, 0805 Chip Resistor
4 3 100 R4 R14 R15 805 Panasonic-ECG or Alternate ERJ-6ENF1000V RES, 100 Ω, 1/10W, 1%, 0805 SMD
5 2 604 R6 R10 805 Panasonic-ECG or Alternate ERJ-6ENF6040V RES, 604 Ω, 1/10W, 1%, 0805 SMD
6 6 10k R7 R16 R17 R18 R19 R20 603 Panasonic-ECG or Alternate ERJ-3EKF1002V RES, 10.0 kΩ, 1/16W, 1%, 0603 SMD
7 1 49.9 R8 1206 Panasonic-ECG or Alternate ERJ-8ENF49R9V RES, 49.9 Ω, 1/8W, 1%, 1206 SMD
8 1 49.9k R9 805 Panasonic-ECG or Alternate ERJ-6ENF4992V RES, 49.9 kΩ, 1/10W, 1%, 0805 SMD
9
1 12 R13 805 Panasonic-ECG or Alternate ERJ-6GEYJ120V RES, 12 Ω, 1/8W, 5%, 0805 SMD
1 10 R13(1) 805 Yageo America or Alternate 9C08052A10R0FKHFT RES, 10 Ω, 1/8W, 1%, 0805 SMD
10 1 75 R21 805 Panasonic-ECG or Alternate ERJ-6ENF75R0V RES, 75.0 Ω, 1/10W, 1%, 0805 SMD
11 1 0 R24 603 Panasonic-ECG or Alternate ERJ-3GEY0R00V RES, 0 Ω, 1/16W, 5%, 0603 SMD
12 1 10k R22 805 Panasonic-ECG or Alternate ERJ-6ENF1002V RES, 10.0 kΩ, 1/10W, 1%, 0805 SMD
13 1 10k R25 BOURNS_ 32×4W Bourns 3214W-1-103E TRIMPOT, 10 kΩ, 4MM TOP ADJ SMD
14 4 10 µF C1 C6 C12 C19 1206 TDK Corporation or Alternate C3216X5R1C106KT CAP, CER, 10 µF, 16V, X5R, 20%, 1206
15 2 1 µF C2 C28 603 TDK Corporation or Alternate C1608X5R1C105K CAP, CER, 1.0 µF, 16V, X5R, 10%, 0603
16 5 1000 pF C3 C5 C11 C16 C23 603 TDK Corporation or Alternate C1608C0G1H102J CAP, CER, 1000 pF, 50V, C0G, 5%, 0603
17 13 0.01 µF C4 C10 C13 C20 C21C26 C41
C44 C46 C48 C50 C53 C56 603 TDK Corporation or Alternate C1608X7R1H103KT CAP, CER, 10000 pF, 50V, X7R, 10%, 0603
18 4 0.1 µF C7 C15 C32 C36 805 TDK Corporation or Alternate C1608X7R1E104K CAP, CER, 0.10 µF, 25V X7R, 10%, 0603
19 8 2.2 µF C8 C40 C42 C47 C51 C52 C54
C55 603 TDK Corporation or Alternate C1608X5R1A225MT CAP, CER, 2.2 µF, 6.3V, X5R, 20%, 0603
20 9 0.1 µF C9 C18 C22 C25 C38 C43 C57
C58 C62 603 TDK Corporation or Alternate C1608X7R1E104K CAP, CER, 0.10 µF, 25V, X7R 10%, 0603
21 4 10 µF C14 C24 C27 C29 6032 Panasonic-ECG or Alternate ECS-T1EC106R CAP, 10 µF, 25V, TANTALUM, TE, SMD
22
1 22 µF C17 1206 Panasonic-ECG or Alternate C3216XR0J226M CAP, CER, 22 µF, 6.3V X5R, 20%, 1206
1 1500 pF C16(1) 603 TDK Corporation or Alternate C1608C0G1H152J CAP, CER, 1500 pF, 50V, C0G, 5%, 0603
23 4 NI C30 C39 C61 C63 805 NOT INSTALLED NOT INSTALLED Multilayer Ceramic - 0805 Size
24 5 1 µF C31 C33 C37 C59 C60 805 TDK Corporation or Alternate C2012X7R1E105K CAP, CER, 1.0 µF, 25V, X7R, 0805, T/R
25 1 130 pF C35 805 TDK Corporation or Alternate C2012C0G1H131 CAP, CER, 130 pF, 50V 5%, C0G, 0805
26 1 10 µF C49 3528 Kemet or Alternate T491B106K016AS CAP, TANTALUM, 10 µF, 16V 10%, SMD
27 2 1K RP1 RP3 CTS_742 CTS Corporation 742C163102JTR RES ARRAY, 1 kΩ, 16TERM 8RES SMD
28 1 100 RP2 CTS_742 CTS Corporation 742C163101JTR RES ARRAY 100 Ω 16TRM, 8RES SMD
29 4 L1 L2 L3 L4 805 TDK Corporation MMZ2012R601A Ferrite chip, 600 Ω, 500 mA
30 1 U1 8-SOP(D) Texas Instruments OPA132UA DiFet amplifier
31 1 U2 8-SOP(D) Texas Instruments THS4031IDR 100 MHz, low-noise, high-speed amplifier
32 1 NI U3 3-SOT-23 Not installed Not installed REF3040, 50 ppm/–C, 50-A in SOT23-3 CMOS
voltage reference
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Table 3-1. Bill of Materials (continued)
Item No. Qty. Value Reference
Designators Footprint Manufacturer Manufacturer's Part Number Description
33 1
ADS7881 U4
SOCKET_48 QFPP Texas Instruments
ADS7881IPFBT ADS7881, 12-bit, 4 MSPS
ADS7891 U4(1) ADS7891IPFBT ADS7891, 14-bit, 3 MSPS
34 3 SN74AHC245 U5 U6 U7 20-TSSOP(PW) Texas Instruments SN74AHC245PWR Octal bus transceiver, 3-state
35 1 SN74AHC138 U8 16-TSSOP (PW) Texas Instruments SN74AHC138PWR 3-line to 8-line decoder/ demultiplexer
36 1 REF1004-2.5 U9 8-SOP(D) Texas Instruments REF1004-2.5 Micropower voltage reference
37 1 SN74AHC1G04 U12 5-SOT(DBV) Texas Instruments SN74AHC1G04DBVR Single inverter gate
38 2 10×2×0.1 P1 P2 10×2×0.1_SMT_PLUG_&
_SOCKET Samtec SSW-110-22-S-D-VS 0.025" SMT socket - bottom side of PWB
39 2 Samtec TSM-107-01-T-D-V-P 0.025" SMT plug - top side of PWB
40 1 Data Bus P3 10×2×0.1_SMT_PLUG_&
_SOCKET Samtec SSW-116-22-S-D-VS 0.025" SMT socket - bottom side of PWB
41 1 Samtec TSM-116-01-T-D-V-P 0.025" SMT plug - top side of PWB
42 1 Power Supply J1 5×2×0.1_SMT_SOCKET Samtec SSW-105-22-S-D-VS 0.025" SMT socket - bottom side of PWB
43 1 Samtec TSM-105-01-T-D-V-P 0.025" SMT plug - top side of PWB
44 1 SMA_PCB_MT J2 SMA_JACK Johnson Components Inc. 142-0701-301 Right angle SMA connector
45 1 7×2×0.1 J3 7×2×0.1_SMT_PLUG_&_
SOCKET Samtec SSW-107-22-S-D-VS 0.025" SMT socket - bottom side of PWB
46 1 Samtec TSM-107-01-T-D-V-P 0.025" SMT plug - top side of PWB
47 1 SW-PB S1 EVQ-PJ Panasonic EVQ-PJU04K switch
48 5 W1 W2 W3 W4 W5 3POS_JUMPER Samtec TSW-103-07-L-S 3 Position jumper _ 0.1" spacing
49 1 SJP2 SJP5 SJP2 Not installed Not installed Pad 2 position jumper
50 5 SJP3 SJP1 SJP2 SJP4 SJP6 SJP7 SJP3 Not installed Not installed Pad 3 position jumper
51 1 TO_0.025 TP1 test_point2 Keystone Electronics 5002K-ND Test point, PC, mini 0.040" D, white
52 10 TO_0.025 TP3 TP4 TP6 TP8 TP9 TP10 TP11
TP12 TP14 TP15 test_point2 Keystone Electronics 5000K-ND Test point, PC, mini 0.040" D, red
53 4 TO_0.025 TP5 TP7 TP2 TP13 test_point2 Keystone Electronics 5001K-ND Test point, PC, mini 0.040" D, black
(1) Used for the ADS7891EVM only.
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4 ADS78x1EVM Layout
Figure 4-1 to Figure 4-4 illustrate the silkscreens for the ADS78x1EVM.
Figure 4-1. Top Layer – Layer 1
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Figure 4-2. Ground Plane – Layer 2
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Figure 4-3. Power Plane – Layer 3
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Figure 4-4. Bottom Layer – Layer 4
www.ti.com ADS78x1EVM Layout
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5 ADS78x1EVM Schematics
Figure 5-1 to Figure 5-3 illustrate the schematic drawings for the ADS78x1EVM.
+IN
EXT_REF
B_CS B_RD B_CONVST B_BYTE B_PWN/RST BUSY DB[13...0] B_APWD
Analog Circuits & A/D
Parallel Control
12
34
56
78
910
1112
1314
1516
1718
1920
P2
Analog Input
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
P1
+VA
-VA
B_DB[13...0]
DB[13...0]
CS RD CONVST BYTE PWN/RST B_BUSY
BUSY
B_CS
B_RD
B_CONVST
B_BYTE
B_PWN/RST
+AVCC
+VA
-VA
+BVDD
A0 A1 A2 DC_CS A_PWD INTc
B_APWD
Power & Digital Buffer
J2
B_DB[13...0]
DB[13..0]
B_DB0
B_DB1
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B_DB10
B_DB11
B_DB12
B_DB13
+AVCC
+BVDD
1
122
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
P3
Data Bus
CS
RD
CONVST
BYTE
PWN/RST
B_BUSY
A0
A1
A2
1 2
3 4
5 6
7 8
9 10
J1
Power Supply
+VA -VA
+5VD
AGND
+AVCC
TP10
TP11
TP12
TP14
ADC Control
INTc
DC_CS
12
34
56
78
9
11
13
10
12
14
J3
A_PWD
DGND
W5
+3.3VD
Figure 5-1. Schematic Page 1: Digital Buffer
ADS78x1EVM Schematics www.ti.com
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C21
0.01uF
C43
0.1uF
C42
2.2uF
C48
0.01uF
C41
0.01uF
C47
2.2uF
C52
2.2uF
C44
0.01uF
C55
2.2uF
C56
0.01uF
+5VCC
+5VCC
+5VCC
+5VCC
C54
2.2uF
C50
0.01uF
+5VCC
C51
2.2uF
C53
0.01uF
+VBD
B_CS
B_RD
B_CONVST
B_BYTE
BUSY
DB0
DB1
DB2
DB3
DB4
DB5
DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13
C46
0.01uF
C40
2.2uF
+5VCC
BUSY
DB[13...0]
B_CS
B_RD
B_BYTE
B_CONVST
-VCC
+VCC
C7
0.1uF
C31
1uF
C37
1uF
C15
0.1uF
R10
604
R13
10
C39
NI
+IN
C35
130pF
C33
1uF
R5
NI
EXT_REF
R4
100
DB[13...0]
R11
NI
TP4
31
2
SJP2
R6
604
+
C49
10uF
C8
2.2uF
C13
0.01uF
+VBD
C16
1500pF
+5VCC
C17
22uF
R21
75
R14
100
C61
NI
+VCC
C59
1uF
C36
0.1uF
-VCC
C32
0.1uF
C60
1uF
IN
1
OUT
2GND 3
U3
NI
+5VCC
R3
NI
3 1
2
SJP1
3 1
2
SJP4
R24
0
C63
NI
1
2
3
R25
10k
12
SJP5
3
2
6
74
51
U1
OPA132
R8
49.9
31
2
SJP7
31
2
SJP6
*
3
2
6
74
5 1
8
U2
THS4031
C30
NI
*
TP9
R1
21
R2
NI
REFIN
1
REFOUT
2
NC
3
+VA
4
AGND
5
+IN
6
-IN
7
AGND
8
+VA
9
+VA
10
AGND
11
AGND
12
AGND
14
AGND
15
DB13
16
DB12
17
DB11
18
DB10
19
DB9
20
DB8
21
DB7
22
DB6
23
+VBD
24
BDGND 25
DB5 26
DB4 27
DB3 28
DB2 29
DB1 30
DB0 31
N/C 32
N/C 33
+VBD 34
BDGND 35
BUSY 36
APWD 37
pwr_dwn/RESET 38
BYTE 39
CONVST 40
RD 41 CS 42
+VA 43
AGND 44 AGND 45
+VA 46
REFM 47 REFM 48
+VA
13
U4
ADS7881/ADS7891
B_PWN/RST
B_PWN/RST
B_A_PWD
B_A_PWD
N/C
1
N/C
2
N/C
3
Anode
4N/C 5
Cathode 6
N/C 7
Cathode 8
U9
REF1004-2.5
R9
49.9k
R12
21
Installed on ADS7881EVM
R13 : 12 Ohm
C16 : 1000pF C0G
U4 : ADS7881
Installed on ADS7891EVM
R13 =10 Ohm
C16 = 1500 pF C0G
U4 : ADS7891
Figure 5-2. Schematic Page 2: ADS7881, ADS7891
www.ti.com ADS78x1EVM Schematics
SLAU150A – DECEMBER 2004 – REVISED OCTOBER 2021
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L4
MMZ2012R601A
L2
MMZ2012R601A
L1
MMZ2012R601A
+
C24
10uF
+
C29
10uF
+
C27
10uF
C28
1uF
C2
1uF
C4
0.01uF
C26
0.01uF
L3
MMZ2012R601A
+
C14
10uF
TP6 +5VCC
C10
0.01uF
C9
0.1uF
TP5
TP8 +VBD
C20
0.01uF
C22
0.1uF
TP7
TP3
TP1
TP2
+VCC
-VCC
C12
10uF
C19
10uF
C6
10uF
C1
10uF
C5
1000pF
C3
1000pF
C23
1000pF
C11
1000pF
B_DB[13...0]
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
RP1
1K
/OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
VCC
GND
U6
SN74AHC245PWR
C57
0.1uF
B_RD
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
RP3
1K
+VBD
/OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
VCC
GND
U7
SN74AHC245PWR
C58
0.1uF B_RD
DB[17...0]
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
B_DB13
B_DB12
B_DB11
B_DB0
B_DB10
B_DB1
B_DB9
B_DB2
B_DB8
B_DB3
B_DB7
B_DB4
B_DB6
B_DB5
CS
RD
CONVST
BYTE
PWN/RST
B_BUSY
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
RP2
100
/OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
VCC
GND
U5
SN74AHC245PWR
+VBD
C25
0.1uF
CS
RD
CONVST
BYTE
PWN/RST
R20
10k
R19
10k
R18
10k
+VBD
R17
10k
R16
10k
BUSY
B_CS
B_RD
B_CONVST
B_BYTE
B_PWN/RST
+AVCC +VA
-VA
DB[17...0]
B_DB[13...0]
+BVDD
B_CS
B_BYTE
B_CONVST
B_RD
B_PWN/RST
A1
B2
C3
G1 6
G2A 4
G2B 5
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9
Y7
7
VCC 16
GND
8
U8
SN74AHC138PWR
A0
A1
A2
A0
A2
A1
+VBD
C62
0.1uF
+VBD
13
2
W1
13
2
W2
TP13
W3
+VBD
DC_CS
RESET#
S1
DC_CS
2 4
53
U12
SN74AHC1G04DBV
+VBD
C38
0.1uF
INTc
W4
A_PWD
R7
10k
A_PWD
B_A_PWD
B_A_PWD
R15 100
C18 0.1uF
R22
10k
+VBD
TP15
Figure 5-3. Schematic Page 3: Digital Communication
ADS78x1EVM Schematics www.ti.com
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6 Revision History
Changes from Revision * (December 2004) to Revision A (October 2021) Page
• Changed document title from ADS7881/ADS7891EVM to ADS7881EVM, ADS7891EVM Evaluation Module 1
• Changed ADS7881/ADS7891EVM to ADS78x1EVM throughout document......................................................1
• Added Related Documentation from Texas Instruments table to Introduction section....................................... 2
• Changed paragraph preceding Data Bus Connector P3 ................................................................................... 4
• Changed Data Bus Connector P3 table..............................................................................................................4
www.ti.com Revision History
SLAU150A – DECEMBER 2004 – REVISED OCTOBER 2021
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STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

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2
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.

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3
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.