Texas Instruments AM64 SK EVM Series User manual

User's Guide
AM64x SK EVM
ABSTRACT
This technical user’s guide describes the hardware architecture of the AM64x SKEVM. The AM64x processor
comprises of a Dual-Core 64-bit Arm-Cortex A53 microprocessor, 2x Dual core Arm® Cortex®-R5F MCUs and an
Arm Cortex-M4F MCU.
The AM64x starter kit is a stand-alone test and development platform that is an excellent choice for accelerating
the prototype phase of the next design. The kit includes: wired and wireless connectivity, three expansion
headers, multiple boot options and flexible debug capabilities.
The starter kit is equipped with AM64x processor from TI and an optimized feature-set to allow the user to create
commercial and industrial devices using Ethernet-based, USB, and serial wired interfaces plus 2.4-GHz and
5-GHz wireless communications. Two 1-Gbps Ethernet Ports for wired connectivity are on-board, in addition to
three expansion headers (PRU, MCU, User) headers to expand the functionality of the board. Using standard
serial protocols such as UART, I2C, and SPI, the starter kit can interface with a multitude of other devices,
acting as a communications gateway. Receiving 5-V power from a standard USB-C port, the starter kit allows
the user to access the R5F cores of the AM64x; making the device an excellent choice as a programmable
logic controller (PLC) or motor controller, processing sensor inputs and managing peripherals in real-time while
running Linux on the A53 cores, and making the device the central engine in a remote industrial communication
network. The embedded emulation logic allows for emulation and debugging using standard development tools
such as Code Composer Studio™ from TI.
Note
This evaluation board is a pre-production release and has several known issues that must not be
copied into a production system. For detailed information, see Section 5.
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Table of Contents
1 Key Features........................................................................................................................................................................... 4
2 EVM Revisions and Assembly Variants................................................................................................................................4
3 Important Usage Notes...........................................................................................................................................................5
4 System Description................................................................................................................................................................ 6
4.1 Key Features......................................................................................................................................................................7
4.2 Functional Block Diagram.................................................................................................................................................. 9
4.3 Power-On/Off Procedures................................................................................................................................................10
4.3.1 Power-On Procedure.................................................................................................................................................10
4.3.2 Power-Off Procedure................................................................................................................................................. 11
4.4 Peripheral and Major Component Description..................................................................................................................11
4.4.1 Clocking.....................................................................................................................................................................12
4.4.1.1 Ethernet PHY Clock............................................................................................................................................ 12
4.4.1.2 AM64x SoC Clock...............................................................................................................................................12
4.4.2 Reset......................................................................................................................................................................... 12
4.4.3 Power........................................................................................................................................................................ 13
4.4.3.1 Power Input.........................................................................................................................................................13
4.4.3.2 USB Type-C Interface for Power Input................................................................................................................14
4.4.3.3 Power Fault Indication........................................................................................................................................ 15
4.4.3.4 Power Supply......................................................................................................................................................15
4.4.3.5 Power Sequencing..............................................................................................................................................16
4.4.3.6 Power Supply......................................................................................................................................................17
4.4.4 Configuration............................................................................................................................................................. 18
4.4.4.1 Boot Modes.........................................................................................................................................................18
4.4.5 JTAG..........................................................................................................................................................................21
4.4.6 Test Automation.........................................................................................................................................................22
4.4.7 UART Interface..........................................................................................................................................................25
4.4.8 Memory Interfaces.....................................................................................................................................................26
4.4.8.1 LPDDR4 Interface...............................................................................................................................................26
4.4.8.2 MMC Interface.................................................................................................................................................... 26
4.4.9 Ethernet Interface...................................................................................................................................................... 30
4.4.9.1 DP83867 PHY Default Configuration..................................................................................................................30
4.4.9.2 DP83867 – Power, Clock, Reset, Interrupt and LEDs........................................................................................ 34
4.4.9.3 Industrial Application LEDs................................................................................................................................. 36
4.4.10 USB 3.0 Interface.................................................................................................................................................... 36
4.4.11 PRU Connector........................................................................................................................................................37
4.4.12 User Expansion Connector......................................................................................................................................38
4.4.13 MCU Connector.......................................................................................................................................................40
4.4.14 Interrupt................................................................................................................................................................... 41
4.4.15 I2C Interface............................................................................................................................................................ 41
4.4.16 IO Expander (GPIOs).............................................................................................................................................. 42
5 Known Issues........................................................................................................................................................................43
5.1 Issue 1: LP8733x Max output Capacitance Spec Exceeded on LDO0 and LDO1...........................................................43
5.2 Issue 2: LP8733x Output Voltage of 0.9V Exceeds AM64x VDDR_CORE max Voltage Spec of 0.895 V...................... 43
5.3 Issue 3 - SDIO Devices on MMC0 Require Careful Trace Lengths to Meet Interface Timing Requirements.................. 43
5.4 Issue 4 - LPDDR4 Data Rate Limitation in Stressful Conditions......................................................................................44
5.5 Issue 5 - Junk Character.................................................................................................................................................. 44
5.6 Issue 6 - Test Power Down Signal Floating......................................................................................................................44
5.7 Issue 7 - uSD Boot Not Working...................................................................................................................................... 44
6 Regulatory Compliance........................................................................................................................................................47
7 Revision History................................................................................................................................................................... 47
List of Figures
Figure 4-1. Top View of Starter Kit Processor Board................................................................................................................... 6
Figure 4-2. Bottom View of Starter Kit Processor Board..............................................................................................................7
Figure 4-3. Starter Kit Processor Board Functional Block Diagram.............................................................................................9
Figure 4-4. Common Bootmode Switch Positions..................................................................................................................... 10
Figure 4-5. Top LED...................................................................................................................................................................11
Figure 4-6. AM64x SK EVM Clock Tree.................................................................................................................................... 12
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Figure 4-7. Overall Reset Architecture of the AM64x SK Event................................................................................................ 13
Figure 4-8. USB Type-C Interface for Power Input.................................................................................................................... 14
Figure 4-9. Power-Up and Power-Down Sequencing................................................................................................................16
Figure 4-10. Bootmode Switch Positions Example....................................................................................................................18
Figure 4-11. JTAG Interface.......................................................................................................................................................21
Figure 4-12. Test Automation Header........................................................................................................................................23
Figure 4-13. UART Interface......................................................................................................................................................25
Figure 4-14. LPDDR4 Interface................................................................................................................................................. 26
Figure 4-15. Micro SD Interface.................................................................................................................................................27
Figure 4-16. WiLink Module Interface........................................................................................................................................28
Figure 4-17. OSPI Interface.......................................................................................................................................................29
Figure 4-18. Board ID EEPROM................................................................................................................................................29
Figure 4-19. CPSW Ethernet PHY-1 Strap Settings.................................................................................................................. 31
Figure 4-20. CPSW Ethernet PHY-2 Strap Settings.................................................................................................................. 32
Figure 4-21. Ethernet Interface..................................................................................................................................................35
Figure 4-22. Ethernet Interface - LEDs......................................................................................................................................36
Figure 4-23. USB 3.0 Host Interface..........................................................................................................................................36
Figure 4-24. 54-Pin PRU Connector..........................................................................................................................................38
Figure 4-25. 40-Pin User Expansion Connector........................................................................................................................ 39
Figure 4-26. 28-Pin MCU Connector......................................................................................................................................... 40
Figure 4-27. I2C Interface..........................................................................................................................................................41
Figure 5-1. MMC1 Schematics.................................................................................................................................................. 45
Figure 5-2. MMC1 Layout.......................................................................................................................................................... 46
List of Tables
Table 2-1. AM64 SK EVM PCB Design Revisions, and Assembly Variants................................................................................ 4
Table 2-2. Summary of Known Issues......................................................................................................................................... 4
Table 4-1. SoC Clock Source.....................................................................................................................................................12
Table 4-2. Current Sourcing Capability and State of USB Type C Cable.................................................................................. 14
Table 4-3. Power Fault Indication LED...................................................................................................................................... 15
Table 4-4. Power Test Points..................................................................................................................................................... 15
Table 4-5. Power LEDs.............................................................................................................................................................. 16
Table 4-6. SoC Power Supply....................................................................................................................................................17
Table 4-7. BOOT-MODE Pin Mapping....................................................................................................................................... 19
Table 4-8. PLL Reference Clock Selection BOOTMODE [2:0].................................................................................................. 19
Table 4-9. Boot Device Selection BOOT-MODE [6:3]................................................................................................................19
Table 4-10. Backup Boot Mode Selection BOOT-MODE [12:10]...............................................................................................20
Table 4-11. Primary Boot Media Configuration BOOT-MODE [9:7]........................................................................................... 20
Table 4-12. Backup Boot Media Configuration BOOT-MODE [13]............................................................................................ 20
Table 4-13. cTI 20 Pin Connector (J14) Pin-outs.......................................................................................................................21
Table 4-14. List of Signals Routed to Test Automation Header J16...........................................................................................22
Table 4-15. Automation Header Signals Connected to XDS110................................................................................................23
Table 4-16. Test Automation Header (J16) Pin-Outs................................................................................................................. 24
Table 4-17. Strap Value Configuration....................................................................................................................................... 30
Table 4-18. Default Strap Setting of CPSW RGMII-1 Ethernet PHY......................................................................................... 32
Table 4-19. Default strap setting of CPSW RGMII-2 Ethernet PHY...........................................................................................33
Table 4-20. Selection of PRG0 Signals on PRU Connector...................................................................................................... 37
Table 4-21. 40 Pin User Expansion Connector..........................................................................................................................38
Table 4-22. 28 Pin MCU Connector........................................................................................................................................... 40
Table 4-23. IO Expander Pin Details..........................................................................................................................................42
Table 5-1. AM64 SK EVM Known Issues...................................................................................................................................43
Trademarks
Code Composer Studio™ and Sitara™ are trademarks of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All trademarks are the property of their respective owners.
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1 Key Features
• Software: TI Processor SDK Linux/ RT Linux kernel, Yocto file system, out-of-box demos including WiFi
• Processing: AM64x with 2x Arm Cortex-A53, 4x Arm Cortex-R5, 2x TI PRU_ICSSG
• Networking: WiFi (dual-band), Bluetooth/ BLE 5.1; 2x RJ-45 Ethernet 1000/100 Mbps
• Connectivity: 1x Type A USB 3.1 gen1 (SuperSpeed), on-board XDS110 JTAG Emulator and 3x UARTs via
micro-USB
• Expansion and prototyping: 40-pin Raspberry Pi (RPI4) HATs, PRU-ICSSG Real-Time I/O, and TI-MCU
headers
• Storage: 2GB LPDDR4
• Bootable interfaces on SK: Removable uSD, USB, 16 MB OSPI, Ethernet, UART
2 EVM Revisions and Assembly Variants
The various AM64 SK EVM PCB design revisions, and assembly variants are listed in Table 2-1. Specific PCB
revision is indicated in silkscreen on the PCB. Specific assembly variant is indicated with an additional sticker
label. Table 2-2 lists known board issues.
Table 2-1. AM64 SK EVM PCB Design Revisions, and Assembly Variants
PCB Revision Revision and Assembly Variant Description
PROC100E1 First prototype, early release revision of the AM64 SK EVM. Used a blue solder
mask.Implements the Sitara™ AM6442 MPU.
PROC100E2 First production release of the AM64 SK EVM. Uses a white solder mask.
Implements the Sitara AM6442 MPU.
PROC100E3 Production release of the SK-AM64 EVM. Uses a Red solder mask. Implements
the Sitara AM64x MPU with two PMIC power solution.
PROC100E4 Prototype revision of SK-AM64 EVM. Used a Green solder mask. Implements
the Sitara AM64x MPU with single PMIC power solution.
PROC100A Production release of SK-AM64B EVM. Used a Red solder mask. Implements
the High-Security Field-Securable (HS-FS) silicon Sitara AM64x MPU with
single PMIC power solution.
Table 2-2. Summary of Known Issues
ID Severity Summary HW Versions Affected Fix
1 HIGH AM64x power
requirements not met by
power solution
E1, E2, E3 E4
2 HIGH AM64x voltage spec not
met
E1, E2, E3 E4
3 INFO Do not use MMC0 for
SDIO devices
E1, E2 E3
4 MEDIUM LPDDR4 data rate
limitation under stressful
benchmarking conditions
E1, E2 E3
5 INFO Junk Character on UART
Console
E3 E3A
6 MEDIUM Test power down signal is
floating
E4 RevA
7 HIGH uSD boot not working Rev A N/A
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3 Important Usage Notes
Please read through this section prior to using your AM64x Starter Kit. These notes are intended to make your
evaluation as trouble-free as possible. If you have any questions, please create a post on E2E and request
clarification.
Verify your intended boot media against the boot modes described the Configuration section later in this
document.
The AM64x Starter Kit shall be powered through the USB-C port (no data or display alt-mode support)/
The USB-C power controller on the AM64x Starter Kit is expecting a negotiation sequence with the power-
delivery source, and requires a source capable of supplying 5 V at 3 A. A red LED on the bottom of the AM64x
Starter Kit illuminates if the power-delivery source cannot meet these requirements.
Older and low-cost mains voltage to 5VDC USB type-A bricks intended for powering or charging consumer
electronics do not have the capability to properly complete the negotiation sequence with the USB-C power
controller on the AM64x Starter Kit, and prevents the EVM from powering on. Guidelines on recommended
supplies are given in the Power-On/Off Procedures section.
Caution AM64x Starter Kit shall not be powered through the 5V0 or 3V3 pins on the 40-pin "User Expansion
Connector". The AM64x Starter Kit was not designed to be powered through the expansion headers.
Caution Expansion headers on the AM64x Starter Kit are not fail-safe. This means expansion boards shall not
drive any I/O pins while the AM64x Starter Kit is powered off. Doing so violates AM64x data sheet specifications
and can cause damage to the processor or other components on the board, and is not covered by warranty.
The 40-pin "User Expansion Connector" was designed to match the types of signals and hardware interfaces
found on the RPI4 40-pin connector, thereby enabling a large percentage of community developed add-on
boards at a hardware level. Some deeper alternate pin functions do not match those found on the RPI4 due to
the nature of each SoC vendor deciding their own pin function multiplexing.
Attention: Concerning HAT compatibility with the 40-pin "User Expansion Connector", always check the
hardware resources required by HAT, and the active pin function PRIOR to attaching the HAT to the AM64x
Starter Kit. Pin multiplex settings can require a change in the bootloader first.
Caution: ESD Susceptible
Electrostatic discharge (ESD) can damage equipment and impair electrical circuitry. ESD can occur when
electronic printed circuit cards are improperly handled and can cause complete or intermittent failures.
Starter Kit Evaluation Board contains ESD Sensitive Electronic Devices. Hence due care must be taken while
handling these boards. SK EVM must be used under controlled Lab Environment with All ESD Safe Precautions
being adapted by the Test Engineers and Developers.
Please refer below for the precautionary measures:
• Make sure that the user is using the equipment in the ESD protected lab environment.
• Persons handling the product must have electronics training and observe good engineering practice
standards.
• Wear an ESD-preventive coat, ESD slippers, or wrist strap, making sure that the gear makes good skin
contact.
• Handle components by only their handles or edges; do not touch the printed circuit boards or connectors.
• Avoid contact between the printed circuit boards and clothing. The wrist strap only protects components from
ESD voltages on the body; ESD voltages on clothing can still cause damage so wear ESD coat.
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4 System Description
Figure 4-1. Top View of Starter Kit Processor Board
Note: Two USB Micro-B Receptacles
J12: XDS110 USB TO MAIN UART1
J11: DEBUG CONSOLE (MCU UART0 and MAIN UART1)
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Figure 4-2. Bottom View of Starter Kit Processor Board
4.1 Key Features
Major Features of AM64B SKEVM are as follows:
• Includes AM64x SoC, Memory, boot interfaces, on-board JTAG and power supply circuit.
• Provides general purpose expansion interfaces for hardware add on boards.
• Operates in a stand-alone mode without any of the daughter cards.
• Powered through USB Type-C Connector.
• External Communication through Giga-Bit Ethernet Ports (x2) and USB 3.0 Type-A (x1).
• USB3.0 high speed interface terminated on Type-A USB Host connector.
• Wi-link WL1837 Module with support for both Wi-Fi and Bluetooth.
• Optionally supply the power needed for the daughter cards (limited to 500 mA on 3V3 and 155 mA on 5 V
rail).
AM64x System-on-Chip (SoC):
• AM64x combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG with up to two Arm Cortex-A53
cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU. The SoC is soldered to the PCB without
socket.
Memory
• 2GB DDR4 supporting data rate up to 1600MT/s
• Micro Secure Digital (SD) Card with UHS-1 support
• 512 Mbit OSPI EEPROM
• 512 Kbit Inter-Integrated Circuit (I2C) board ID EEPROM
High Speed Interface:
• Two CPSW Gigabit Ethernet (RGMII) ports interfaced with Texas Instruments Gigabit Ethernet PHYs
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• One USB3.0 Host interface terminated on a USB Type-A connector for data transfer
Expansion Bus:
• 3x Expansion connectors using 0.1" spaced 0.025" square post connectors
– 1x Raspberry Pi compatible 40 pin expansion connector allowing seamless integration to HAT boards
– 1x PRU 54 pin connector to PRG0 interface
– 1x MCU 28 pin connector
Debug:
• XDS110 On-Board Emulator
• Supports 20-pin JTAG connection from external emulator
• Automatic selection between on-board and external emulator (higher priority)
• Dual port Universal Asynchronous Receiver/Transmitter (UART) to USB circuit over micro-B USB connector
prodivded via CP2105
• 2x 8-Bit DIP Switches for user selection of SoC Boot Modes
• 1x Push button for Interrupt SoC GPIO
• LEDs. One for Main Power, one for PMIC good, 1 for MCU Domain, 1 for MCU Domain GPIO and others
connected to the two industrial interfaces
Power Supply:
• The SK-AM64B EVM is powered through a USB Type-C Connector.
• 5 V is stepped down to 3V3 by LM61460AASQRJRRQ1 regulator. VCC3V3SYS_EXT is the input supply to
the PMIC.
• TPS6522053RHBR PMIC and other discrete regulators on the starter kit provide all the required power
supplies for SoC and other peripherals (LPDDR4, Wi-Fi Module, and OSPI, Clock buffers, Level translators
and logic gates).
• Dedicated regulators are also provided for:
– Powering the always-on circuits of the Test Automation Header section.
– E-Fuse programming of the SoC.
– XDS110 Debugger section.
– 3V3 for SoC and peripherals.
– 1V0 for Ethernet Phys.
•Recommended Power Supplies:
– CUI Inc. 5 V 15W AC/DC External Wall Mount Adapter - SWC15-S5-NB
– GlobalTek Inc. 5 V 15W AC/DC External Mount Wall Adapter - WR9QA3000USBC3MNA-CIMR6B
– Qualtek USB 2.0 Cable C Male to C Male 3.28' Shielded Cable for powering the boards through a laptop
Type-C port - 3021091-01M
• Status Output: LEDs to indicate power status
Compliance:
• RoHS Compliant
• REACH Compliant
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4.2 Functional Block Diagram
Figure 4-3 shows the functional block diagram of the AM64x SK EVM.
Figure 4-3. Starter Kit Processor Board Functional Block Diagram
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4.3 Power-On/Off Procedures
Power to the EVM is provided through an external AC/DC converter providing 5 V, 3 A (max) DC voltage to the
USB Type-C Port.
4.3.1 Power-On Procedure
Note
The Processor SDK Linux image provides an interactive user demo by default. Once booted, the
board acts as a Wireless access point with SSID AM64xSK-AP and Password tiwilink8. Once
connected, the demo can be found by navigating to http://192.168.43.1:8081. More details can be
found on the Software Quick Start Guide, located on the product page.
1. Place the SK EVM boot switch selectors (SW2, SW3) into selected boot mode. Example boot-modes for SD
card and no-boot are shown below. For additional options, see Section 4.4.4.1.
Figure 4-4. Common Bootmode Switch Positions
2. Connect your boot media (if applicable).
3. Attach the 5 V USB Type-C cable to the SK EVM Type-C (J8) Connector.
4. Connect the other end of the Type-C cable to the source, either AC Power Adapter, or Type C source device
(such as a Laptop computer).
5. Use ON/OFF sliding switch SW5 to Power on the board.
6. Visually inspect the LEDs against the reference photos below. The following LEDs are illuminated: LD2 and
LD16 on top side of the board.
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Figure 4-5. Top LED
7. XDS110 JTAG and UART debug console output are routed to micro-USB ports J12 and J11, respectively.
Note
Linux console output is routed to the second enumerated ttyUSB port.
4.3.2 Power-Off Procedure
1. Use ON/OFF sliding switch SW5 to Power off the Board.
2. Disconnect AC power from AC/DC converter.
3. Remove the USB Type-C cable from the EVM.
4.4 Peripheral and Major Component Description
The following sections provide an overview of the different interfaces and circuits on the AM64x SK EVM.
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4.4.1 Clocking
4.4.1.1 Ethernet PHY Clock
The clock buffer of part number LMK1C1103PWR is used to drive the 25 MHz clock to the Ethernet PHYs.
LMK1C1103PWR is a 1:3 LVCMOS clock buffer, which takes a 25 MHz crystal/LVCMOS reference input and
provides four 25 MHz LVCMOS clock outputs. The source for the clock buffer is either the CLKOUT0 pin from
the SoC or a 25 MHz oscillator (ECS-2520MV-250-CN-TR). The selection can be made using a set of resistors.
By default, the oscillator is used as input to the clock buffer in SK-AM64B EVM. Output Y2 and Y3 of the clock
buffer LMK1C1103PWR are used as a reference clock input for two Gigabit Ethernet PHYs in SKEVM.
Figure 4-6. AM64x SK EVM Clock Tree
Note
Resistors that are marked with a red color box are DNI.
4.4.1.2 AM64x SoC Clock
Output Y0 from the clock buffer LMK1C1103PWR is used as a reference clock for the SoC on SKEVM. An
optional 25 MHz crystal (XRCGB25M000F3M00R0) is also provided for driving the SoC. Selection of clock for
the SoC is done using resistors. By default an output from the SoC_CLKIN clock buffer is provided to the SoC.
For clock source selection, see Table 4-1.
Table 4-1. SoC Clock Source
Clock Source to SoC Part Number Mount Unmount
Clock Buffer LMK1C1103PWR R116 R40,R41
25 MHz Crystal XRCGB25M000F3M00R0 R40,R41 R116
4.4.2 Reset
The AM64x SoC has the following resets:
• RESETSTATz is the warm reset status output for Main domain.
• PORz_OUT is the power ON reset status output from Main and MCU domain.
• MCU_PORz is the power ON/ Cold Reset input for MCU and Main domain.
• MCU_RESETz is the warm reset input for MCU domain.
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• MCU_RESETSTATz is the Warm Reset status output for MCU domain.
SoC_PORz signal is provided by ANDing the PGOOD signal of PMIC and JTAG emulator reset. MCU_PORz
is provided by ANDing the CONN_MCU_PORz from MCU Connector, TEST_PORZn from Test Automation
Connector and SoC_PORz.
MCU Domain warm reset (MCU_RESETz) and MCU Domain cold reset (MCU_PORz) of the SoC is achieved by
CONN_MCU_RESETz and CONN_MCU_PORz respectively from the Safety Connector.
Upon Power on Reset, all peripheral devices connected to the main domain get reset by RESETSTATz along
with a GPIO control as shown in Figure 4-7.
Figure 4-7. Overall Reset Architecture of the AM64x SK Event
4.4.3 Power
4.4.3.1 Power Input
The AM64x SK EVM receives 5 V input from a USB Type-C connector. The following sections describe the
power distribution network topology that supply the SK EVM board, supporting components and reference
voltages.
SK-AM64B EVM board includes a power solution based on PMIC and few discrete regulators. The initial stage of
the power supply is 5 V from a Type-C USB connector with part No 2012670005 from Molex, which supports 3 A
current rating and necessary protection circuits for over current and voltage surge. The 5 V input (VUSB_MAIN)
from the USB Connector is used to generate 3.3V (VCC3V3SYS_EXT) with the help of switching regulator
(part No. LM61460AASQRJRRQ1), which is the input supply to the PMIC section. PMIC generates necessary
voltages required for the SKEVM.
An ON/OFF Toggle switch (with part number AS11AP) is provided to initiate the power on and power down
sequence of the Board. This switch connects TPS6522053_EN enable signal to ground when switch is in OFF
position and enables PMIC TPS6522053RHBR when the switch is in ON position, thereby initiating the Power –
Up Sequence. A low on enable pin of the TPS6522053RHBR PMIC by sliding the switch to OFF position initiates
the Power-down Sequence.
Additionally, TEST_POWERDOWN from the test automation header is also connected to the enable pin of
TPS6522053RHBR PMIC to control on/off of the EVM via the test automation board. The test automation
connector requires 3.3V supply, which is provided from power mux (part No: TPS2121RUXT). The inputs to the
power mux are 3V3 from two different sources. First, 3V3 supply is generated from 5 V (XDS_USB_VBUS) using
an LDO (Part No: TPS79601DRBR). This is generated as long as Micro B cable is connected to J12. Second,
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3V3 input is generated from 5 V (VUSB_MAIN) using a switching Buck regulator (part No: TPS62177DQCR).
This is an Always ON Regulator and is supplying the necessary power as long as the USB Type C Cable is
plugged in. When Both Type C cable and Micro B cable at J12 are connected, the mux priority is set to the
first input supply (VCC3V3_XDS). If USB is not connected to the J12, then the mux output is from VCC3V3_TA,
which is an always ON power supply.
4.4.3.2 USB Type-C Interface for Power Input
The AM64x SKEVM is powered through a USB type-C Connector. The USB Type-C source is capable of
providing 3 A at 5 V and advertises the current sourcing capability through CC1 and CC2 signals. On SK EVM,
CC1 and CC2 from the USB Type-C connector are interfaced to the TUSB320LAIRWBR port controller IC. This
device uses the CC pins to determine port attach and detach, cable orientation, role detection, and port control
for Type-C current mode. This IC allows for pin swapping when the Type-C cable is flipped and inserted. The CC
logic block monitors the CC1 and CC2 pins for pull-up or pull-down resistances to determine when a USB port
has been attached, the orientation of the cable, and the role detected. The CC logic detects the Type-C current
mode as default, medium, or high depending on the role detected. Pin PORT is pulled down to ground through
a resistor to configure as UFP (Upward Facing Port) mode. VBUS detection is implemented to determine a
successful attach in UFP mode. Pin ADDR is left open to configure as GPIO mode. OUT1 and OUT2 pin is
connected to a NOR gate. Active low on both OUT1 and OUT2 pin advertises high current (3 A) in the attached
state which enables the VUSB_MAIN power switch to provide the VUSB_PMIC supply which powers one PMIC.
In UFP mode, the TUSB320 device constantly presents pull-down resistors (Rd) on both CC pins. The TUSB320
device monitors the CC pins for the voltage level corresponding to the Type-C mode current advertisement
by the connected DFP. The TUSB320 device de-bounces the CC pins and waits for VBUS detection before
successfully attaching. As a UFP, the TUSB320 device detects and communicates the advertised current level
of the DFP to the system through the OUT1 and OUT2 GPIOs. SKEVM power requirement is 5 V @ 3 A. If the
source is not capable of providing 5 V at 3 A, output at the NOR gate becomes low which disables VUSB_Main
power switch. Hence all power supplies except VCC3V3_TA remain in the off state. The board gets powered ON
completely only when the source is capable of providing 5 V at 3 A.
Figure 4-8. USB Type-C Interface for Power Input
Table 4-2. Current Sourcing Capability and State of USB Type C Cable
OUT1 OUT2 Advertisement
H H Default current in unattached state
H L Default current in attached state
L H Medium current (1.5A) in attached state
L L High current (3.0A) in attached state
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4.4.3.3 Power Fault Indication
Red led LD15 is used to indicate power fault condition (for example, current less than 3A) by using USB type C
configuration channel logic and port controller IC.
Table 4-3. Power Fault Indication LED
LED ON Status OFF Status
LD15 Source provides less than 15W Source provides the required 15W power
4.4.3.4 Power Supply
The SK-AM64B EVM board utilizes one PMIC and three discrete regulators to supply the necessary voltage and
power to SOC, various memories, Wi-link module and other peripherals on the board. Probe points for power
supplies provided on the SKEVM Board are mentioned in Table 4-4.
Table 4-4. Power Test Points
SI. No Power Supply Probe Point Ground Probe Point
Expected Voltage
(V)
Points on Top Side
1 VUSB_MAIN TP28 DGND J3.2 5
2 XDS_USB_VBUS TP75 DGND J3.2 5
3 VCC_3V3_SYS TP80 DGND J3.2 3.3
4 VDDAR_CORE TP85 DGND J3.2 0.85
5 VPP_1V8 TP89 DGND J3.2 0
6 VDD_CORE TP81 DGND J3.2 0.75
7 VDD_LPDDR4 TP83 DGND J3.2 1.1
8 VDD_1V0 TP88 DGND J3.2 1
9 VCC1V8 TP82. DGND J3.2 1.8
10 VDD_PHY_2V5 TP87 DGND J3.2 2.5
11 VDDSHV_SD_IO_PM
IC
TP84 DGND J3.2 3.3
12 VDD_MMC1 C47.1 DGND J3.2 3.3
13 VBUS_USB_CP2105 TP76 DGND J3.2 5
14 VCC3V3_XDS TP74 DGND J3.2 3.3
15 VDDSHV_SD_IO TP15 DGND J3.2 3.3
Points on Bottom Side
16 VCC3V3SYS_EXT TP78 DGND J3.2 3.3
17 VDDA_1V8 TP86 DGND J3.2 1.8
18 VCC3V3_TA C340.1 DGND J3.2 3.3
19 VCC3V3_TA_XDS C421.1 DGND J3.2 3.3
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Table 4-5 gives details about power-good LEDs provided on SKEVM board to give users positive confirmation of
the status of each supply. Figure 4-7 highlights the power-good LEDs in SK EVM board.
Table 4-5. Power LEDs
SI.No Power Supply LED Part Reference
1 VCC3V3SYS_EXT LD2
2 VCC_3V3_SYS LD16
3 VDDAR_CORE LD16
4 VDDA_1V8 LD16
5 VDD_LPDDR4 LD16
6 VDD_CORE LD16
7 VCC1V8 LD16
8 VDDSHV_SD_IO_PMIC LD16
9 VDD_PHY_2V5 LD16
10 VDDA_1V8 LD16
11 VDD_CP2105 LD18
4.4.3.5 Power Sequencing
Figure 4-9 shows the Power Up and Power Down Sequence of all the Power supplies present on the SK EVM
Board.
Figure 4-9. Power-Up and Power-Down Sequencing
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4.4.3.6 Power Supply
The SoC Core voltage (VDD_CORE) of the AM64x SoC is set to 0.75V. SoC Array Core Voltage (VDDR_CORE)
and other array core voltages (VDDA_0P85_SERDES0_C, VDDA_0P85_SERDES0, VDDA_0P85_USB0,
VDD_DLL_MMC0 and VDD_MMC0) are configured to 0.85V and are supplied through a common rail.
The SoC has different IO groups. Each IO group is powered by specific power supplies as given in Table 4-6.
Table 4-6. SoC Power Supply
SI.No Power Supply SoC Supply Rails IO Power Group Power
1 VDDAR_CORE VDDA_0P85_SERDES0 SERDES0 0.85
VDDA_0P85_SERDES0_
C
0.85
VDDA_0P85_USB0 USB0 0.85
VDD_MMC0 MMC0 0.85
VDDR_CORE CORE 0.85
2 SoC_DVDD3V3 VDDSHV_MCU MCU 3.3
VDDA_3P3_USB0 USB0 3.3
VDDSHV0 General 3.3
VDDSHV1 PRG0 3.3
VDDSHV2 PRG1 3.3
VDDSHV3 GPMC 3.3
VMON_3P3_MCU 3.3
VMON_3P3_SOC 3.3
3 VDDA_1V8_MCU VDDA_MCU MCU 1.8
4 VDDA_1V8_SERDES VDDA_1P8_SERDES0 SERDES0 1.8
5 VDDA_1V8_USB0 VDDA_1P8_USB0 USB0 1.8
6 VDDA_1V8 VDDS_OSC OSC0 1.8
VDDA_TEMP_0/1 1.8
VDDA_PLL_0/1/2 1.8
7 VDDS_DDR VDDS_DDR DDR0 1.1
VDDS_DDR_C 1.1
8 SOC_DVDD1V8 VDDSHV4 FLASH 1.8
VDDS_MMC0 MMC0 1.8
VMON_1P8_MCU 1.8
VMON_1P8_SOC 1.8
9 VDDSHV_SD_IO VDDSHV5 MMC1 3.3
10 VDDS_MMC0/
ADC0_VREFP
VDDS_MMC0 MMC0 0
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4.4.4 Configuration
4.4.4.1 Boot Modes
The boot mode for the SK EVM board is defined by two banks of switches, SW2 and SW3, or by the I2C buffer
connected to the test automation connector. This allows for AM64x boot mode control by either the user (DIP
Switch Control) or the test automation header. At the minimum, all the boot mode pins require a footprint for
a pull-up or pull-down resistor. Any boot mode pin that must be toggled to support a needed boot mode must
have a weak pull-down resistor and a switch (416131160808 from Wurth) capable of connecting a stronger
pull-up resistor. The switch disconnects the pull-up resistor in the OFF position. For boot mode pins that are not
controlled by switches, pull-up and pull-down resistor pads are included. Various boot modes for AM64x must be
controlled by the user with the help of 8-Bit DIP switches. The following boot modes are supported by SK EVM:
• OSPI
• MMC1 - SD-Card
• CSPW Ethernet
• USB devices
The boot mode pins of the SoC have associated alternate functions during normal operation. Hence, isolation
is provided using the Buffer IC to cater for alternate pin functionality. The output of the buffer is connected to
the bootmode pins ON the AM64x and the output is enabled when the bootmode is needed during a reset
cycle. The input to the buffer is connected to the DIP switch circuit and to the output of an I2C buffer set by the
test automation circuit. If the test automation circuit is going to control the bootmode, then all the switches are
manually set to the OFF position. The bootmode buffer are powered by an always ON power supply to make
sure that the bootmode remains present even if the SoC power is cycled..
Figure 4-10 and Table 4-7 provide guidance to select the boot mode before the device is powered up.
Figure 4-10. Bootmode Switch Positions Example
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Table 4-7. BOOT-MODE Pin Mapping
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserv
ed
Reserv
ed
Backup
Boot
Mode
Config
uration
Backup Boot Mode Primary Boot Mode
Configuration
Primary Boot Mode PLL Configuration
• BOOT-MODE [0:2] – Denote system clock frequency for PLL configuration. By default, this bits are set for 25
MHz.
Table 4-8 gives details ON PLL reference clock selection.
Table 4-8. PLL Reference Clock Selection BOOTMODE [2:0]
SW3.6 SW3.7 SW3.8 PLL REF CLK (MHz)
OFF OFF OFF 19.2
OFF OFF ON 20
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON 27
ON ON OFF Reserved
ON ON ON No PLL Configuration Done (slow
speed backup)
• BOOT-MODE [3:6] – This provides primary boot mode configuration to select the requested boot mode after
POR, that is, the peripheral/memory to boot from. Table 4-9 provides primary boot device selection details.
Table 4-9. Boot Device Selection BOOT-MODE [6:3]
SW3.2 SW3.3 SW3.4 SW3.5
Primary Boot Device
Selected
OFF OFF OFF OFF Reserved
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII
OFF ON OFF ON Ethernet RMII
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/SD card
ON OFF OFF ON emmc
ON OFF ON OFF USB
ON OFF ON ON Reserved
ON ON OFF OFF GPMC NOR
ON ON OFF ON PCIe
ON ON ON OFF xSPI
ON ON ON ON No boot/Dev Boot
• BOOT-MODE [10:12] – Select the backup boot mode, that is, the peripheral/memory to boot from, if primary
boot device failed.
Table 4-10 provides backup boot mode selection details.
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Table 4-10. Backup Boot Mode Selection BOOT-MODE [12:10]
SW2.4 SW2.5 SW2.6 Backup Boot Device Selected
OFF OFF OFF None (No backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C
• BOOT-MODE [9:7] – These pins provide optional settings and are used in conjunction with the primary boot
device selected.
Table 4-11 gives primary boot media configuration details.
Table 4-11. Primary Boot Media Configuration BOOT-MODE [9:7]
SW2.7 SW2.8 SW3.1 Boot Device
Reserved Reserved
Speed Iclk Csel OSPI
Reserved Iclk Csel QSPI
Reserved Mode Csel SPI
Clkout Delay Link stat Ethernet RGMII
Clkout Clk src Reserved Ethernet RMII
Bus Reset Reserved Addr I2C
Reserved Reserved UART
Port Reserved Fs/raw MMC/ SD card
Reserved voltage eMMC
Reserved Mode Lane swap USB
Reserved Reserved
Reserved GPMC NOR
Reserved Clocking PCIe
Speed Pin Cmd Csel xSPI
Reserved No/Dev No boot/Dev Boot
• BOOT-MODE [13] – These pins provide optional settings and are used in conjunction with the backup boot
device devices. Switch SW2.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.
• BOOT-MODE [14:15] – Reserved.
Table 4-12 provides backup boot media configuration options.
Table 4-12. Backup Boot Media Configuration BOOT-MODE [13]
SW2.3 Boot Device
Reserved None
Mode USB
Reserved Reserved
Reserved UART
IF Ethernet
Port MMC/SD
Reserved SPI
Reserved I2C
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