Texas Instruments LM5175RHFEVM-HD User manual

LM5175RHF (QFN) EVM
User's Guide
Literature Number: SNVU518
April 2016

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Table of Contents
Contents
1 High Density EVM Description............................................................................................... 3
1.1 Additional Features ...................................................................................................... 3
2 EVM Photos......................................................................................................................... 4
3 Signal Connections and Test Point Descriptions ..................................................................... 5
3.1 Test Point Descriptions.................................................................................................. 5
3.2 Optional Configurations ................................................................................................. 5
3.3 Signal Connections ...................................................................................................... 5
3.3.1 Input Voltage Monitoring..................................................................................... 5
3.3.2 Output Voltage Monitoring................................................................................... 5
3.3.3 Power Good Voltage Output................................................................................ 5
3.3.4 Enable Voltage Input......................................................................................... 5
3.3.5 SYNC Input.................................................................................................... 6
4 Test Setup and Procedure..................................................................................................... 6
4.1 Test Equipment........................................................................................................... 7
4.2 Recommended Test Setup ............................................................................................. 7
4.2.1 Input Connections ............................................................................................ 7
4.2.2 Output Connections.......................................................................................... 7
4.3 Test Procedure........................................................................................................... 8
4.3.1 Line, Load Regulation and Efficiency...................................................................... 8
4.3.2 Control Loop Gain and Phase .............................................................................. 8
5 Test Data and Performance Curves........................................................................................ 8
5.1 Efficiency .................................................................................................................. 8
5.2 Line and Load Regulation ............................................................................................. 11
5.3 Bode Plots............................................................................................................... 11
5.4 Operating Waveforms.................................................................................................. 13
5.4.1 Switch Node Voltages and Inductor Current ............................................................ 13
5.4.2 Output Voltage Ripple, 20-MHz Bandwidth.............................................................. 15
5.4.3 Startup Waveform........................................................................................... 15
6 EVM Documentation ........................................................................................................... 17
6.1 Schematic................................................................................................................ 17
6.2 PCB Layout.............................................................................................................. 18
6.3 Bill of Materials.......................................................................................................... 22
Revision History.......................................................................................................................... 23

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LM5175RHF (QFN) EVM User Guide
User's Guide
SNVU518–April 2016
LM5175RHF (QFN) EVM User Guide
1 High Density EVM Description
The LM5175RHFEVM-HD demonstrates a compact buck-boost design using the LM5175 high
performance 4-switch buck-boost controller. This evaluation module is designed to operate with input
voltage from 5 V to 42 V and provide a regulated 12 V output with load current up to 6 A. The transition
region control method of the LM5175 maintains high efficiency over the entire operating input voltage in
contrast with a conventional four-switch buck-boost converter which has a drop in efficiency at VIN close to
VOUT. The switching frequency is set at 400 kHz and can be synchronized to an external clock signal. The
board specifications are listed in Table 1.
Table 1. Board Specifications
Parameter Value
Input Voltage (VIN) 5.5V to 42V (45V transient)
Output Voltage (VOUT) 12V
Maximum Output Current (IOUT) 6A
Default Switching Frequency (fsw) 400 kHz
Synchronizable Frequency Range Up to 600 kHz
Efficiency (IOUT = 5A, VIN = 6V to 36V) 95.1% to 98.4%
Board Size (6 layers) 50 mm x 43 mm
(1.98 in x 1.7 in)
1.1 Additional Features
• Smooth Buck-Boost Operation
• Ultra-high (>98%) peak power conversion efficiency
• High power density compact design
• Adjustable output voltage using TRIM
• Resistor programmable switching frequency (adjustable) with optional external synchronization (SYNC)
up to 600 kHz
• Cycle-by-cycle overcurrent protection via shunt resistor current sensing
• Optional hiccup mode overload protection (off by default)
• Default forced PWM (CCM) fixed switching operation with option to set diode emulation mode (DCM)
• Programmable VIN UVLO threshold and hysteresis
• Spread spectrum dither option for reduced EMI
• Power Good indicator
• Input circuit damping and energy storage provided by bulk electrolytic capacitor
• Easy access to PGOOD, ENABLE, TRIM and SYNC using conveniently located test points

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2 EVM Photos
Figure 1. EVM Top Side
Figure 2. EVM Bottom Side

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3 Signal Connections and Test Point Descriptions
3.1 Test Point Descriptions
Table 2. Test Point Descriptions
LABEL DESCRIPTION
VIN Input voltage positive power and sense connection
GND Input voltage negative power and sense connection
VOUT Output voltage positive power and sense connection
GND Output voltage negative power and sense connection
AGND Analog GND
SYNC External frequency synchronization input (SYNC). This terminal is connected to
the RT/SYNC pin of the LM5175 controller through a 100 pF capacitor on the
board.
EN ENABLE input; tie to GND to disable converter
PGOOD Power Good output
3.2 Optional Configurations
Table 3. Optional Configurations
COMPONENT DESCRIPTION
R8 R8 can be used to select DCM or CCM mode and for enabling hiccup mode current limit. See LM5175 device datasheet for R8 values. Default EVM configuration is
CCM/No hiccup.
Rcd Dither is disabled by default. Replace with an appropriate capacitor to enable dither.
See LM5175 datasheet on how to set the dither frequency.
3.3 Signal Connections
3.3.1 Input Voltage Monitoring
The LM5175RHFEVM-HD provides two solder lug test points for measuring input voltage at the input
banana connections. This allows the user to measure the actual input voltage without losses from input
cables and connectors. All input voltage measurements should be made between VIN and GND test
points.
3.3.2 Output Voltage Monitoring
The LM5175RHFEVM-HD provides two solder lug test points for measuring output voltage at the output
banana connections. This facilitates measurement of the output voltage without losses related to output
cables and connectors.
3.3.3 Power Good Voltage Output
The LM5175RHFEVM-HD provides a test point for measuring the PGOOD flag voltage. A 20-kΩpullup
resistor, Rpg, to VCC is included. For true open-drain operation with no pullup, remove Rpg. One possible
scenario where a PGOOD pullup is not required involves PGOOD of an upstream converter connected to
the EN input of a downstream converter to provide sequential startup of multiple regulators.
3.3.4 Enable Voltage Input
The LM5175RHFEVM-HD provides a test point for measuring the EN voltage. Shorting this test point to
GND disables the converter. The EN/UVLO voltage should not exceed the input voltage.

A COM
Ammeter Electronic Load
+ -
V
Voltmeter 1
COM V
Voltmeter 2
COM
+
-
Power Supply
-s +s
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3.3.5 SYNC Input
The LM5175RHFEVM-HD provides a test point for applying a synchronization (SYNC) input signal. The
free-running switching frequency is set at 400 kHz by resistor RT1. However, the converter aligns in
frequency and phase with that of the applied SYNC signal up to 600 kHz. If required, apply an external
SYNC signal with a frequency higher than the internal free-running frequency as per the LM5175 device
datasheet.
4 Test Setup and Procedure
Figure 3 shows the recommended test setup to evaluate the LM5175RHFEVM-HD. Working at an ESD
workstation, make sure that any wrist straps, boot straps or mats are connected referencing the user to
earth ground before power is applied to the EVM.
Figure 3. Test Setup Connection Diagram

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4.1 Test Equipment
Voltage Source: The input voltage source VIN should be a 0–50-V dc source capable of supplying 15 A.
Multimeters:
•Voltmeter 1: Input voltage at VIN to GND
•Voltmeter 2: Output voltage at VOUT to GND
•Ammeter: Input current (or use the power supply readout if its accuracy is deemed acceptable)
Electronic Load: The output load should be an electronic constant-resistance or constant-current mode
load capable of 0-10 A at 12 V.
Oscilloscope (optional): A digital or analog oscilloscope can be used to measure pertinent converter
waveforms. With the scope set to 20-MHz bandwidth and AC coupling, the output voltage ripple can be
measured directly across an output capacitor with a short ground lead normally provided with the scope
probe. Place the oscilloscope probe tip on the positive terminal of the output capacitor, holding the probe's
ground barrel through the ground lead to the capacitor's negative terminal. It is not recommended to use a
long leaded ground connection because this may induce additional noise given a large ground loop. To
measure other waveforms, adjust the oscilloscope as needed.
Fan: Depending on the EVM's operating conditions, the temperature rise of certain powertrain
components can approach 50°C. Although not mandatory, use a small fan capable of 200–400 LFM to
reduce component temperatures while the EVM is operating. Exercise care when touching the EVM while
the fan is not running. Always use caution when touching any circuits that may be live or energized.
4.2 Recommended Test Setup
4.2.1 Input Connections
• Prior to connecting the DC input source, it is advisable to limit the source current to 10 A maximum.
Make sure the input source is initially set to 0 V and connected to VIN and GND banana connections
as shown in Figure 3. While the on-board hybrid electrolytic capacitor provides input circuit damping,
an additional high-ESR input capacitor may be required if long input lines are used.
• Connect voltmeter 1 at VIN and GND test points to measure the input voltage.
• Connect ammeter to measure the input current.
4.2.2 Output Connections
• Connect an electronic load to VOUT and GND connections. Set the load to constant-resistance mode
or constant-current mode at 0 Adc before applying input voltage. Use short load lines to minimize
voltage drop to the load.
• Connect voltmeter 2 at VOUT and GND solder lugs to measure the output voltage.
• The output current level can be taken from the electronic load readout (if its accuracy is deemed
acceptable).

IOUT (A)
EFFICIENCY (%)
0 1 2 3 4 5 6
88
90
92
94
96
98
100
D001
VIN = 6V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 30V
VIN = 36V
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4.3 Test Procedure
4.3.1 Line, Load Regulation and Efficiency
• Set up the EVM as described above.
• Set target load in the electronic load using either constant resistance or constant current mode.
• Increase input source from 0 V to 42 V, using voltmeter 1 to measure input voltage.
• Use voltmeter 2 to measure output voltage, VOUT.
• Vary load from 0 to 6 Adc, VOUT should remain within load regulation specification.
• Vary input source voltage from 5.5 V to 42 V, VOUT should remain within line regulation specification.
• Decrease load to 0 A. Decrease input source voltage to 0 V to power down.
4.3.2 Control Loop Gain and Phase
The resistor R16 on the LM5175RHFEVM-HD is a convenient injection point for loop response analysis.
• Set up EVM as described previously.
• Connect isolation transformer secondary across R16.
• Connect output signal amplitude measurement probe (TEST) to VOUT and input signal amplitude
measurement (REF) probe to opposite side of R16.
• Connect ground leads to the AGND test point as required.
• Apply 10 mV or less AC signal to the isolation transformer primary. Adjust amplitude as necessary.
• Sweep the frequency over the frequency range of interest (e.g. 100 Hz to 100 kHz) with 10 Hz or lower
post filter.
• Measure the control loop gain and phase characteristic. Record the crossover frequency and phase
margin.
• Disconnect isolation transformer before making other measurements (signal injection into the loop may
interfere with the integrity of other measurements).
5 Test Data and Performance Curves
5.1 Efficiency
Figure 4. Efficiency vs. Output Current

IOUT (A)
EFFICIENCY (%)
0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.4 0.5 0.7 1 2 3 4 5 6 7 8 910
20
30
40
50
60
70
80
90
100
CCM
DCM
Input Voltage (V)
Efficiency (%)
5 10 15 20 25 30 35 40
92
94
96
98
100 IOUT = 3A
IOUT = 6A
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Figure 5. Efficiency vs Input Voltage
Figure 6. Efficiency vs Output Current for VIN = 24 V

IOUT (A)
EFFICIENCY (%)
0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.4 0.5 0.7 1 2 3 4 5 6 7 8 910
40
50
60
70
80
90
100
CCM
DCM
IOUT (A)
EFFICIENCY (%)
0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.4 0.5 0.7 1 2 3 4 5 6 7 8 910
40
50
60
70
80
90
100
CCM
DCM
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Figure 7. Efficiency vs Output Current for VIN =6V
Figure 8. Efficiency vs Output Current for VIN = 12 V
Table 4. No Load Input Current (IQ) vs Input Voltage
VIN IQ (CCM) IQ (DCM)
24V 35 mA 2.6 mA
12V 22 mA 12 mA
6V 58 mA 41 mA

Fc = 4.5 kHz
3M§60o
IOUT (A)
VOUT (V)
0 1 2 3 4 5 6
11.5
11.6
11.7
11.8
11.9
12
12.1
12.2
12.3
12.4
12.5
+1%
-1%
VIN = 6V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 30V
VIN = 36V
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5.2 Line and Load Regulation
Figure 9. Line and Load Regulation
5.3 Bode Plots
Figure 10. Bode Plot for VIN = 6V, IOUT = 3A

Fc = 10 kHz
3M§77o
Fc = 9 kHz
3M§72o
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Figure 11. Bode Plot for VIN = 12V, IOUT = 3A
Figure 12. Bode Plot for VIN = 24V, IOUT = 3A

SW1
SW2
IL1
SW1
SW2
IL1
SW1
SW2
IL1
SW1
SW2
IL1
SW1
SW2
LM34935
SW1
SW2
IL1
SW1
SW2
IL1
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5.4 Operating Waveforms
5.4.1 Switch Node Voltages and Inductor Current
Figure 13. SW1, SW2, ILWaveforms: VIN = 6 V, VOUT = 12 V,
IOUT = 0 A Figure 14. SW1, SW2, ILWaveforms: VIN = 6 V, VOUT = 12 V,
IOUT = 5 A
Figure 15. SW1, SW2, ILWaveforms: VIN = 12 V, VOUT = 12
V, IOUT = 0 A Figure 16. SW1, SW2, ILWaveforms: VIN = 12 V, VOUT = 12
V, IOUT = 5 A
Figure 17. SW1, SW2, ILWaveforms: VIN = 16 V, VOUT = 12
V, IOUT = 0 A Figure 18. SW1, SW2, ILWaveforms: VIN = 16 V, VOUT = 12
V, IOUT = 5 A

SW1
SW2
IL1
SW1
SW2
IL1
SW1
SW2
IL1
SW1
SW2
IL1
SW1
SW2
IL1
SW1
SW2
IL1
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Figure 19. SW1, SW2, ILWaveforms: VIN = 18 V, VOUT = 12
V, IOUT = 0 A Figure 20. SW1, SW2, ILWaveforms: VIN = 18 V, VOUT = 12
V, IOUT = 5 A
Figure 21. SW1, SW2, ILWaveforms: VIN = 24 V, VOUT = 12
V, IOUT = 0 A Figure 22. SW1, SW2, ILWaveforms: VIN = 24 V, VOUT = 12 V, IOUT = 5 A
Figure 23. SW1, SW2, ILWaveforms: VIN = 42 V, VOUT = 12
V, IOUT = 0 A Figure 24. SW1, SW2, ILWaveforms: VIN = 42 V, VOUT = 12
V, IOUT = 5 A

VOUT
VIN
VOUT
VIN
VOUT
VIN
VOUT
VIN
VIN = 24V
VIN = 12V
VIN = 6V
VIN = 24V
VIN = 12V
VIN = 6V
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5.4.2 Output Voltage Ripple, 20-MHz Bandwidth
Figure 25. VOUT Ripple, IOUT = 0A Figure 26. VOUT Ripple, IOUT = 5A
5.4.3 Startup Waveform
Figure 27. Startup at VIN = 8 V, IOUT = 0A Figure 28. Startup at VIN = 8 V, IOUT = 4A
Figure 29. Startup at VIN = 12 V, IOUT = 0A Figure 30. Startup at VIN = 12 V, IOUT = 4A

VOUT
VIN
VOUT
VIN
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Figure 31. Startup at VIN = 24 V, IOUT = 0A Figure 32. Startup at VIN = 24 V, IOUT = 4A

GND
1µF
Cvcc
0.1µF
Cb1
0.1µF
Cb2
VCC
VOUT
L1
3.3uH
10.0
R3
GND
60.4k
RT1
200k
R8
10.0
R6
200k
R1
52.3k
R2
10µF
Co2
10µF
Co3
10µF
Co4
10µF
Cin6
10µF
Cin5
10µF
Cin4
GND
10µF
Cin3
68µF
Cin7
10µF
Co1
GND
10µF
Co5
0.047µF
Css
0
Rcd
VOUTSNS
HDRV1
LDRV2
SW1
PGOOD
BIAS
BOOT1
BOOT2
LDRV1
VIN 6V TO 42V
VIN
VIN_IC
EN
VISNS
MODE
DITH
SLOPE
SS
COMP
FB
GND
VOUT
12VDC @ 6A
GND
AGND
100pF
C1
220pF
Cc2
47pF
C13
D1
BAT54HT1G
VCC
10.0
R4
20.0k
Rpg
0.22µF
Cbias
68µF
Co7
HDRV2
SW2
0
Rh1
0
Rl1
Rs1
0.007
0.22µF
Cin8
100pF
C4
120pF
C5
0.022µF
Cc1
3.01k
Rc
7.15k
R10 100k
R12
4
7,8
1,2,3
5,6,
QH1
BSZ042N06NS 4
7,8
1,2,3
5,6,
QH2
BSZ0902NS
4
7,8
1,2,3
5,6,
QL1
BSZ042N06NS 4
7,8
1,2,3
5,6,
QL2
BSZ0902NS
100
R14
100
R13
100pF
C11
100pF
CT1
**FOR SPREAD SPECTRUM MODULATION (DITHER), REPLACE Rcd WITH 0.047µF CAPACITOR
10µF
Cin2
10µF
Cin1
10µF
Co6
GND
6.65k
R15
TRIM
SYNC
50
R16
LDRV1
SW1
LDRV2
SW1
LDRV1
HDRV1
HDRV1
HDRV2
SW2
HDRV2
SW2
LDRV2
10.0
R5
100pF
C14
SYNC
PGOOD
D2
BAS516,115
D3
BAS516,115
EN
GND
GND
GND
GND
GND
**
EN/UVLO
26
VIN
27
VINSNS
28
MODE
1
DITH
2
RT
3
SLOPE
4
SS
5
COMP
6
AGND 7
FB 8
VOSNS 9
ISNS- 10
ISNS+ 11
CSG 12
CS 13
PGOOD 14
SW2 15
HDRV2 16
BOOT2 17
LDRV2 18
PGND 19
VCC 20
BIAS 21
LDRV1 22
BOOT1 23
HDRV1 24
SW1 25
PAD 29
U1
LM5175RHFR
SYNC
0
R9
0
R11
VOUT
SS
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6 EVM Documentation
6.1 Schematic
Figure 33. EVM Schematic

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6.2 PCB Layout
Figure 34 through Figure 41 show the design of the LM5175 6-layer PCB with 2-oz copper thickness. The
EVM is a two-sided design, and it includes positions for input and output bulk capacitors.
Figure 34. Top Copper (Top View)
Figure 35. Layer 2 (Top View)

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Figure 36. Layer 3 (Top View)
Figure 37. Layer 4 (Top View)

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Figure 38. Layer 5 (Top View)
Figure 39. Bottom Copper (Bottom View)