Texas Instruments DAC8554EVM User manual

User's GuideSBAU121 – January 2006
DAC8554EVM User's Guide
This user’s guide describes the characteristics, operation and use of the DAC8554Evaluation Module (EVM). It covers all matters related to proper use and configurationof this EVM along with the devices that it supports. The physical printed circuit board(PCB) layout, schematic diagram and circuit descriptions are also included. For a moredetailed description of the DAC8554 , please refer to the product datasheet availablefrom the Texas Instruments web site at http://www.ti.com. Additional supportdocuments are listed in the section of this guide entitled Related Documentation fromTexas Instruments. Throughout this document, the acronym EVM and the phrasesevaluation module and demonstration board are synonymous with the DAC8554EVM.
Contents1 Overview ............................................................................................. 22 PCB Design and Performance .................................................................... 43 EVM Operation .................................................................................... 144 Schematic .......................................................................................... 20
List of Figures
1 DAC8554EVM Functional Block Diagram ....................................................... 32 DAC8554EVM PCB—Top Silkscreen Image ................................................... 53 DAC8554EVM PCB—Layer 1 (Top Signal Layer) ............................................. 54 DAC8554EVM PCB—Layer 2 (Ground Plane) ................................................. 65 DAC8554EVM PCB—Layer 3 (Power Plane) .................................................. 66 DAC8554EVM PCB—Layer 4 (Bottom Signal Layer) ......................................... 77 DAC8554EVM PCB—Bottom Silkscreen Image ............................................... 78 DAC8554EVM—Drill Drawing..................................................................... 89 INL and DNL Characterization Graph of DAC A ............................................... 910 INL and DNL Characterization Graph of DAC B .............................................. 1011 INL and DNL Characterization Graph of DAC C .............................................. 1112 INL and DNL Characterization Graph of DAC D .............................................. 12
List of Tables
1 DAC8554EVM Parts List ......................................................................... 132 Factory Default Jumper Settings ................................................................ 143 DAC Output Channel Mapping .................................................................. 154 Unity Gain Output Jumper Settings ............................................................. 165 Output Gain of 2 Jumper Settings .............................................................. 166 Capacitive Load Drive Output Jumper Settings ............................................... 177 Jumper Settings and Functions ................................................................. 17
LabVIEW is a trademark of National Instruments.All trademarks are the property of their respective owners.
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1 Overview
1.1 Features
1.2 Power Requirements
Overview
This section gives a general overview of the DAC8554EVM and describes some of the factors that mustbe considered when using this demonstration board.
The DAC8554EVM is a simple evaluation module designed for a quick and easy way to evaluate thefunctionality and performance of the high-resolution, quad-channel, serial input DAC8554 digital-to-analogconverter (DAC). This EVM features a serial interface to communicate with any host microprocessor or TIDSP-based system.
This subsection describes the power requirements for this device.
1.2.1 Supply Voltage
The DC power supply requirement for the digital section (V
DD
) of this EVM is typically +5V connected tothe J5-1 terminal or via the J3-10 terminal (when plugged in with another EVM board or interface card)and is referenced to ground through the J5-2 and J3-5 terminals. The DC power supply requirements forthe analog section of this EVM are: V
CC
and V
SS
range from +15.75V to –15.75V (maximum), connectingthrough J1-3 and J1-1 respectively, or through terminals J3-1 and J3-2. The +5V
A
connects throughterminals J5-3 or J3-3, and the +3.3V
A
connects through terminal J3-8. All of the analog power suppliesare referenced to analog ground through terminals J1-2 and J3-6.
The analog power supply for the device under test, U1, can be powered by either +5V
A
or +3.3V
A
byselecting the proper position of jumper JMP7. This configuration allows the DAC8554 analog section tooperate from either supply power while the I/O and digital section are powered by +5V, V
DD
.
The V
CC
supply source is primarily used to provide the positive rail of the external output op amp, U2, thereference chip, U3 and the reference buffer, U4. The negative rail of the output op amp, U2, can beselected between V
SS
and AGND via jumper JMP10. The external op amp is installed as an option toprovide output signal conditioning or to boost capacitive load drive, or for other desired output moderequirements.
CAUTIONTo avoid potential damage to the EVM board, be sure that the correctcables are connected to their respective terminals as labeled on the EVMboard. Stresses above the maximum listed voltage ratings may causepermanent damage to the device.
1.2.2 Reference Voltage
The +5V precision voltage reference is provided to supply the external voltage reference for the DACthrough the REF02 (U3) via jumper JMP8, by shorting pins 1 and 2. The reference voltage goes throughan adjustable 100k Ωpotentiometer, R15, in series with 20k Ω, R16, to allow the user to adjust thereference voltage to its desired settings. The voltage reference is then buffered through U4A as seen bythe device under test. The test points TP2, TP3 and TP4 are also provided, as well as J4-18 and J4-20, inorder to allow the user to connect another external reference source if the onboard reference circuit is notdesired. The external voltage reference should not exceed +5V DC.
The REF02 precision reference is powered by V
CC
(+15V) through either terminal J1-3 or J3-1.
CAUTIONWhen applying an external voltage reference through TP2 or J4-20, makesure that it does not exceed +5V maximum. External voltage references inexcess of +5V can permanently damage the DAC8554 being tested (U1).
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1.3 EVM Basic Functions
JMP11
JMP12
JMP13
JMP14
External
Reference
Module
+5VA
VDD
+3.3VA
(J2A)
(J2B)
DAC Module
(J4A)
(J4B) 8 CH
(J1)
(J5)
(J3A)
(J3B)
4 CH
JMP15
JMP16
JMP9
JMP10
DAC Out
VSS
V H
REF
TP4
TP3
VCC
GND
VSS
GND
VDD
+5VA
+3.3VA
A0
A1
EN
DIN
LDAC
SCLK
SYNC
JMP5
JMP6
JMP4
A0
JMP3
A1
JMP8
V H
REF
TP2
VSS
VCC
V L
REF
Output
Buffer
Module
Overview
The DAC8554EVM is designed to provide a demonstration platform for testing certain operationalcharacteristics of the DAC8554 digital-to-analog converter. Functional evaluation of the DAC8554 can beaccomplished with the use of any microprocessor, TI DSP or some sort of waveform generator.
Headers J2A (top side) and J2B (bottom side) are pass-through connectors provided to interface a hostprocessor or waveform generator with the DAC8554EVM using a custom-built cable. These connectorsenable the control signals and data to pass between the host and the device.
A mating adapter interface card (5-6k adapter interface) is also available to fit with TI’s TMS320C5000 andTMS320C6000 DSP Starter Kits (DSKs). This card resolves most of the trouble involved with building acustom cable. Additionally, there is also an MSP430-based platform (HPA449) that uses the MSP430F449microprocessor, to which this EVM can connect and interface as well. For more details or informationregarding the 5-6k adapter interface card or the HPA449 platform, please contact your Texas Instrumentsrepresentative, visit the TI web site or email the Data Converter Applications Support Team at[email protected].
The DAC outputs can be monitored through the selected pins of the J4 header connector. All outputs canbe switched through their respective jumpers—JMP11, JMP12, JMP13 and JMP14—for the purpose ofstacking. Stacking allows a total of eight DAC channels to be used, provided the A0 and A1 addresssignals are unique for each EVM board stacked.
In addition, the option of selecting one DAC output that can be fed to the noninverting side of the outputop amp, U2, is also possible by using a jumper across the selected pins of J4. The output op amp (U2)must first be correctly configured for the desired waveform characteristic. For more information, refer toSection 3 of this user’s guide.
A block diagram of the EVM is shown in Figure 1 .
Figure 1. DAC8554EVM Functional Block Diagram
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2 PCB Design and Performance
2.1 PCB Layout
PCB Design and Performance
1.3.1 Related Documentation from Texas Instruments
The following documents provide information regarding Texas Instrument integrated circuits used in theassembly of the DAC8554EVM. The latest revisions of these documents are available from the TI web siteat http://www.ti.com.
Data Sheet Literature NumberDAC8854 Datasheet SLAS431REF02 Datasheet SBVS003OPA627 Datasheet SBOS165OPA2132 Datasheet SBOS054
This section discusses the layout design of the DAC8554EVM PCB, describing the physical andmechanical characteristics of the EVM as well as a brief description of the demonstration board testperformance procedures performed. The list of components used in this evaluation module is alsoincluded.
The DAC8554EVM is designed to preserve the performance quality of the DAC8554, the device undertest (DUT), as specified in the data sheet. In order to take full advantage of the EVM capabilities, use careduring the schematic design phase to properly select the right components and to build the circuitcorrectly. The circuit design should include adequate bypassing, identifying and managing the analog anddigital signals, and understanding the components' electrical and mechanical attributes.
The primary design concerns during the layout process are optimal component placement and propersignal routing. Place the bypass capacitors as close as possible to the device pins, and properly separatethe analog and digital signals from each other. In the layout process, carefully consider the placement ofthe power and ground planes. A solid plane is ideal, but because of its greater cost, a split plane cansometimes be used satisfactorily. When considering a split plane design, analyze the componentplacement and carefully split the board into its analog and digital sections starting from the DUT. Theground plane plays an important role in controlling the noise and other effects that otherwise contribute tothe error of the DAC output. To ensure that the return currents are handled properly, route the appropriatesignals only in their respective sections, meaning that the analog traces should only lay directly above orbelow the analog section and the digital traces in the digital section. Minimize trace length, but use thelargest possible trace width allowable within the design. These design practices are illustrated in Figure 2through Figure 8 .
The DAC8554EVM board is constructed on a four-layer PCB using a copper-clad FR-4 laminate material.The PCB has a dimension of 43,1800mm (1.7000in) by 82,5500mm (3.2500in), and the board thickness is1,5748mm (0.062in). Figure 3 through Figure 7 show the individual artwork layers.
Note: Board layouts are not to scale. These are intended to show how the board is laid out; theyare not intended to be used for manufacturing DAC8554EVM PCBs.
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PCB Design and Performance
Figure 2. DAC8554EVM PCB—Top Silkscreen Image
Figure 3. DAC8554EVM PCB—Layer 1 (Top Signal Layer)
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PCB Design and Performance
Figure 4. DAC8554EVM PCB—Layer 2 (Ground Plane)
Figure 5. DAC8554EVM PCB—Layer 3 (Power Plane)
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PCB Design and Performance
Figure 6. DAC8554EVM PCB—Layer 4 (Bottom Signal Layer)
Figure 7. DAC8554EVM PCB—Bottom Silkscreen Image
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400mil
47.5mil
2700mil
3250mil
1300mil
1700mil
1247.5mil 1247.5mil
Notes:
1. PWB to be fabricated to meet or exceed IPC-6012
Class 3 standards and workmanship shall conform
to IPC-A-600, Class 3 - current revisions.
2. Board material and construction to be UL-Approved
and marked on the finished board.
3. Laminate material: Copper-Clad FR-4.
4. Copper weight: 1 oz. finished, all layers.
5. Finished thickness: .062 ±.010.
6. Min plating thickness in through holes: .001in.
7. SMOBC / HASL.
8. LPI soldermask both sides using appropriate
layer artwork, color = green.
9. LPI silkscreen as required: color = white.
10. Vendor information to be incorporated on back side
whenever possible.
11. Minimum copper conductor width is: 7 mils.
Minimum conductor spacing is: 7 mils.
12. Number of finished layers: 4.
13. Board dimensions: 3.250 in x 1.7 in.
50 15mil 0.381 mm PTH
43 23.622mil 0.6mm PTH
42 39.37mil 1mm PTH
5 40mil 1.016mm PTH
6 47.244mil 1.2mm PTH
1 63mil 1.6002mm PTH
147 total
2.2 EVM Performance
PCB Design and Performance
Figure 8. DAC8554EVM—Drill Drawing
The EVM performance test is executed using a high-density DAC bench test board, an Agilent 3458Adigital multimeter and a PC running LabVIEW™ software. The EVM board is tested for linearity for allcodes between 485 and 64741. The DUT is then allowed to settle for 1ms before the meter is read. Thisprocess is repeated for all codes to generate the measurements for INL and DNL.
Results of the DAC8554EVM tests are shown in Figure 9 through Figure 12 .
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PCB Design and Performance
Figure 9. INL and DNL Characterization Graph of DAC A
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PCB Design and Performance
Figure 10. INL and DNL Characterization Graph of DAC B
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PCB Design and Performance
Figure 11. INL and DNL Characterization Graph of DAC C
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PCB Design and Performance
Figure 12. INL and DNL Characterization Graph of DAC D
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2.3 Bill of Materials
PCB Design and Performance
The parts list, showing the components used in the assembly of the DAC8554EVM, is given in Table 1 .
Table 1. DAC8554EVM Parts ListQTY PER MFRITEM BOARD Ref Des MFR PART NUMBER DESCRIPTION
1 4 R11–R14 Panasonic ERJ-3GEY0R00V Chip Resistor, 0 Ω, 1/10W, 0603
2 1 R24 Panasonic ERJ-8GEYJ101V Chip Resistor, 100 Ω, 1/4W, 1206
Not
2 R5, R6 Panasonic ERJ-3GEYJ302V Chip Resistor, 3k Ω, 1/10W, 0603Installed
R1–R4, R7, R8,3 7 Panasonic ERJ-3EKF1002V Chip Resistor, 10k Ω, 1/16W, 0603R9
4 1 R16 Panasonic ERJ-3EKF2002V Chip Resistor, 20k Ω, 1/16W, 0603
5 1 R10 Bourns 3214W-1-203E Series 5T Pot., 20k Ω, BOURNS_32X4W
6 1 R15 Bourns 3214W-1-104E Series 5T Pot., 100k Ω, BOURNS_32X4W
Not
7 R17–R23 Panasonic Chip Resistor, 1/4W 1206Installed
7 1 C12 TDK C1608C0G1H102J Multilayer Ceramic Capacitor, 1nF, 0603 C0G
8 4 C4–C7 TDK C1608X7R1E104K Multilayer Ceramic Capacitor, 0.1 µF, 0603 X7R
9 2 C10, C11 TDK C2012X7R1E105K Multilayer Ceramic Capacitor, 1 µF, 0805 X7R
10 3 C1, C2, C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor, 10 µF, 1206 X7R
Not
2 C8, C9 TDK Multilayer Ceramic Capacitor, 1206Installed
16-bit, Quad Voltage Output, Serial Input DAC,11 1 U1 Texas Instruments DAC8554IPW
TSSOP-16
12 1 U2 Texas Instruments OPA627AU 8-SOP(D) Precision Op Amp
13 1 U3 Texas Instruments REF02AU +5V, 8-SOP(D) Precision Voltage Reference
14 1 U4 Texas Instruments OPA2132UA 8-SOP(D) Dual Precision Op Amp
Not
2 J1, J5 On-Shore Technology ED555/3DS 3-Pin Terminal ConnectorInstalled
15 2 J2A, J4A Samtec TSM-110-01-L-DV-P
SMT Header, 10x2x0.1, 20-pin, .025in
2
16 1 J3A Samtec TSM-105-01-L-DV-P
SMT Header, 5x2x0.1, 10-pin, .025in
2
17 2 J2B, J4B Samtec SSW-110-22-F-D-VS-K
SMT Socket, 10x2x0.1, 20-pin, .025in
2
18 1 J3B Samtec SSW-105-22-F-D-VS-K
SMT Socket, 5x2x0.1, 10-pin, .025in
2
19 6 JMP1–JMP6 Samtec TSW-102-07-G-S 2-position Jumper_ .1in spacing
20 10 JMP7–JMP16 Samtec TSW-103-07-G-S 3-position Jumper_ .1in spacing
21 1 TP4 Keystone Electronics 5011 Testpoint, Large-Loop
Not TP1, TP2, TP3,5 Keystone Electronics 5000 Testpoint, Mini-LoopInstalled TP5, TP6
22 16 N/A Samtec SNT-100-BK-G-H Shorting Block
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3 EVM Operation
3.1 Default Settings
3.2 Host Processor Interface
3.3 EVM Stacking
EVM Operation
This section covers the operation of the EVM in detail, in order to provide guidance to the user inevaluating the onboard DAC as well as how to interface the EVM to a specific host processor. Refer to theDAC8554 datasheet for information about its serial interface and other related topics. The EVM board isfactory-tested and configured.
The EVM is set to its factory default configuration as described in Table 2 to operate in 5V mode.
Table 2. Factory Default Jumper Settings
Reference Jumper Position Function
JMP1 CLOSE ENABLE pin is tied to DGNDJMP2 CLOSE LDAC pin is tied to DGND. Software LDAC is used.JMP3 CLOSE A1 pin is tied to DGND.JMP4 CLOSE A0 pin is tied to DGND.V
REF
H is not routed to the inverting input of the op amp for voltage offset withJMP5 OPEN
gain of 2 output.JMP6 OPEN Output op amp U2 is not configured for a gain of 2.JMP7 1-2 Analog supply for the DAC8554 is +5V
A
.JPM8 1-2 Onboard external buffered reference U3 is routed to V
REF
H.JMP9 1-2 V
REF
L is tied to AGND.JMP10 1-2 Negative supply rail of U2 op amp is supplied with V
SS
.JMP11 1-2 DAC output A (V
OUT
A) is routed to J4-2.JMP12 1-2 DAC output B (V
OUT
B) is routed to J4-4.JMP13 1-2 DAC output C (V
OUT
C) is routed to J4-6.JMP14 1-2 DAC output D (V
OUT
D) is routed to J4-8.JMP15 1-2 J4-1 is connected to the noninverting input of the output op amp U2.JMP16 1-2 J4-5 is connected to the output of the op amp U2.
The host processor drives the DAC. Thus, proper DAC operation depends on a successful configurationbetween the host processor and the EVM board. In addition, properly written code is also required tooperate the DAC.
As discussed earlier, a custom cable can be made specific to the host interface platform. The EVM allowsinterface to the host processor through header connector J2 for the serial control signals and the serialdata input. The output can be monitored through header connector J4.
An interface adapter card is also available for specific TI DSP DSKs as well as an MSP430-basedmicroprocessor (see Section 1.3 of this manual). Using the interface card alleviates the tedious task ofbuilding customized cables and allows easy configuration of a simple evaluation system.
The DAC8554 interfaces with any host processor capable of handling SPI protocols or the popular TIDSPs. For more information regarding the DAC8554 data interface, please refer to the DAC8554datasheet .
Stacking multiple EVMS is possible if there is a need to evaluate two DAC8554s, yielding a total of eightoutput channels. A maximum of two EVMs can be stacked since the output terminal, J4, dictates thenumber of DAC channels that can be connected without colliding. Table 3 shows how the DAC outputchannels are mapped into the output terminal, J4, with respect to the jumper positions of JMP11, JMP12,JMP13, and JMP14.
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3.4 Output Op Amp
EVM Operation
Table 3. DAC Output Channel Mapping
Reference Jumper Position Function
1-2 DAC output A (V
OUT
A) is routed to J4-2.JMP11
2-3 DAC output A (V
OUT
A) is routed to J4-10.1-2 DAC output B (V
OUT
B) is routed to J4-4.JMP12
2-3 DAC output B (V
OUT
B) is routed to J4-12.1-2 DAC output C (V
OUT
C) is routed to J4-6.JMP13
2-3 DAC output C (V
OUT
C) is routed to J4-14.1-2 DAC output D (V
OUT
D) is routed to J4-8.JMP14
2-3 DAC output D (V
OUT
D) is routed to J4-16.
In order to allow exclusive control of each EVM, different addresses must be selected for each DAC8554.This differentiation is accomplished by using JMP3 and JMP4 on the EVM. When sending data to theDAC8554, the address in the command byte must match the address of the device to be controlled.LDAC, SYNC and ENABLE control signals are shared. The DAC8554 only responds when the correctaddress is given.
The raw outputs of the DAC can be probed through the even numbered pins of J4, the output terminal,which also provides mechanical stability when stacking or plugging into any interface card. In addition, itprovides easy access for monitoring up to eight DAC channels when stacking two EVMs together.
The DAC8554EVM includes an optional signal conditioning circuit for the DAC output through an externaloperational amplifier, U2. The output op amp is set to unity gain configuration by default. Only one DACoutput channel can be monitored at any given time. JMP15 selects which pin of J4 is the input. Either J4-1or J4-3 can be used as the op amp signal input. The default setting for JMP15 selects J4-1. A shortingjumper can be placed between one of the DAC outputs and the op amp input. For example, a jumperacross J4-1 and J4-2 places the DAC A output as the input for the op amp if board jumpers are in thedefault position. If JMP15 is in the alternate position, then a shorting block between J4-3 and J4-2 makesthe DAC B output the input to the op amp.
The output of U2 passes through JMP16. In the default position, the output connects to J4-5. WhenJMP16 is in the alternate position, the output from U2 connects to J4-7. The output can be monitoredfrom, or passed to, another device from the J4 connector.
The jumper arrangement of JMP15 and JMP16 connecting to J4 allows U2 to be used in the stackedboard arrangement discussed above in Section 3.3 .
The following subsections describe the different configurations of the output amplifier, U2.
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EVM Operation
3.4.1 Unity Gain Output
The buffered output configuration can be used to prevent loading of the DAC8554, though it may addsome slight distortion because of the feedback resistor and capacitor. The feedback circuit can be alteredby simply desoldering R8 and C12 and replacing them with components of desired value. If desired, R8and C12 can be removed altogether by replacing R8 with a 0 Ωresistor.
Table 4 shows the jumper setting for the unity gain configuration of the DAC external output buffer inunipolar or bipolar mode.
Table 4. Unity Gain Output Jumper Settings
Jumper Setting
Reference Unipolar Bipolar Function
Disconnect V
REF
H from the inverting input of the opJMP5 Open Open
amp.
Supplies V
SS
to the negative rail of the op amp orJMP10 2-3 1-2
ties it to AGND.Disconnect negative input of op amp from the gainJMP6 Open Open
resistor, R9.
3.4.2 Output Gain of 2
There are two types of configurations that will yield an output gain of 2, depending on the setup of jumpersJMP5 and JMP6. These configurations allow the user to choose whether the DAC output will use V
REF
Has an offset. Table 5 shows the proper jumper settings of the EVM for the DAC8554 output gain of 2.
Table 5. Output Gain of 2 Jumper Settings
Jumper Setting
Reference Unipolar Bipolar Function
Inverting input of the output op amp U2 isClose Close connected to V
REF
H for use as its offset voltagewith a gain of 2. JMP6 must be open.JMP5
V
REF
H is disconnected from the inverting input ofOpen Open
the output op amp U2. JMP6 must be closed.Supplies power, V
SS
, to the negative rail of op ampJMP10 2-3 1-2 U2 for bipolar mode, or ties it to AGND for unipolarmode.
Configures op amp U2 for a gain of 2 outputClose Close
without a voltage offset. JMP5 must be open.JMP6
Inverting input of op amp U2 is disconnected fromOpen Open
the gain resistor, R9. JMP5 must be closed.
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3.5 Optional Signal Conditioning Op-Amp (U4B)
3.6 Jumper Settings
EVM Operation3.4.3 Capacitive Load Drive
It may be required to drive a wide range of capacitive loads. However, under certain conditions, all opamps may become unstable, depending on the op amp configuration, gain, and load value. These factorsare just few of the issues that can affect op amp stability and should be considered during implementation.
In unity gain configuration, the OPA627 op amp (U2) performs very well with very large capacitive loads.Increasing the gain enhances amplifier ability to drive even more capacitance, and adding a load resistoreven improves the capacitive load drive capability.
Table 6 shows the jumper setting configuration for a capacitive load drive.
Table 6. Capacitive Load Drive Output Jumper Settings
Jumper Setting
Reference Unipolar Bipolar Function
V
REF
H is disconnected from the inverting input ofJMP5 Open Open
the output op amp U2.Supplies power, V
SS
, to the negative rail of op ampJMP10 2-3 1-2 U2 for bipolar mode, or ties it to AGND for unipolarmode.
Capacitive load drive output of DAC is routed to pinJMP6 Open Open
2 of JMP6 and may be used as the output terminal.
One half of the OPA2132 dual package op amp (U4) is used for reference buffering (U4A), while the otherhalf is unused. This unused op amp (U4B) is left for whatever op amp circuit application the user desiresto implement. The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are notpopulated and are made available for easy configuration. Test points TP5 and TP6 are not installed, so itis up to the user on how to connect the ( ±) input signals to this op amp. No test point has been madeavailable for the output because of space restrictions, but a wire can be soldered to the output of the opamp via an unused component pad that connects to it. The op amp circuit can be configured by populatingthe corresponding components to those that match the circuit design while leaving all other unusedcomponent footprints unpopulated.
Table 7 shows the function of each specific jumper setting of the EVM.
Table 7. Jumper Settings and FunctionsReference Jumper Setting
(1)
Function
EN pin is set high through pull-up resistor R1. EN can be driven byGPIO2, J2-8.JMP1
EN pin is set low and DAC is enabled.
LDAC pin is set high through pull-up resistor R2. LDAC can be driven byGPIO0, J2-2.JMP2
LDAC pin is set low and DAC update is accomplished via software.
A1 pin is set high through pull-up resistor R3. A1 can be driven by GPIO4,J2-14.JMP3
A1 pin is set low.
(1)
Indicates the corresponding pins that are shorted or closed.
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13
13
13
13
13
13
13
13
13
13
EVM Operation
Table 7. Jumper Settings and Functions (continued)Reference Jumper Setting
(1)
Function
A0 pin is set high through pull-up resistor R4. A0 can be driven by GPIO5,J2-19.JMP4
A0 pin is set low.
Disconnects V
REF
H to the inverting input of the op amp U2.
JMP5
Connects V
REF
H to the inverting input of the op amp U2.
Disconnects the inverting input of the op amp U2 from the gain resistor,R9.JMP6
Connects the inverting input of the op amp U2 from the gain resistor, R9for output gain of 2.
+5V analog supply is selected for AV
DD
.
JMP7
+3.3V analog supply is selected for AV
DD
.
Routes the adjustable, buffered, onboard +5V reference to the V
REF
Hinput of the DAC8554.
JMP8
Routes the user-supplied reference from TP2 or J4-20 to the V
REF
H inputof the DAC8554.
V
REF
L is tied to AGND.
JMP9
Routes the user-supplied negative reference from TP3 or J4-18 to theV
REF
L input of the DAC8554. This voltage should be within the range of0V to V
REF
H.
Negative supply rail of the op amp U2 is powered by V
SS
for bipolaroperation.
JMP10
Negative supply rail of the op amp U2 is tied to AGND for unipolaroperation.
Routes V
OUT
A to J4-2.
JMP11
Routes V
OUT
A to J4-10.
DAC8554EVM User's Guide18 SBAU121 – January 2006

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13
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13
13
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EVM Operation
Table 7. Jumper Settings and Functions (continued)Reference Jumper Setting
(1)
Function
Routes V
OUT
B to J4-4.
JMP12
Routes V
OUT
B to J4-12.
Routes V
OUT
C to J4-6.
JMP13
Routes V
OUT
C to J4-14.
Routes V
OUT
D to J4-8.
JMP14
Routes V
OUT
D to J4-16.
Routes J4-1 to U2 noninverting input.
JMP15
Routes J4-3 to U2 noninverting input.
Routes U2 output to J4-5.
JMP16
Routes U2 output to J4-7.
SBAU121 – January 2006 DAC8554EVM User's Guide 19

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4 Schematic
Schematic
DAC8554EVM User's Guide20 SBAU121 – January 2006